2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
43 compatible = "arm,cortex-a8";
49 compatible = "fsl,imx-display-subsystem";
50 ports = <&ipu_di0>, <&ipu_di1>;
53 tzic: tz-interrupt-controller@0fffc000 {
54 compatible = "fsl,imx53-tzic", "fsl,tzic";
56 #interrupt-cells = <1>;
57 reg = <0x0fffc000 0x4000>;
65 compatible = "fsl,imx-ckil", "fixed-clock";
66 clock-frequency = <32768>;
70 compatible = "fsl,imx-ckih1", "fixed-clock";
71 clock-frequency = <22579200>;
75 compatible = "fsl,imx-ckih2", "fixed-clock";
76 clock-frequency = <0>;
80 compatible = "fsl,imx-osc", "fixed-clock";
81 clock-frequency = <24000000>;
88 compatible = "simple-bus";
89 interrupt-parent = <&tzic>;
95 compatible = "fsl,imx53-ipu";
96 reg = <0x18000000 0x080000000>;
98 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
99 clock-names = "bus", "di0", "di1";
103 #address-cells = <1>;
107 ipu_di0_disp0: endpoint@0 {
111 ipu_di0_lvds0: endpoint@1 {
113 remote-endpoint = <&lvds0_in>;
118 #address-cells = <1>;
122 ipu_di1_disp1: endpoint@0 {
126 ipu_di1_lvds1: endpoint@1 {
128 remote-endpoint = <&lvds1_in>;
131 ipu_di1_tve: endpoint@2 {
133 remote-endpoint = <&tve_in>;
138 aips@50000000 { /* AIPS1 */
139 compatible = "fsl,aips-bus", "simple-bus";
140 #address-cells = <1>;
142 reg = <0x50000000 0x10000000>;
146 compatible = "fsl,spba-bus", "simple-bus";
147 #address-cells = <1>;
149 reg = <0x50000000 0x40000>;
152 esdhc1: esdhc@50004000 {
153 compatible = "fsl,imx53-esdhc";
154 reg = <0x50004000 0x4000>;
156 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
157 clock-names = "ipg", "ahb", "per";
162 esdhc2: esdhc@50008000 {
163 compatible = "fsl,imx53-esdhc";
164 reg = <0x50008000 0x4000>;
166 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
167 clock-names = "ipg", "ahb", "per";
172 uart3: serial@5000c000 {
173 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
174 reg = <0x5000c000 0x4000>;
176 clocks = <&clks 32>, <&clks 33>;
177 clock-names = "ipg", "per";
181 ecspi1: ecspi@50010000 {
182 #address-cells = <1>;
184 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
185 reg = <0x50010000 0x4000>;
187 clocks = <&clks 51>, <&clks 52>;
188 clock-names = "ipg", "per";
193 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
194 reg = <0x50014000 0x4000>;
197 dmas = <&sdma 24 1 0>,
199 dma-names = "rx", "tx";
200 fsl,fifo-depth = <15>;
201 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
205 esdhc3: esdhc@50020000 {
206 compatible = "fsl,imx53-esdhc";
207 reg = <0x50020000 0x4000>;
209 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
210 clock-names = "ipg", "ahb", "per";
215 esdhc4: esdhc@50024000 {
216 compatible = "fsl,imx53-esdhc";
217 reg = <0x50024000 0x4000>;
219 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
220 clock-names = "ipg", "ahb", "per";
227 compatible = "usb-nop-xceiv";
228 clocks = <&clks 124>;
229 clock-names = "main_clk";
234 compatible = "usb-nop-xceiv";
235 clocks = <&clks 125>;
236 clock-names = "main_clk";
240 usbotg: usb@53f80000 {
241 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
242 reg = <0x53f80000 0x0200>;
244 clocks = <&clks 108>;
245 fsl,usbmisc = <&usbmisc 0>;
246 fsl,usbphy = <&usbphy0>;
250 usbh1: usb@53f80200 {
251 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
252 reg = <0x53f80200 0x0200>;
254 clocks = <&clks 108>;
255 fsl,usbmisc = <&usbmisc 1>;
256 fsl,usbphy = <&usbphy1>;
260 usbh2: usb@53f80400 {
261 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
262 reg = <0x53f80400 0x0200>;
264 clocks = <&clks 108>;
265 fsl,usbmisc = <&usbmisc 2>;
269 usbh3: usb@53f80600 {
270 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
271 reg = <0x53f80600 0x0200>;
273 clocks = <&clks 108>;
274 fsl,usbmisc = <&usbmisc 3>;
278 usbmisc: usbmisc@53f80800 {
280 compatible = "fsl,imx53-usbmisc";
281 reg = <0x53f80800 0x200>;
282 clocks = <&clks 108>;
285 gpio1: gpio@53f84000 {
286 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
287 reg = <0x53f84000 0x4000>;
288 interrupts = <50 51>;
291 interrupt-controller;
292 #interrupt-cells = <2>;
295 gpio2: gpio@53f88000 {
296 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
297 reg = <0x53f88000 0x4000>;
298 interrupts = <52 53>;
301 interrupt-controller;
302 #interrupt-cells = <2>;
305 gpio3: gpio@53f8c000 {
306 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
307 reg = <0x53f8c000 0x4000>;
308 interrupts = <54 55>;
311 interrupt-controller;
312 #interrupt-cells = <2>;
315 gpio4: gpio@53f90000 {
316 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
317 reg = <0x53f90000 0x4000>;
318 interrupts = <56 57>;
321 interrupt-controller;
322 #interrupt-cells = <2>;
325 wdog1: wdog@53f98000 {
326 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
327 reg = <0x53f98000 0x4000>;
332 wdog2: wdog@53f9c000 {
333 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
334 reg = <0x53f9c000 0x4000>;
340 gpt: timer@53fa0000 {
341 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
342 reg = <0x53fa0000 0x4000>;
344 clocks = <&clks 36>, <&clks 41>;
345 clock-names = "ipg", "per";
348 iomuxc: iomuxc@53fa8000 {
349 compatible = "fsl,imx53-iomuxc";
350 reg = <0x53fa8000 0x4000>;
353 pinctrl_audmux_1: audmuxgrp-1 {
355 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
356 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
357 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
358 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
362 pinctrl_audmux_2: audmuxgrp-2 {
364 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
365 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
366 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
367 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
371 pinctrl_audmux_3: audmuxgrp-3 {
373 MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000
374 MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000
375 MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000
376 MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000
382 pinctrl_fec_1: fecgrp-1 {
384 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
385 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
386 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
387 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
388 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
389 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
390 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
391 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
392 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
393 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
397 pinctrl_fec_2: fecgrp-2 {
399 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
400 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
401 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
402 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
403 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
404 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
405 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
406 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
407 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
408 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
409 MX53_PAD_KEY_ROW1__FEC_COL 0x80000000
410 MX53_PAD_KEY_COL3__FEC_CRS 0x80000000
411 MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000
412 MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000
413 MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000
414 MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000
415 MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000
416 MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000
422 pinctrl_csi_1: csigrp-1 {
424 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
425 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
426 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
427 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
428 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
429 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
430 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
431 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
432 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
433 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
434 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
435 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
436 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
437 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
438 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
439 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
440 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
441 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
442 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
443 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
444 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
448 pinctrl_csi_2: csigrp-2 {
450 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
451 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
452 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
453 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
454 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
455 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
456 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
457 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
458 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
459 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
460 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
466 pinctrl_cspi_1: cspigrp-1 {
468 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
469 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
470 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
474 pinctrl_cspi_2: cspigrp-2 {
476 MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
477 MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
478 MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
484 pinctrl_ecspi1_1: ecspi1grp-1 {
486 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
487 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
488 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
492 pinctrl_ecspi1_2: ecspi1grp-2 {
494 MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000
495 MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000
496 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
497 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
498 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
499 MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000
505 pinctrl_ecspi2_1: ecspi2grp-1 {
507 MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000
508 MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
509 MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
515 pinctrl_esdhc1_1: esdhc1grp-1 {
517 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
518 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
519 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
520 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
521 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
522 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
526 pinctrl_esdhc1_2: esdhc1grp-2 {
528 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
529 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
530 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
531 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
532 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
533 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
534 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
535 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
536 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
537 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
543 pinctrl_esdhc2_1: esdhc2grp-1 {
545 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
546 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
547 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
548 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
549 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
550 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
556 pinctrl_esdhc3_1: esdhc3grp-1 {
558 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
559 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
560 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
561 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
562 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
563 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
564 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
565 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
566 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
567 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
573 pinctrl_can1_1: can1grp-1 {
575 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
576 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
580 pinctrl_can1_2: can1grp-2 {
582 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
583 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
587 pinctrl_can1_3: can1grp-3 {
589 MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
590 MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
596 pinctrl_can2_1: can2grp-1 {
598 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
599 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
605 pinctrl_i2c1_1: i2c1grp-1 {
607 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
608 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
612 pinctrl_i2c1_2: i2c1grp-2 {
614 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
615 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
621 pinctrl_i2c2_1: i2c2grp-1 {
623 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
624 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
628 pinctrl_i2c2_2: i2c2grp-2 {
630 MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
631 MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
637 pinctrl_i2c3_1: i2c3grp-1 {
639 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
640 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
646 pinctrl_ipu_disp0_1: ipudisp0grp-1 {
648 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
649 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
650 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
651 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
652 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
653 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
654 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
655 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
656 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
657 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
658 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
659 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
660 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
661 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
662 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
663 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
664 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
665 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
666 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
667 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
668 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
669 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
670 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
671 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
672 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
673 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
674 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
675 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
681 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
683 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
684 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
685 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
686 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
687 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
688 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
689 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
690 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
691 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
692 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
693 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
694 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
695 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
696 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
697 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
698 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
699 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
700 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
701 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
702 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
703 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
704 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
705 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
706 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
707 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
708 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
709 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
710 MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
711 MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
712 MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
713 MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
714 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
720 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
722 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
723 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
724 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
725 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
726 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
727 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
728 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
729 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
730 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
731 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
737 pinctrl_nand_1: nandgrp-1 {
739 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
740 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
741 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
742 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
743 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
744 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
745 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
746 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
747 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
748 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
749 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
750 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
751 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
752 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
753 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
759 pinctrl_owire_1: owiregrp-1 {
761 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
767 pinctrl_pwm1_1: pwm1grp-1 {
769 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
775 pinctrl_pwm2_1: pwm2grp-1 {
777 MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000
783 pinctrl_uart1_1: uart1grp-1 {
785 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
786 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
790 pinctrl_uart1_2: uart1grp-2 {
792 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
793 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
797 pinctrl_uart1_3: uart1grp-3 {
799 MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
800 MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5
806 pinctrl_uart2_1: uart2grp-1 {
808 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
809 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
813 pinctrl_uart2_2: uart2grp-2 {
815 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
816 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
817 MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5
818 MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5
824 pinctrl_uart3_1: uart3grp-1 {
826 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
827 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
828 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
829 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
833 pinctrl_uart3_2: uart3grp-2 {
835 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
836 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
843 pinctrl_uart4_1: uart4grp-1 {
845 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
846 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
852 pinctrl_uart5_1: uart5grp-1 {
854 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4
855 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
861 gpr: iomuxc-gpr@53fa8000 {
862 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
863 reg = <0x53fa8000 0xc>;
867 #address-cells = <1>;
869 compatible = "fsl,imx53-ldb";
870 reg = <0x53fa8008 0x4>;
872 clocks = <&clks 122>, <&clks 120>,
873 <&clks 115>, <&clks 116>,
874 <&clks 123>, <&clks 85>;
875 clock-names = "di0_pll", "di1_pll",
876 "di0_sel", "di1_sel",
886 remote-endpoint = <&ipu_di0_lvds0>;
897 remote-endpoint = <&ipu_di0_lvds0>;
905 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
906 reg = <0x53fb4000 0x4000>;
907 clocks = <&clks 37>, <&clks 38>;
908 clock-names = "ipg", "per";
914 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
915 reg = <0x53fb8000 0x4000>;
916 clocks = <&clks 39>, <&clks 40>;
917 clock-names = "ipg", "per";
921 uart1: serial@53fbc000 {
922 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
923 reg = <0x53fbc000 0x4000>;
925 clocks = <&clks 28>, <&clks 29>;
926 clock-names = "ipg", "per";
930 uart2: serial@53fc0000 {
931 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
932 reg = <0x53fc0000 0x4000>;
934 clocks = <&clks 30>, <&clks 31>;
935 clock-names = "ipg", "per";
940 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
941 reg = <0x53fc8000 0x4000>;
943 clocks = <&clks 158>, <&clks 157>;
944 clock-names = "ipg", "per";
949 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
950 reg = <0x53fcc000 0x4000>;
952 clocks = <&clks 87>, <&clks 86>;
953 clock-names = "ipg", "per";
958 compatible = "fsl,imx53-src", "fsl,imx51-src";
959 reg = <0x53fd0000 0x4000>;
964 compatible = "fsl,imx53-ccm";
965 reg = <0x53fd4000 0x4000>;
966 interrupts = <0 71 0x04 0 72 0x04>;
970 gpio5: gpio@53fdc000 {
971 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
972 reg = <0x53fdc000 0x4000>;
973 interrupts = <103 104>;
976 interrupt-controller;
977 #interrupt-cells = <2>;
980 gpio6: gpio@53fe0000 {
981 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
982 reg = <0x53fe0000 0x4000>;
983 interrupts = <105 106>;
986 interrupt-controller;
987 #interrupt-cells = <2>;
990 gpio7: gpio@53fe4000 {
991 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
992 reg = <0x53fe4000 0x4000>;
993 interrupts = <107 108>;
996 interrupt-controller;
997 #interrupt-cells = <2>;
1000 i2c3: i2c@53fec000 {
1001 #address-cells = <1>;
1003 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
1004 reg = <0x53fec000 0x4000>;
1006 clocks = <&clks 88>;
1007 status = "disabled";
1010 uart4: serial@53ff0000 {
1011 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
1012 reg = <0x53ff0000 0x4000>;
1014 clocks = <&clks 65>, <&clks 66>;
1015 clock-names = "ipg", "per";
1016 status = "disabled";
1020 aips@60000000 { /* AIPS2 */
1021 compatible = "fsl,aips-bus", "simple-bus";
1022 #address-cells = <1>;
1024 reg = <0x60000000 0x10000000>;
1028 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
1029 reg = <0x63f98000 0x4000>;
1031 clocks = <&clks 107>;
1034 uart5: serial@63f90000 {
1035 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
1036 reg = <0x63f90000 0x4000>;
1038 clocks = <&clks 67>, <&clks 68>;
1039 clock-names = "ipg", "per";
1040 status = "disabled";
1043 owire: owire@63fa4000 {
1044 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
1045 reg = <0x63fa4000 0x4000>;
1046 clocks = <&clks 159>;
1047 status = "disabled";
1050 ecspi2: ecspi@63fac000 {
1051 #address-cells = <1>;
1053 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
1054 reg = <0x63fac000 0x4000>;
1056 clocks = <&clks 53>, <&clks 54>;
1057 clock-names = "ipg", "per";
1058 status = "disabled";
1061 sdma: sdma@63fb0000 {
1062 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
1063 reg = <0x63fb0000 0x4000>;
1065 clocks = <&clks 56>, <&clks 56>;
1066 clock-names = "ipg", "ahb";
1068 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
1071 cspi: cspi@63fc0000 {
1072 #address-cells = <1>;
1074 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
1075 reg = <0x63fc0000 0x4000>;
1077 clocks = <&clks 55>, <&clks 55>;
1078 clock-names = "ipg", "per";
1079 status = "disabled";
1082 i2c2: i2c@63fc4000 {
1083 #address-cells = <1>;
1085 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
1086 reg = <0x63fc4000 0x4000>;
1088 clocks = <&clks 35>;
1089 status = "disabled";
1092 i2c1: i2c@63fc8000 {
1093 #address-cells = <1>;
1095 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
1096 reg = <0x63fc8000 0x4000>;
1098 clocks = <&clks 34>;
1099 status = "disabled";
1102 ssi1: ssi@63fcc000 {
1103 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
1104 reg = <0x63fcc000 0x4000>;
1106 clocks = <&clks 48>;
1107 dmas = <&sdma 28 0 0>,
1109 dma-names = "rx", "tx";
1110 fsl,fifo-depth = <15>;
1111 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
1112 status = "disabled";
1115 audmux: audmux@63fd0000 {
1116 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
1117 reg = <0x63fd0000 0x4000>;
1118 status = "disabled";
1121 nfc: nand@63fdb000 {
1122 compatible = "fsl,imx53-nand";
1123 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
1125 clocks = <&clks 60>;
1126 status = "disabled";
1129 ssi3: ssi@63fe8000 {
1130 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
1131 reg = <0x63fe8000 0x4000>;
1133 clocks = <&clks 50>;
1134 dmas = <&sdma 46 0 0>,
1136 dma-names = "rx", "tx";
1137 fsl,fifo-depth = <15>;
1138 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
1139 status = "disabled";
1142 fec: ethernet@63fec000 {
1143 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
1144 reg = <0x63fec000 0x4000>;
1146 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
1147 clock-names = "ipg", "ahb", "ptp";
1148 status = "disabled";
1152 compatible = "fsl,imx53-tve";
1153 reg = <0x63ff0000 0x1000>;
1155 clocks = <&clks 69>, <&clks 116>;
1156 clock-names = "tve", "di_sel";
1157 status = "disabled";
1161 remote-endpoint = <&ipu_di1_tve>;
1167 compatible = "fsl,imx53-vpu";
1168 reg = <0x63ff4000 0x1000>;
1170 clocks = <&clks 63>, <&clks 63>;
1171 clock-names = "per", "ahb";
1173 status = "disabled";
1177 ocram: sram@f8000000 {
1178 compatible = "mmio-sram";
1179 reg = <0xf8000000 0x20000>;
1180 clocks = <&clks 186>;