2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
51 compatible = "arm,cortex-a8";
53 clocks = <&clks IMX5_CLK_ARM>;
54 clock-latency = <61036>;
55 voltage-tolerance = <5>;
68 compatible = "fsl,imx-display-subsystem";
69 ports = <&ipu_di0>, <&ipu_di1>;
72 tzic: tz-interrupt-controller@0fffc000 {
73 compatible = "fsl,imx53-tzic", "fsl,tzic";
75 #interrupt-cells = <1>;
76 reg = <0x0fffc000 0x4000>;
84 compatible = "fsl,imx-ckil", "fixed-clock";
86 clock-frequency = <32768>;
90 compatible = "fsl,imx-ckih1", "fixed-clock";
92 clock-frequency = <22579200>;
96 compatible = "fsl,imx-ckih2", "fixed-clock";
98 clock-frequency = <0>;
102 compatible = "fsl,imx-osc", "fixed-clock";
104 clock-frequency = <24000000>;
109 #address-cells = <1>;
111 compatible = "simple-bus";
112 interrupt-parent = <&tzic>;
115 sata: sata@10000000 {
116 compatible = "fsl,imx53-ahci";
117 reg = <0x10000000 0x1000>;
119 clocks = <&clks IMX5_CLK_SATA_GATE>,
120 <&clks IMX5_CLK_SATA_REF>,
121 <&clks IMX5_CLK_AHB>;
122 clock-names = "sata", "sata_ref", "ahb";
127 #address-cells = <1>;
129 compatible = "fsl,imx53-ipu";
130 reg = <0x18000000 0x08000000>;
131 interrupts = <11 10>;
132 clocks = <&clks IMX5_CLK_IPU_GATE>,
133 <&clks IMX5_CLK_IPU_DI0_GATE>,
134 <&clks IMX5_CLK_IPU_DI1_GATE>;
135 clock-names = "bus", "di0", "di1";
139 #address-cells = <1>;
143 ipu_di0_disp0: endpoint@0 {
147 ipu_di0_lvds0: endpoint@1 {
149 remote-endpoint = <&lvds0_in>;
154 #address-cells = <1>;
158 ipu_di1_disp1: endpoint@0 {
162 ipu_di1_lvds1: endpoint@1 {
164 remote-endpoint = <&lvds1_in>;
167 ipu_di1_tve: endpoint@2 {
169 remote-endpoint = <&tve_in>;
174 aips@50000000 { /* AIPS1 */
175 compatible = "fsl,aips-bus", "simple-bus";
176 #address-cells = <1>;
178 reg = <0x50000000 0x10000000>;
182 compatible = "fsl,spba-bus", "simple-bus";
183 #address-cells = <1>;
185 reg = <0x50000000 0x40000>;
188 esdhc1: esdhc@50004000 {
189 compatible = "fsl,imx53-esdhc";
190 reg = <0x50004000 0x4000>;
192 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
193 <&clks IMX5_CLK_DUMMY>,
194 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
195 clock-names = "ipg", "ahb", "per";
200 esdhc2: esdhc@50008000 {
201 compatible = "fsl,imx53-esdhc";
202 reg = <0x50008000 0x4000>;
204 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
205 <&clks IMX5_CLK_DUMMY>,
206 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
207 clock-names = "ipg", "ahb", "per";
212 uart3: serial@5000c000 {
213 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
214 reg = <0x5000c000 0x4000>;
216 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
217 <&clks IMX5_CLK_UART3_PER_GATE>;
218 clock-names = "ipg", "per";
222 ecspi1: ecspi@50010000 {
223 #address-cells = <1>;
225 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
226 reg = <0x50010000 0x4000>;
228 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
229 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
230 clock-names = "ipg", "per";
235 #sound-dai-cells = <0>;
236 compatible = "fsl,imx53-ssi",
239 reg = <0x50014000 0x4000>;
241 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
242 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
243 clock-names = "ipg", "baud";
244 dmas = <&sdma 24 1 0>,
246 dma-names = "rx", "tx";
247 fsl,fifo-depth = <15>;
251 esdhc3: esdhc@50020000 {
252 compatible = "fsl,imx53-esdhc";
253 reg = <0x50020000 0x4000>;
255 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
256 <&clks IMX5_CLK_DUMMY>,
257 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
258 clock-names = "ipg", "ahb", "per";
263 esdhc4: esdhc@50024000 {
264 compatible = "fsl,imx53-esdhc";
265 reg = <0x50024000 0x4000>;
267 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
268 <&clks IMX5_CLK_DUMMY>,
269 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
270 clock-names = "ipg", "ahb", "per";
276 aipstz1: bridge@53f00000 {
277 compatible = "fsl,imx53-aipstz";
278 reg = <0x53f00000 0x60>;
282 compatible = "usb-nop-xceiv";
283 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
284 clock-names = "main_clk";
289 compatible = "usb-nop-xceiv";
290 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
291 clock-names = "main_clk";
295 usbotg: usb@53f80000 {
296 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
297 reg = <0x53f80000 0x0200>;
299 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
300 fsl,usbmisc = <&usbmisc 0>;
301 fsl,usbphy = <&usbphy0>;
305 usbh1: usb@53f80200 {
306 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
307 reg = <0x53f80200 0x0200>;
309 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
310 fsl,usbmisc = <&usbmisc 1>;
311 fsl,usbphy = <&usbphy1>;
315 usbh2: usb@53f80400 {
316 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
317 reg = <0x53f80400 0x0200>;
319 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
320 fsl,usbmisc = <&usbmisc 2>;
324 usbh3: usb@53f80600 {
325 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
326 reg = <0x53f80600 0x0200>;
328 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
329 fsl,usbmisc = <&usbmisc 3>;
333 usbmisc: usbmisc@53f80800 {
335 compatible = "fsl,imx53-usbmisc";
336 reg = <0x53f80800 0x200>;
337 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
340 gpio1: gpio@53f84000 {
341 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
342 reg = <0x53f84000 0x4000>;
343 interrupts = <50 51>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
350 gpio2: gpio@53f88000 {
351 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
352 reg = <0x53f88000 0x4000>;
353 interrupts = <52 53>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
360 gpio3: gpio@53f8c000 {
361 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
362 reg = <0x53f8c000 0x4000>;
363 interrupts = <54 55>;
366 interrupt-controller;
367 #interrupt-cells = <2>;
370 gpio4: gpio@53f90000 {
371 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
372 reg = <0x53f90000 0x4000>;
373 interrupts = <56 57>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
381 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
382 reg = <0x53f94000 0x4000>;
384 clocks = <&clks IMX5_CLK_DUMMY>;
388 wdog1: wdog@53f98000 {
389 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
390 reg = <0x53f98000 0x4000>;
392 clocks = <&clks IMX5_CLK_DUMMY>;
395 wdog2: wdog@53f9c000 {
396 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
397 reg = <0x53f9c000 0x4000>;
399 clocks = <&clks IMX5_CLK_DUMMY>;
403 gpt: timer@53fa0000 {
404 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
405 reg = <0x53fa0000 0x4000>;
407 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
408 <&clks IMX5_CLK_GPT_HF_GATE>;
409 clock-names = "ipg", "per";
412 iomuxc: iomuxc@53fa8000 {
413 compatible = "fsl,imx53-iomuxc";
414 reg = <0x53fa8000 0x4000>;
417 gpr: iomuxc-gpr@53fa8000 {
418 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
419 reg = <0x53fa8000 0xc>;
423 #address-cells = <1>;
425 compatible = "fsl,imx53-ldb";
426 reg = <0x53fa8008 0x4>;
428 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
429 <&clks IMX5_CLK_LDB_DI1_SEL>,
430 <&clks IMX5_CLK_IPU_DI0_SEL>,
431 <&clks IMX5_CLK_IPU_DI1_SEL>,
432 <&clks IMX5_CLK_LDB_DI0_GATE>,
433 <&clks IMX5_CLK_LDB_DI1_GATE>;
434 clock-names = "di0_pll", "di1_pll",
435 "di0_sel", "di1_sel",
440 #address-cells = <1>;
449 remote-endpoint = <&ipu_di0_lvds0>;
455 #address-cells = <1>;
464 remote-endpoint = <&ipu_di1_lvds1>;
472 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
473 reg = <0x53fb4000 0x4000>;
474 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
475 <&clks IMX5_CLK_PWM1_HF_GATE>;
476 clock-names = "ipg", "per";
482 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
483 reg = <0x53fb8000 0x4000>;
484 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
485 <&clks IMX5_CLK_PWM2_HF_GATE>;
486 clock-names = "ipg", "per";
490 uart1: serial@53fbc000 {
491 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
492 reg = <0x53fbc000 0x4000>;
494 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
495 <&clks IMX5_CLK_UART1_PER_GATE>;
496 clock-names = "ipg", "per";
500 uart2: serial@53fc0000 {
501 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
502 reg = <0x53fc0000 0x4000>;
504 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
505 <&clks IMX5_CLK_UART2_PER_GATE>;
506 clock-names = "ipg", "per";
511 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
512 reg = <0x53fc8000 0x4000>;
514 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
515 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
516 clock-names = "ipg", "per";
521 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
522 reg = <0x53fcc000 0x4000>;
524 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
525 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
526 clock-names = "ipg", "per";
531 compatible = "fsl,imx53-src", "fsl,imx51-src";
532 reg = <0x53fd0000 0x4000>;
537 compatible = "fsl,imx53-ccm";
538 reg = <0x53fd4000 0x4000>;
539 interrupts = <0 71 0x04 0 72 0x04>;
543 gpio5: gpio@53fdc000 {
544 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
545 reg = <0x53fdc000 0x4000>;
546 interrupts = <103 104>;
549 interrupt-controller;
550 #interrupt-cells = <2>;
553 gpio6: gpio@53fe0000 {
554 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
555 reg = <0x53fe0000 0x4000>;
556 interrupts = <105 106>;
559 interrupt-controller;
560 #interrupt-cells = <2>;
563 gpio7: gpio@53fe4000 {
564 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
565 reg = <0x53fe4000 0x4000>;
566 interrupts = <107 108>;
569 interrupt-controller;
570 #interrupt-cells = <2>;
574 #address-cells = <1>;
576 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
577 reg = <0x53fec000 0x4000>;
579 clocks = <&clks IMX5_CLK_I2C3_GATE>;
583 uart4: serial@53ff0000 {
584 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
585 reg = <0x53ff0000 0x4000>;
587 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
588 <&clks IMX5_CLK_UART4_PER_GATE>;
589 clock-names = "ipg", "per";
594 aips@60000000 { /* AIPS2 */
595 compatible = "fsl,aips-bus", "simple-bus";
596 #address-cells = <1>;
598 reg = <0x60000000 0x10000000>;
601 aipstz2: bridge@63f00000 {
602 compatible = "fsl,imx53-aipstz";
603 reg = <0x63f00000 0x60>;
607 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
608 reg = <0x63f98000 0x4000>;
610 clocks = <&clks IMX5_CLK_IIM_GATE>;
613 uart5: serial@63f90000 {
614 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
615 reg = <0x63f90000 0x4000>;
617 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
618 <&clks IMX5_CLK_UART5_PER_GATE>;
619 clock-names = "ipg", "per";
623 owire: owire@63fa4000 {
624 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
625 reg = <0x63fa4000 0x4000>;
626 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
630 ecspi2: ecspi@63fac000 {
631 #address-cells = <1>;
633 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
634 reg = <0x63fac000 0x4000>;
636 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
637 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
638 clock-names = "ipg", "per";
642 sdma: sdma@63fb0000 {
643 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
644 reg = <0x63fb0000 0x4000>;
646 clocks = <&clks IMX5_CLK_SDMA_GATE>,
647 <&clks IMX5_CLK_SDMA_GATE>;
648 clock-names = "ipg", "ahb";
650 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
653 cspi: cspi@63fc0000 {
654 #address-cells = <1>;
656 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
657 reg = <0x63fc0000 0x4000>;
659 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
660 <&clks IMX5_CLK_CSPI_IPG_GATE>;
661 clock-names = "ipg", "per";
666 #address-cells = <1>;
668 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
669 reg = <0x63fc4000 0x4000>;
671 clocks = <&clks IMX5_CLK_I2C2_GATE>;
676 #address-cells = <1>;
678 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
679 reg = <0x63fc8000 0x4000>;
681 clocks = <&clks IMX5_CLK_I2C1_GATE>;
686 #sound-dai-cells = <0>;
687 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
689 reg = <0x63fcc000 0x4000>;
691 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
692 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
693 clock-names = "ipg", "baud";
694 dmas = <&sdma 28 0 0>,
696 dma-names = "rx", "tx";
697 fsl,fifo-depth = <15>;
701 audmux: audmux@63fd0000 {
702 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
703 reg = <0x63fd0000 0x4000>;
708 compatible = "fsl,imx53-nand";
709 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
711 clocks = <&clks IMX5_CLK_NFC_GATE>;
716 #sound-dai-cells = <0>;
717 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
719 reg = <0x63fe8000 0x4000>;
721 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
722 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
723 clock-names = "ipg", "baud";
724 dmas = <&sdma 46 0 0>,
726 dma-names = "rx", "tx";
727 fsl,fifo-depth = <15>;
731 fec: ethernet@63fec000 {
732 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
733 reg = <0x63fec000 0x4000>;
735 clocks = <&clks IMX5_CLK_FEC_GATE>,
736 <&clks IMX5_CLK_FEC_GATE>,
737 <&clks IMX5_CLK_FEC_GATE>;
738 clock-names = "ipg", "ahb", "ptp";
743 compatible = "fsl,imx53-tve";
744 reg = <0x63ff0000 0x1000>;
746 clocks = <&clks IMX5_CLK_TVE_GATE>,
747 <&clks IMX5_CLK_IPU_DI1_SEL>;
748 clock-names = "tve", "di_sel";
753 remote-endpoint = <&ipu_di1_tve>;
759 compatible = "fsl,imx53-vpu", "cnm,coda7541";
760 reg = <0x63ff4000 0x1000>;
762 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
763 <&clks IMX5_CLK_VPU_GATE>;
764 clock-names = "per", "ahb";
769 sahara: crypto@63ff8000 {
770 compatible = "fsl,imx53-sahara";
771 reg = <0x63ff8000 0x4000>;
772 interrupts = <19 20>;
773 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
774 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
775 clock-names = "ipg", "ahb";
779 ocram: sram@f8000000 {
780 compatible = "mmio-sram";
781 reg = <0xf8000000 0x20000>;
782 clocks = <&clks IMX5_CLK_OCRAM>;
786 compatible = "arm,cortex-a8-pmu";