arch/arm/boot/dts/imx53.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14 #include "imx53-pinfunc.h"
  15
  16 / {
  17         aliases {
  18                 gpio0 = &gpio1;
  19                 gpio1 = &gpio2;
  20                 gpio2 = &gpio3;
  21                 gpio3 = &gpio4;
  22                 gpio4 = &gpio5;
  23                 gpio5 = &gpio6;
  24                 gpio6 = &gpio7;
  25                 i2c0 = &i2c1;
  26                 i2c1 = &i2c2;
  27                 i2c2 = &i2c3;
  28                 serial0 = &uart1;
  29                 serial1 = &uart2;
  30                 serial2 = &uart3;
  31                 serial3 = &uart4;
  32                 serial4 = &uart5;
  33                 spi0 = &ecspi1;
  34                 spi1 = &ecspi2;
  35                 spi2 = &cspi;
  36         };
  37
  38         cpus {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41                 cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a8";
  44                         reg = <0x0>;
  45                 };
  46         };
  47
  48         tzic: tz-interrupt-controller@0fffc000 {
  49                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  50                 interrupt-controller;
  51                 #interrupt-cells = <1>;
  52                 reg = <0x0fffc000 0x4000>;
  53         };
  54
  55         clocks {
  56                 #address-cells = <1>;
  57                 #size-cells = <0>;
  58
  59                 ckil {
  60                         compatible = "fsl,imx-ckil", "fixed-clock";
  61                         clock-frequency = <32768>;
  62                 };
  63
  64                 ckih1 {
  65                         compatible = "fsl,imx-ckih1", "fixed-clock";
  66                         clock-frequency = <22579200>;
  67                 };
  68
  69                 ckih2 {
  70                         compatible = "fsl,imx-ckih2", "fixed-clock";
  71                         clock-frequency = <0>;
  72                 };
  73
  74                 osc {
  75                         compatible = "fsl,imx-osc", "fixed-clock";
  76                         clock-frequency = <24000000>;
  77                 };
  78         };
  79
  80         soc {
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 compatible = "simple-bus";
  84                 interrupt-parent = <&tzic>;
  85                 ranges;
  86
  87                 ipu: ipu@18000000 {
  88                         #crtc-cells = <1>;
  89                         compatible = "fsl,imx53-ipu";
  90                         reg = <0x18000000 0x080000000>;
  91                         interrupts = <11 10>;
  92                         clocks = <&clks 59>, <&clks 110>, <&clks 61>;
  93                         clock-names = "bus", "di0", "di1";
  94                         resets = <&src 2>;
  95                 };
  96
  97                 aips@50000000 { /* AIPS1 */
  98                         compatible = "fsl,aips-bus", "simple-bus";
  99                         #address-cells = <1>;
 100                         #size-cells = <1>;
 101                         reg = <0x50000000 0x10000000>;
 102                         ranges;
 103
 104                         spba@50000000 {
 105                                 compatible = "fsl,spba-bus", "simple-bus";
 106                                 #address-cells = <1>;
 107                                 #size-cells = <1>;
 108                                 reg = <0x50000000 0x40000>;
 109                                 ranges;
 110
 111                                 esdhc1: esdhc@50004000 {
 112                                         compatible = "fsl,imx53-esdhc";
 113                                         reg = <0x50004000 0x4000>;
 114                                         interrupts = <1>;
 115                                         clocks = <&clks 44>, <&clks 0>, <&clks 71>;
 116                                         clock-names = "ipg", "ahb", "per";
 117                                         bus-width = <4>;
 118                                         status = "disabled";
 119                                 };
 120
 121                                 esdhc2: esdhc@50008000 {
 122                                         compatible = "fsl,imx53-esdhc";
 123                                         reg = <0x50008000 0x4000>;
 124                                         interrupts = <2>;
 125                                         clocks = <&clks 45>, <&clks 0>, <&clks 72>;
 126                                         clock-names = "ipg", "ahb", "per";
 127                                         bus-width = <4>;
 128                                         status = "disabled";
 129                                 };
 130
 131                                 uart3: serial@5000c000 {
 132                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 133                                         reg = <0x5000c000 0x4000>;
 134                                         interrupts = <33>;
 135                                         clocks = <&clks 32>, <&clks 33>;
 136                                         clock-names = "ipg", "per";
 137                                         status = "disabled";
 138                                 };
 139
 140                                 ecspi1: ecspi@50010000 {
 141                                         #address-cells = <1>;
 142                                         #size-cells = <0>;
 143                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 144                                         reg = <0x50010000 0x4000>;
 145                                         interrupts = <36>;
 146                                         clocks = <&clks 51>, <&clks 52>;
 147                                         clock-names = "ipg", "per";
 148                                         status = "disabled";
 149                                 };
 150
 151                                 ssi2: ssi@50014000 {
 152                                         compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 153                                         reg = <0x50014000 0x4000>;
 154                                         interrupts = <30>;
 155                                         clocks = <&clks 49>;
 156                                         fsl,fifo-depth = <15>;
 157                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 158                                         status = "disabled";
 159                                 };
 160
 161                                 esdhc3: esdhc@50020000 {
 162                                         compatible = "fsl,imx53-esdhc";
 163                                         reg = <0x50020000 0x4000>;
 164                                         interrupts = <3>;
 165                                         clocks = <&clks 46>, <&clks 0>, <&clks 73>;
 166                                         clock-names = "ipg", "ahb", "per";
 167                                         bus-width = <4>;
 168                                         status = "disabled";
 169                                 };
 170
 171                                 esdhc4: esdhc@50024000 {
 172                                         compatible = "fsl,imx53-esdhc";
 173                                         reg = <0x50024000 0x4000>;
 174                                         interrupts = <4>;
 175                                         clocks = <&clks 47>, <&clks 0>, <&clks 74>;
 176                                         clock-names = "ipg", "ahb", "per";
 177                                         bus-width = <4>;
 178                                         status = "disabled";
 179                                 };
 180                         };
 181
 182                         usbphy0: usbphy@0 {
 183                                 compatible = "usb-nop-xceiv";
 184                                 clocks = <&clks 124>;
 185                                 clock-names = "main_clk";
 186                                 status = "okay";
 187                         };
 188
 189                         usbphy1: usbphy@1 {
 190                                 compatible = "usb-nop-xceiv";
 191                                 clocks = <&clks 125>;
 192                                 clock-names = "main_clk";
 193                                 status = "okay";
 194                         };
 195
 196                         usbotg: usb@53f80000 {
 197                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 198                                 reg = <0x53f80000 0x0200>;
 199                                 interrupts = <18>;
 200                                 clocks = <&clks 108>;
 201                                 fsl,usbmisc = <&usbmisc 0>;
 202                                 fsl,usbphy = <&usbphy0>;
 203                                 status = "disabled";
 204                         };
 205
 206                         usbh1: usb@53f80200 {
 207                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 208                                 reg = <0x53f80200 0x0200>;
 209                                 interrupts = <14>;
 210                                 clocks = <&clks 108>;
 211                                 fsl,usbmisc = <&usbmisc 1>;
 212                                 fsl,usbphy = <&usbphy1>;
 213                                 status = "disabled";
 214                         };
 215
 216                         usbh2: usb@53f80400 {
 217                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 218                                 reg = <0x53f80400 0x0200>;
 219                                 interrupts = <16>;
 220                                 clocks = <&clks 108>;
 221                                 fsl,usbmisc = <&usbmisc 2>;
 222                                 status = "disabled";
 223                         };
 224
 225                         usbh3: usb@53f80600 {
 226                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 227                                 reg = <0x53f80600 0x0200>;
 228                                 interrupts = <17>;
 229                                 clocks = <&clks 108>;
 230                                 fsl,usbmisc = <&usbmisc 3>;
 231                                 status = "disabled";
 232                         };
 233
 234                         usbmisc: usbmisc@53f80800 {
 235                                 #index-cells = <1>;
 236                                 compatible = "fsl,imx53-usbmisc";
 237                                 reg = <0x53f80800 0x200>;
 238                                 clocks = <&clks 108>;
 239                         };
 240
 241                         gpio1: gpio@53f84000 {
 242                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 243                                 reg = <0x53f84000 0x4000>;
 244                                 interrupts = <50 51>;
 245                                 gpio-controller;
 246                                 #gpio-cells = <2>;
 247                                 interrupt-controller;
 248                                 #interrupt-cells = <2>;
 249                         };
 250
 251                         gpio2: gpio@53f88000 {
 252                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 253                                 reg = <0x53f88000 0x4000>;
 254                                 interrupts = <52 53>;
 255                                 gpio-controller;
 256                                 #gpio-cells = <2>;
 257                                 interrupt-controller;
 258                                 #interrupt-cells = <2>;
 259                         };
 260
 261                         gpio3: gpio@53f8c000 {
 262                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 263                                 reg = <0x53f8c000 0x4000>;
 264                                 interrupts = <54 55>;
 265                                 gpio-controller;
 266                                 #gpio-cells = <2>;
 267                                 interrupt-controller;
 268                                 #interrupt-cells = <2>;
 269                         };
 270
 271                         gpio4: gpio@53f90000 {
 272                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 273                                 reg = <0x53f90000 0x4000>;
 274                                 interrupts = <56 57>;
 275                                 gpio-controller;
 276                                 #gpio-cells = <2>;
 277                                 interrupt-controller;
 278                                 #interrupt-cells = <2>;
 279                         };
 280
 281                         wdog1: wdog@53f98000 {
 282                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 283                                 reg = <0x53f98000 0x4000>;
 284                                 interrupts = <58>;
 285                                 clocks = <&clks 0>;
 286                         };
 287
 288                         wdog2: wdog@53f9c000 {
 289                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 290                                 reg = <0x53f9c000 0x4000>;
 291                                 interrupts = <59>;
 292                                 clocks = <&clks 0>;
 293                                 status = "disabled";
 294                         };
 295
 296                         gpt: timer@53fa0000 {
 297                                 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
 298                                 reg = <0x53fa0000 0x4000>;
 299                                 interrupts = <39>;
 300                                 clocks = <&clks 36>, <&clks 41>;
 301                                 clock-names = "ipg", "per";
 302                         };
 303
 304                         iomuxc: iomuxc@53fa8000 {
 305                                 compatible = "fsl,imx53-iomuxc";
 306                                 reg = <0x53fa8000 0x4000>;
 307
 308                                 audmux {
 309                                         pinctrl_audmux_1: audmuxgrp-1 {
 310                                                 fsl,pins = <
 311                                                         MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC  0x80000000
 312                                                         MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD  0x80000000
 313                                                         MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
 314                                                         MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x80000000
 315                                                 >;
 316                                         };
 317
 318                                         pinctrl_audmux_2: audmuxgrp-2 {
 319                                                 fsl,pins = <
 320                                                         MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC     0x80000000
 321                                                         MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD     0x80000000
 322                                                         MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS    0x80000000
 323                                                         MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD     0x80000000
 324                                                 >;
 325                                         };
 326
 327                                         pinctrl_audmux_3: audmuxgrp-3 {
 328                                                 fsl,pins = <
 329                                                         MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC     0x80000000
 330                                                         MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD     0x80000000
 331                                                         MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS    0x80000000
 332                                                         MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD     0x80000000
 333                                                 >;
 334                                         };
 335                                 };
 336
 337                                 fec {
 338                                         pinctrl_fec_1: fecgrp-1 {
 339                                                 fsl,pins = <
 340                                                         MX53_PAD_FEC_MDC__FEC_MDC        0x80000000
 341                                                         MX53_PAD_FEC_MDIO__FEC_MDIO      0x80000000
 342                                                         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
 343                                                         MX53_PAD_FEC_RX_ER__FEC_RX_ER    0x80000000
 344                                                         MX53_PAD_FEC_CRS_DV__FEC_RX_DV   0x80000000
 345                                                         MX53_PAD_FEC_RXD1__FEC_RDATA_1   0x80000000
 346                                                         MX53_PAD_FEC_RXD0__FEC_RDATA_0   0x80000000
 347                                                         MX53_PAD_FEC_TX_EN__FEC_TX_EN    0x80000000
 348                                                         MX53_PAD_FEC_TXD1__FEC_TDATA_1   0x80000000
 349                                                         MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
 350                                                 >;
 351                                         };
 352
 353                                         pinctrl_fec_2: fecgrp-2 {
 354                                                 fsl,pins = <
 355                                                         MX53_PAD_FEC_MDC__FEC_MDC        0x80000000
 356                                                         MX53_PAD_FEC_MDIO__FEC_MDIO      0x80000000
 357                                                         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
 358                                                         MX53_PAD_FEC_RX_ER__FEC_RX_ER    0x80000000
 359                                                         MX53_PAD_FEC_CRS_DV__FEC_RX_DV   0x80000000
 360                                                         MX53_PAD_FEC_RXD1__FEC_RDATA_1   0x80000000
 361                                                         MX53_PAD_FEC_RXD0__FEC_RDATA_0   0x80000000
 362                                                         MX53_PAD_FEC_TX_EN__FEC_TX_EN    0x80000000
 363                                                         MX53_PAD_FEC_TXD1__FEC_TDATA_1   0x80000000
 364                                                         MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
 365                                                         MX53_PAD_KEY_ROW1__FEC_COL       0x80000000
 366                                                         MX53_PAD_KEY_COL3__FEC_CRS       0x80000000
 367                                                         MX53_PAD_KEY_COL2__FEC_RDATA_2   0x80000000
 368                                                         MX53_PAD_KEY_COL0__FEC_RDATA_3   0x80000000
 369                                                         MX53_PAD_KEY_COL1__FEC_RX_CLK    0x80000000
 370                                                         MX53_PAD_KEY_ROW2__FEC_TDATA_2   0x80000000
 371                                                         MX53_PAD_GPIO_19__FEC_TDATA_3    0x80000000
 372                                                         MX53_PAD_KEY_ROW0__FEC_TX_ER     0x80000000
 373                                                 >;
 374                                         };
 375                                 };
 376
 377                                 csi {
 378                                         pinctrl_csi_1: csigrp-1 {
 379                                                 fsl,pins = <
 380                                                         MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
 381                                                         MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC     0x1d5
 382                                                         MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC      0x1d5
 383                                                         MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
 384                                                         MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19      0x1d5
 385                                                         MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18      0x1d5
 386                                                         MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17      0x1d5
 387                                                         MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16      0x1d5
 388                                                         MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15      0x1d5
 389                                                         MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14      0x1d5
 390                                                         MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13      0x1d5
 391                                                         MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12      0x1d5
 392                                                         MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11      0x1d5
 393                                                         MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10      0x1d5
 394                                                         MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9        0x1d5
 395                                                         MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8        0x1d5
 396                                                         MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7        0x1d5
 397                                                         MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6        0x1d5
 398                                                         MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5        0x1d5
 399                                                         MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4        0x1d5
 400                                                         MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
 401                                                 >;
 402                                         };
 403
 404                                         pinctrl_csi_2: csigrp-2 {
 405                                                 fsl,pins = <
 406                                                         MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC     0x1d5
 407                                                         MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC      0x1d5
 408                                                         MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
 409                                                         MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19      0x1d5
 410                                                         MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18      0x1d5
 411                                                         MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17      0x1d5
 412                                                         MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16      0x1d5
 413                                                         MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15      0x1d5
 414                                                         MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14      0x1d5
 415                                                         MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13      0x1d5
 416                                                         MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12      0x1d5
 417                                                 >;
 418                                         };
 419                                 };
 420
 421                                 cspi {
 422                                         pinctrl_cspi_1: cspigrp-1 {
 423                                                 fsl,pins = <
 424                                                         MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
 425                                                         MX53_PAD_SD1_CMD__CSPI_MOSI   0x1d5
 426                                                         MX53_PAD_SD1_CLK__CSPI_SCLK   0x1d5
 427                                                 >;
 428                                         };
 429
 430                                         pinctrl_cspi_2: cspigrp-2 {
 431                                                 fsl,pins = <
 432                                                         MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
 433                                                         MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
 434                                                         MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
 435                                                 >;
 436                                         };
 437                                 };
 438
 439                                 ecspi1 {
 440                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 441                                                 fsl,pins = <
 442                                                         MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
 443                                                         MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
 444                                                         MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
 445                                                 >;
 446                                         };
 447
 448                                         pinctrl_ecspi1_2: ecspi1grp-2 {
 449                                                 fsl,pins = <
 450                                                         MX53_PAD_GPIO_19__ECSPI1_RDY    0x80000000
 451                                                         MX53_PAD_EIM_EB2__ECSPI1_SS0    0x80000000
 452                                                         MX53_PAD_EIM_D16__ECSPI1_SCLK   0x80000000
 453                                                         MX53_PAD_EIM_D17__ECSPI1_MISO   0x80000000
 454                                                         MX53_PAD_EIM_D18__ECSPI1_MOSI   0x80000000
 455                                                         MX53_PAD_EIM_D19__ECSPI1_SS1    0x80000000
 456                                                 >;
 457                                         };
 458                                 };
 459
 460                                 ecspi2 {
 461                                         pinctrl_ecspi2_1: ecspi2grp-1 {
 462                                                 fsl,pins = <
 463                                                         MX53_PAD_EIM_OE__ECSPI2_MISO  0x80000000
 464                                                         MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
 465                                                         MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
 466                                                 >;
 467                                         };
 468                                 };
 469
 470                                 esdhc1 {
 471                                         pinctrl_esdhc1_1: esdhc1grp-1 {
 472                                                 fsl,pins = <
 473                                                         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
 474                                                         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
 475                                                         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
 476                                                         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
 477                                                         MX53_PAD_SD1_CMD__ESDHC1_CMD    0x1d5
 478                                                         MX53_PAD_SD1_CLK__ESDHC1_CLK    0x1d5
 479                                                 >;
 480                                         };
 481
 482                                         pinctrl_esdhc1_2: esdhc1grp-2 {
 483                                                 fsl,pins = <
 484                                                         MX53_PAD_SD1_DATA0__ESDHC1_DAT0   0x1d5
 485                                                         MX53_PAD_SD1_DATA1__ESDHC1_DAT1   0x1d5
 486                                                         MX53_PAD_SD1_DATA2__ESDHC1_DAT2   0x1d5
 487                                                         MX53_PAD_SD1_DATA3__ESDHC1_DAT3   0x1d5
 488                                                         MX53_PAD_PATA_DATA8__ESDHC1_DAT4  0x1d5
 489                                                         MX53_PAD_PATA_DATA9__ESDHC1_DAT5  0x1d5
 490                                                         MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
 491                                                         MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
 492                                                         MX53_PAD_SD1_CMD__ESDHC1_CMD      0x1d5
 493                                                         MX53_PAD_SD1_CLK__ESDHC1_CLK      0x1d5
 494                                                 >;
 495                                         };
 496                                 };
 497
 498                                 esdhc2 {
 499                                         pinctrl_esdhc2_1: esdhc2grp-1 {
 500                                                 fsl,pins = <
 501                                                         MX53_PAD_SD2_CMD__ESDHC2_CMD    0x1d5
 502                                                         MX53_PAD_SD2_CLK__ESDHC2_CLK    0x1d5
 503                                                         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
 504                                                         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
 505                                                         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
 506                                                         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
 507                                                 >;
 508                                         };
 509                                 };
 510
 511                                 esdhc3 {
 512                                         pinctrl_esdhc3_1: esdhc3grp-1 {
 513                                                 fsl,pins = <
 514                                                         MX53_PAD_PATA_DATA8__ESDHC3_DAT0  0x1d5
 515                                                         MX53_PAD_PATA_DATA9__ESDHC3_DAT1  0x1d5
 516                                                         MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
 517                                                         MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
 518                                                         MX53_PAD_PATA_DATA0__ESDHC3_DAT4  0x1d5
 519                                                         MX53_PAD_PATA_DATA1__ESDHC3_DAT5  0x1d5
 520                                                         MX53_PAD_PATA_DATA2__ESDHC3_DAT6  0x1d5
 521                                                         MX53_PAD_PATA_DATA3__ESDHC3_DAT7  0x1d5
 522                                                         MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
 523                                                         MX53_PAD_PATA_IORDY__ESDHC3_CLK   0x1d5
 524                                                 >;
 525                                         };
 526                                 };
 527
 528                                 can1 {
 529                                         pinctrl_can1_1: can1grp-1 {
 530                                                 fsl,pins = <
 531                                                         MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
 532                                                         MX53_PAD_PATA_DIOR__CAN1_RXCAN  0x80000000
 533                                                 >;
 534                                         };
 535
 536                                         pinctrl_can1_2: can1grp-2 {
 537                                                 fsl,pins = <
 538                                                         MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
 539                                                         MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
 540                                                 >;
 541                                         };
 542
 543                                         pinctrl_can1_3: can1grp-3 {
 544                                                 fsl,pins = <
 545                                                         MX53_PAD_GPIO_7__CAN1_TXCAN     0x80000000
 546                                                         MX53_PAD_GPIO_8__CAN1_RXCAN     0x80000000
 547                                                 >;
 548                                         };
 549                                 };
 550
 551                                 can2 {
 552                                         pinctrl_can2_1: can2grp-1 {
 553                                                 fsl,pins = <
 554                                                         MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
 555                                                         MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
 556                                                 >;
 557                                         };
 558                                 };
 559
 560                                 i2c1 {
 561                                         pinctrl_i2c1_1: i2c1grp-1 {
 562                                                 fsl,pins = <
 563                                                         MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
 564                                                         MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
 565                                                 >;
 566                                         };
 567
 568                                         pinctrl_i2c1_2: i2c1grp-2 {
 569                                                 fsl,pins = <
 570                                                         MX53_PAD_EIM_D21__I2C1_SCL      0xc0000000
 571                                                         MX53_PAD_EIM_D28__I2C1_SDA      0xc0000000
 572                                                 >;
 573                                         };
 574                                 };
 575
 576                                 i2c2 {
 577                                         pinctrl_i2c2_1: i2c2grp-1 {
 578                                                 fsl,pins = <
 579                                                         MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
 580                                                         MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
 581                                                 >;
 582                                         };
 583
 584                                         pinctrl_i2c2_2: i2c2grp-2 {
 585                                                 fsl,pins = <
 586                                                         MX53_PAD_EIM_D16__I2C2_SDA      0xc0000000
 587                                                         MX53_PAD_EIM_EB2__I2C2_SCL      0xc0000000
 588                                                 >;
 589                                         };
 590                                 };
 591
 592                                 i2c3 {
 593                                         pinctrl_i2c3_1: i2c3grp-1 {
 594                                                 fsl,pins = <
 595                                                         MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
 596                                                         MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
 597                                                 >;
 598                                         };
 599                                 };
 600
 601                                 ipu_disp0 {
 602                                         pinctrl_ipu_disp0_1: ipudisp0grp-1 {
 603                                                 fsl,pins = <
 604                                                 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
 605                                                 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15               0x5
 606                                                 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2         0x5
 607                                                 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                 0x5
 608                                                 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0            0x5
 609                                                 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1            0x5
 610                                                 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2            0x5
 611                                                 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3            0x5
 612                                                 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4            0x5
 613                                                 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5            0x5
 614                                                 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6            0x5
 615                                                 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7            0x5
 616                                                 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8            0x5
 617                                                 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9            0x5
 618                                                 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10          0x5
 619                                                 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11          0x5
 620                                                 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12          0x5
 621                                                 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13          0x5
 622                                                 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14          0x5
 623                                                 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15          0x5
 624                                                 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16          0x5
 625                                                 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17          0x5
 626                                                 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18          0x5
 627                                                 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19          0x5
 628                                                 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20          0x5
 629                                                 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21          0x5
 630                                                 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22          0x5
 631                                                 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23          0x5
 632                                                 >;
 633                                         };
 634                                 };
 635
 636                                 ipu_disp1 {
 637                                         pinctrl_ipu_disp1_1: ipudisp1grp-1 {
 638                                                 fsl,pins = <
 639                                                         MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0       0x5
 640                                                         MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1       0x5
 641                                                         MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2       0x5
 642                                                         MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3       0x5
 643                                                         MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4       0x5
 644                                                         MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5       0x5
 645                                                         MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6       0x5
 646                                                         MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7       0x5
 647                                                         MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8       0x5
 648                                                         MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9       0x5
 649                                                         MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10      0x5
 650                                                         MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11      0x5
 651                                                         MX53_PAD_EIM_A17__IPU_DISP1_DAT_12      0x5
 652                                                         MX53_PAD_EIM_A18__IPU_DISP1_DAT_13      0x5
 653                                                         MX53_PAD_EIM_A19__IPU_DISP1_DAT_14      0x5
 654                                                         MX53_PAD_EIM_A20__IPU_DISP1_DAT_15      0x5
 655                                                         MX53_PAD_EIM_A21__IPU_DISP1_DAT_16      0x5
 656                                                         MX53_PAD_EIM_A22__IPU_DISP1_DAT_17      0x5
 657                                                         MX53_PAD_EIM_A23__IPU_DISP1_DAT_18      0x5
 658                                                         MX53_PAD_EIM_A24__IPU_DISP1_DAT_19      0x5
 659                                                         MX53_PAD_EIM_D31__IPU_DISP1_DAT_20      0x5
 660                                                         MX53_PAD_EIM_D30__IPU_DISP1_DAT_21      0x5
 661                                                         MX53_PAD_EIM_D26__IPU_DISP1_DAT_22      0x5
 662                                                         MX53_PAD_EIM_D27__IPU_DISP1_DAT_23      0x5
 663                                                         MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK      0x5
 664                                                         MX53_PAD_EIM_DA13__IPU_DI1_D0_CS        0x5
 665                                                         MX53_PAD_EIM_DA14__IPU_DI1_D1_CS        0x5
 666                                                         MX53_PAD_EIM_DA15__IPU_DI1_PIN1         0x5
 667                                                         MX53_PAD_EIM_DA11__IPU_DI1_PIN2         0x5
 668                                                         MX53_PAD_EIM_DA12__IPU_DI1_PIN3         0x5
 669                                                         MX53_PAD_EIM_A25__IPU_DI1_PIN12         0x5
 670                                                         MX53_PAD_EIM_DA10__IPU_DI1_PIN15        0x5
 671                                                 >;
 672                                         };
 673                                 };
 674
 675                                 ipu_disp2 {
 676                                         pinctrl_ipu_disp2_1: ipudisp2grp-1 {
 677                                                 fsl,pins = <
 678                                                         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0     0x80000000
 679                                                         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1     0x80000000
 680                                                         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2     0x80000000
 681                                                         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3     0x80000000
 682                                                         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK     0x80000000
 683                                                         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0     0x80000000
 684                                                         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1     0x80000000
 685                                                         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2     0x80000000
 686                                                         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3     0x80000000
 687                                                         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK     0x80000000
 688                                                 >;
 689                                         };
 690                                 };
 691
 692                                 nand {
 693                                         pinctrl_nand_1: nandgrp-1 {
 694                                                 fsl,pins = <
 695                                                         MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B     0x4
 696                                                         MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B     0x4
 697                                                         MX53_PAD_NANDF_CLE__EMI_NANDF_CLE       0x4
 698                                                         MX53_PAD_NANDF_ALE__EMI_NANDF_ALE       0x4
 699                                                         MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B     0xe0
 700                                                         MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0      0xe0
 701                                                         MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0      0x4
 702                                                         MX53_PAD_PATA_DATA0__EMI_NANDF_D_0      0xa4
 703                                                         MX53_PAD_PATA_DATA1__EMI_NANDF_D_1      0xa4
 704                                                         MX53_PAD_PATA_DATA2__EMI_NANDF_D_2      0xa4
 705                                                         MX53_PAD_PATA_DATA3__EMI_NANDF_D_3      0xa4
 706                                                         MX53_PAD_PATA_DATA4__EMI_NANDF_D_4      0xa4
 707                                                         MX53_PAD_PATA_DATA5__EMI_NANDF_D_5      0xa4
 708                                                         MX53_PAD_PATA_DATA6__EMI_NANDF_D_6      0xa4
 709                                                         MX53_PAD_PATA_DATA7__EMI_NANDF_D_7      0xa4
 710                                                 >;
 711                                         };
 712                                 };
 713
 714                                 owire {
 715                                         pinctrl_owire_1: owiregrp-1 {
 716                                                 fsl,pins = <
 717                                                         MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
 718                                                 >;
 719                                         };
 720                                 };
 721
 722                                 pwm1 {
 723                                         pinctrl_pwm1_1: pwm1grp-1 {
 724                                                 fsl,pins = <
 725                                                         MX53_PAD_DISP0_DAT8__PWM1_PWMO  0x5
 726                                                 >;
 727                                         };
 728                                 };
 729
 730                                 pwm2 {
 731                                         pinctrl_pwm2_1: pwm2grp-1 {
 732                                                 fsl,pins = <
 733                                                         MX53_PAD_GPIO_1__PWM2_PWMO      0x80000000
 734                                                 >;
 735                                         };
 736                                 };
 737
 738                                 uart1 {
 739                                         pinctrl_uart1_1: uart1grp-1 {
 740                                                 fsl,pins = <
 741                                                         MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
 742                                                         MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
 743                                                 >;
 744                                         };
 745
 746                                         pinctrl_uart1_2: uart1grp-2 {
 747                                                 fsl,pins = <
 748                                                         MX53_PAD_PATA_DIOW__UART1_TXD_MUX  0x1e4
 749                                                         MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
 750                                                 >;
 751                                         };
 752
 753                                         pinctrl_uart1_3: uart1grp-3 {
 754                                                 fsl,pins = <
 755                                                         MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
 756                                                         MX53_PAD_PATA_IORDY__UART1_RTS   0x1c5
 757                                                 >;
 758                                         };
 759                                 };
 760
 761                                 uart2 {
 762                                         pinctrl_uart2_1: uart2grp-1 {
 763                                                 fsl,pins = <
 764                                                         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
 765                                                         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     0x1e4
 766                                                 >;
 767                                         };
 768
 769                                         pinctrl_uart2_2: uart2grp-2 {
 770                                                 fsl,pins = <
 771                                                         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX  0x1c5
 772                                                         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX      0x1c5
 773                                                         MX53_PAD_PATA_DIOR__UART2_RTS           0x1c5
 774                                                         MX53_PAD_PATA_INTRQ__UART2_CTS          0x1c5
 775                                                 >;
 776                                         };
 777                                 };
 778
 779                                 uart3 {
 780                                         pinctrl_uart3_1: uart3grp-1 {
 781                                                 fsl,pins = <
 782                                                         MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
 783                                                         MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
 784                                                         MX53_PAD_PATA_DA_1__UART3_CTS     0x1e4
 785                                                         MX53_PAD_PATA_DA_2__UART3_RTS     0x1e4
 786                                                 >;
 787                                         };
 788
 789                                         pinctrl_uart3_2: uart3grp-2 {
 790                                                 fsl,pins = <
 791                                                         MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
 792                                                         MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
 793                                                 >;
 794                                         };
 795
 796                                 };
 797
 798                                 uart4 {
 799                                         pinctrl_uart4_1: uart4grp-1 {
 800                                                 fsl,pins = <
 801                                                         MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
 802                                                         MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
 803                                                 >;
 804                                         };
 805                                 };
 806
 807                                 uart5 {
 808                                         pinctrl_uart5_1: uart5grp-1 {
 809                                                 fsl,pins = <
 810                                                         MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4
 811                                                         MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
 812                                                 >;
 813                                         };
 814                                 };
 815                         };
 816
 817                         gpr: iomuxc-gpr@53fa8000 {
 818                                 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
 819                                 reg = <0x53fa8000 0xc>;
 820                         };
 821
 822                         ldb: ldb@53fa8008 {
 823                                 #address-cells = <1>;
 824                                 #size-cells = <0>;
 825                                 compatible = "fsl,imx53-ldb";
 826                                 reg = <0x53fa8008 0x4>;
 827                                 gpr = <&gpr>;
 828                                 clocks = <&clks 122>, <&clks 120>,
 829                                          <&clks 115>, <&clks 116>,
 830                                          <&clks 123>, <&clks 85>;
 831                                 clock-names = "di0_pll", "di1_pll",
 832                                               "di0_sel", "di1_sel",
 833                                               "di0", "di1";
 834                                 status = "disabled";
 835
 836                                 lvds-channel@0 {
 837                                         reg = <0>;
 838                                         crtcs = <&ipu 0>;
 839                                         status = "disabled";
 840                                 };
 841
 842                                 lvds-channel@1 {
 843                                         reg = <1>;
 844                                         crtcs = <&ipu 1>;
 845                                         status = "disabled";
 846                                 };
 847                         };
 848
 849                         pwm1: pwm@53fb4000 {
 850                                 #pwm-cells = <2>;
 851                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 852                                 reg = <0x53fb4000 0x4000>;
 853                                 clocks = <&clks 37>, <&clks 38>;
 854                                 clock-names = "ipg", "per";
 855                                 interrupts = <61>;
 856                         };
 857
 858                         pwm2: pwm@53fb8000 {
 859                                 #pwm-cells = <2>;
 860                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 861                                 reg = <0x53fb8000 0x4000>;
 862                                 clocks = <&clks 39>, <&clks 40>;
 863                                 clock-names = "ipg", "per";
 864                                 interrupts = <94>;
 865                         };
 866
 867                         uart1: serial@53fbc000 {
 868                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 869                                 reg = <0x53fbc000 0x4000>;
 870                                 interrupts = <31>;
 871                                 clocks = <&clks 28>, <&clks 29>;
 872                                 clock-names = "ipg", "per";
 873                                 status = "disabled";
 874                         };
 875
 876                         uart2: serial@53fc0000 {
 877                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 878                                 reg = <0x53fc0000 0x4000>;
 879                                 interrupts = <32>;
 880                                 clocks = <&clks 30>, <&clks 31>;
 881                                 clock-names = "ipg", "per";
 882                                 status = "disabled";
 883                         };
 884
 885                         can1: can@53fc8000 {
 886                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 887                                 reg = <0x53fc8000 0x4000>;
 888                                 interrupts = <82>;
 889                                 clocks = <&clks 158>, <&clks 157>;
 890                                 clock-names = "ipg", "per";
 891                                 status = "disabled";
 892                         };
 893
 894                         can2: can@53fcc000 {
 895                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 896                                 reg = <0x53fcc000 0x4000>;
 897                                 interrupts = <83>;
 898                                 clocks = <&clks 87>, <&clks 86>;
 899                                 clock-names = "ipg", "per";
 900                                 status = "disabled";
 901                         };
 902
 903                         src: src@53fd0000 {
 904                                 compatible = "fsl,imx53-src", "fsl,imx51-src";
 905                                 reg = <0x53fd0000 0x4000>;
 906                                 #reset-cells = <1>;
 907                         };
 908
 909                         clks: ccm@53fd4000{
 910                                 compatible = "fsl,imx53-ccm";
 911                                 reg = <0x53fd4000 0x4000>;
 912                                 interrupts = <0 71 0x04 0 72 0x04>;
 913                                 #clock-cells = <1>;
 914                         };
 915
 916                         gpio5: gpio@53fdc000 {
 917                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 918                                 reg = <0x53fdc000 0x4000>;
 919                                 interrupts = <103 104>;
 920                                 gpio-controller;
 921                                 #gpio-cells = <2>;
 922                                 interrupt-controller;
 923                                 #interrupt-cells = <2>;
 924                         };
 925
 926                         gpio6: gpio@53fe0000 {
 927                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 928                                 reg = <0x53fe0000 0x4000>;
 929                                 interrupts = <105 106>;
 930                                 gpio-controller;
 931                                 #gpio-cells = <2>;
 932                                 interrupt-controller;
 933                                 #interrupt-cells = <2>;
 934                         };
 935
 936                         gpio7: gpio@53fe4000 {
 937                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 938                                 reg = <0x53fe4000 0x4000>;
 939                                 interrupts = <107 108>;
 940                                 gpio-controller;
 941                                 #gpio-cells = <2>;
 942                                 interrupt-controller;
 943                                 #interrupt-cells = <2>;
 944                         };
 945
 946                         i2c3: i2c@53fec000 {
 947                                 #address-cells = <1>;
 948                                 #size-cells = <0>;
 949                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 950                                 reg = <0x53fec000 0x4000>;
 951                                 interrupts = <64>;
 952                                 clocks = <&clks 88>;
 953                                 status = "disabled";
 954                         };
 955
 956                         uart4: serial@53ff0000 {
 957                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 958                                 reg = <0x53ff0000 0x4000>;
 959                                 interrupts = <13>;
 960                                 clocks = <&clks 65>, <&clks 66>;
 961                                 clock-names = "ipg", "per";
 962                                 status = "disabled";
 963                         };
 964                 };
 965
 966                 aips@60000000 { /* AIPS2 */
 967                         compatible = "fsl,aips-bus", "simple-bus";
 968                         #address-cells = <1>;
 969                         #size-cells = <1>;
 970                         reg = <0x60000000 0x10000000>;
 971                         ranges;
 972
 973                         iim: iim@63f98000 {
 974                                 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
 975                                 reg = <0x63f98000 0x4000>;
 976                                 interrupts = <69>;
 977                                 clocks = <&clks 107>;
 978                         };
 979
 980                         uart5: serial@63f90000 {
 981                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 982                                 reg = <0x63f90000 0x4000>;
 983                                 interrupts = <86>;
 984                                 clocks = <&clks 67>, <&clks 68>;
 985                                 clock-names = "ipg", "per";
 986                                 status = "disabled";
 987                         };
 988
 989                         owire: owire@63fa4000 {
 990                                 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
 991                                 reg = <0x63fa4000 0x4000>;
 992                                 clocks = <&clks 159>;
 993                                 status = "disabled";
 994                         };
 995
 996                         ecspi2: ecspi@63fac000 {
 997                                 #address-cells = <1>;
 998                                 #size-cells = <0>;
 999                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
1000                                 reg = <0x63fac000 0x4000>;
1001                                 interrupts = <37>;
1002                                 clocks = <&clks 53>, <&clks 54>;
1003                                 clock-names = "ipg", "per";
1004                                 status = "disabled";
1005                         };
1006
1007                         sdma: sdma@63fb0000 {
1008                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
1009                                 reg = <0x63fb0000 0x4000>;
1010                                 interrupts = <6>;
1011                                 clocks = <&clks 56>, <&clks 56>;
1012                                 clock-names = "ipg", "ahb";
1013                                 #dma-cells = <3>;
1014                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
1015                         };
1016
1017                         cspi: cspi@63fc0000 {
1018                                 #address-cells = <1>;
1019                                 #size-cells = <0>;
1020                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
1021                                 reg = <0x63fc0000 0x4000>;
1022                                 interrupts = <38>;
1023                                 clocks = <&clks 55>, <&clks 55>;
1024                                 clock-names = "ipg", "per";
1025                                 status = "disabled";
1026                         };
1027
1028                         i2c2: i2c@63fc4000 {
1029                                 #address-cells = <1>;
1030                                 #size-cells = <0>;
1031                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
1032                                 reg = <0x63fc4000 0x4000>;
1033                                 interrupts = <63>;
1034                                 clocks = <&clks 35>;
1035                                 status = "disabled";
1036                         };
1037
1038                         i2c1: i2c@63fc8000 {
1039                                 #address-cells = <1>;
1040                                 #size-cells = <0>;
1041                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
1042                                 reg = <0x63fc8000 0x4000>;
1043                                 interrupts = <62>;
1044                                 clocks = <&clks 34>;
1045                                 status = "disabled";
1046                         };
1047
1048                         ssi1: ssi@63fcc000 {
1049                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
1050                                 reg = <0x63fcc000 0x4000>;
1051                                 interrupts = <29>;
1052                                 clocks = <&clks 48>;
1053                                 fsl,fifo-depth = <15>;
1054                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
1055                                 status = "disabled";
1056                         };
1057
1058                         audmux: audmux@63fd0000 {
1059                                 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
1060                                 reg = <0x63fd0000 0x4000>;
1061                                 status = "disabled";
1062                         };
1063
1064                         nfc: nand@63fdb000 {
1065                                 compatible = "fsl,imx53-nand";
1066                                 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
1067                                 interrupts = <8>;
1068                                 clocks = <&clks 60>;
1069                                 status = "disabled";
1070                         };
1071
1072                         ssi3: ssi@63fe8000 {
1073                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
1074                                 reg = <0x63fe8000 0x4000>;
1075                                 interrupts = <96>;
1076                                 clocks = <&clks 50>;
1077                                 fsl,fifo-depth = <15>;
1078                                 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
1079                                 status = "disabled";
1080                         };
1081
1082                         fec: ethernet@63fec000 {
1083                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
1084                                 reg = <0x63fec000 0x4000>;
1085                                 interrupts = <87>;
1086                                 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
1087                                 clock-names = "ipg", "ahb", "ptp";
1088                                 status = "disabled";
1089                         };
1090
1091                         tve: tve@63ff0000 {
1092                                 compatible = "fsl,imx53-tve";
1093                                 reg = <0x63ff0000 0x1000>;
1094                                 interrupts = <92>;
1095                                 clocks = <&clks 69>, <&clks 116>;
1096                                 clock-names = "tve", "di_sel";
1097                                 crtcs = <&ipu 1>;
1098                                 status = "disabled";
1099                         };
1100
1101                         vpu: vpu@63ff4000 {
1102                                 compatible = "fsl,imx53-vpu";
1103                                 reg = <0x63ff4000 0x1000>;
1104                                 interrupts = <9>;
1105                                 clocks = <&clks 63>, <&clks 63>;
1106                                 clock-names = "per", "ahb";
1107                                 iram = <&ocram>;
1108                                 status = "disabled";
1109                         };
1110                 };
1111
1112                 ocram: sram@f8000000 {
1113                         compatible = "mmio-sram";
1114                         reg = <0xf8000000 0x20000>;
1115                 };
1116         };
1117 };