2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
38 tzic: tz-interrupt-controller@0fffc000 {
39 compatible = "fsl,imx53-tzic", "fsl,tzic";
41 #interrupt-cells = <1>;
42 reg = <0x0fffc000 0x4000>;
50 compatible = "fsl,imx-ckil", "fixed-clock";
51 clock-frequency = <32768>;
55 compatible = "fsl,imx-ckih1", "fixed-clock";
56 clock-frequency = <22579200>;
60 compatible = "fsl,imx-ckih2", "fixed-clock";
61 clock-frequency = <0>;
65 compatible = "fsl,imx-osc", "fixed-clock";
66 clock-frequency = <24000000>;
73 compatible = "simple-bus";
74 interrupt-parent = <&tzic>;
79 compatible = "fsl,imx53-ipu";
80 reg = <0x18000000 0x080000000>;
82 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
83 clock-names = "bus", "di0", "di1";
87 aips@50000000 { /* AIPS1 */
88 compatible = "fsl,aips-bus", "simple-bus";
91 reg = <0x50000000 0x10000000>;
95 compatible = "fsl,spba-bus", "simple-bus";
98 reg = <0x50000000 0x40000>;
101 esdhc1: esdhc@50004000 {
102 compatible = "fsl,imx53-esdhc";
103 reg = <0x50004000 0x4000>;
105 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
106 clock-names = "ipg", "ahb", "per";
111 esdhc2: esdhc@50008000 {
112 compatible = "fsl,imx53-esdhc";
113 reg = <0x50008000 0x4000>;
115 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
116 clock-names = "ipg", "ahb", "per";
121 uart3: serial@5000c000 {
122 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
123 reg = <0x5000c000 0x4000>;
125 clocks = <&clks 32>, <&clks 33>;
126 clock-names = "ipg", "per";
130 ecspi1: ecspi@50010000 {
131 #address-cells = <1>;
133 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
134 reg = <0x50010000 0x4000>;
136 clocks = <&clks 51>, <&clks 52>;
137 clock-names = "ipg", "per";
142 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
143 reg = <0x50014000 0x4000>;
146 fsl,fifo-depth = <15>;
147 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
151 esdhc3: esdhc@50020000 {
152 compatible = "fsl,imx53-esdhc";
153 reg = <0x50020000 0x4000>;
155 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
156 clock-names = "ipg", "ahb", "per";
161 esdhc4: esdhc@50024000 {
162 compatible = "fsl,imx53-esdhc";
163 reg = <0x50024000 0x4000>;
165 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
166 clock-names = "ipg", "ahb", "per";
173 compatible = "usb-nop-xceiv";
174 clocks = <&clks 124>;
175 clock-names = "main_clk";
180 compatible = "usb-nop-xceiv";
181 clocks = <&clks 125>;
182 clock-names = "main_clk";
186 usbotg: usb@53f80000 {
187 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
188 reg = <0x53f80000 0x0200>;
190 clocks = <&clks 108>;
191 fsl,usbmisc = <&usbmisc 0>;
192 fsl,usbphy = <&usbphy0>;
196 usbh1: usb@53f80200 {
197 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
198 reg = <0x53f80200 0x0200>;
200 clocks = <&clks 108>;
201 fsl,usbmisc = <&usbmisc 1>;
202 fsl,usbphy = <&usbphy1>;
206 usbh2: usb@53f80400 {
207 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
208 reg = <0x53f80400 0x0200>;
210 clocks = <&clks 108>;
211 fsl,usbmisc = <&usbmisc 2>;
215 usbh3: usb@53f80600 {
216 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
217 reg = <0x53f80600 0x0200>;
219 clocks = <&clks 108>;
220 fsl,usbmisc = <&usbmisc 3>;
224 usbmisc: usbmisc@53f80800 {
226 compatible = "fsl,imx53-usbmisc";
227 reg = <0x53f80800 0x200>;
228 clocks = <&clks 108>;
231 gpio1: gpio@53f84000 {
232 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
233 reg = <0x53f84000 0x4000>;
234 interrupts = <50 51>;
237 interrupt-controller;
238 #interrupt-cells = <2>;
241 gpio2: gpio@53f88000 {
242 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
243 reg = <0x53f88000 0x4000>;
244 interrupts = <52 53>;
247 interrupt-controller;
248 #interrupt-cells = <2>;
251 gpio3: gpio@53f8c000 {
252 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
253 reg = <0x53f8c000 0x4000>;
254 interrupts = <54 55>;
257 interrupt-controller;
258 #interrupt-cells = <2>;
261 gpio4: gpio@53f90000 {
262 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
263 reg = <0x53f90000 0x4000>;
264 interrupts = <56 57>;
267 interrupt-controller;
268 #interrupt-cells = <2>;
271 wdog1: wdog@53f98000 {
272 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
273 reg = <0x53f98000 0x4000>;
278 wdog2: wdog@53f9c000 {
279 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
280 reg = <0x53f9c000 0x4000>;
286 gpt: timer@53fa0000 {
287 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
288 reg = <0x53fa0000 0x4000>;
290 clocks = <&clks 36>, <&clks 41>;
291 clock-names = "ipg", "per";
294 iomuxc: iomuxc@53fa8000 {
295 compatible = "fsl,imx53-iomuxc";
296 reg = <0x53fa8000 0x4000>;
299 pinctrl_audmux_1: audmuxgrp-1 {
301 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
302 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
303 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
304 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
308 pinctrl_audmux_2: audmuxgrp-2 {
310 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
311 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
312 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
313 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
317 pinctrl_audmux_3: audmuxgrp-3 {
319 MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000
320 MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000
321 MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000
322 MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000
328 pinctrl_fec_1: fecgrp-1 {
330 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
331 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
332 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
333 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
334 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
335 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
336 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
337 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
338 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
339 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
343 pinctrl_fec_2: fecgrp-2 {
345 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
346 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
347 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
348 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
349 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
350 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
351 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
352 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
353 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
354 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
355 MX53_PAD_KEY_ROW1__FEC_COL 0x80000000
356 MX53_PAD_KEY_COL3__FEC_CRS 0x80000000
357 MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000
358 MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000
359 MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000
360 MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000
361 MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000
362 MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000
368 pinctrl_csi_1: csigrp-1 {
370 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
371 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
372 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
373 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
374 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
375 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
376 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
377 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
378 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
379 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
380 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
381 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
382 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
383 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
384 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
385 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
386 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
387 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
388 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
389 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
390 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
394 pinctrl_csi_2: csigrp-2 {
396 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
397 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
398 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
399 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
400 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
401 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
402 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
403 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
404 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
405 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
406 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
412 pinctrl_cspi_1: cspigrp-1 {
414 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
415 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
416 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
420 pinctrl_cspi_2: cspigrp-2 {
422 MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
423 MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
424 MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
430 pinctrl_ecspi1_1: ecspi1grp-1 {
432 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
433 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
434 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
438 pinctrl_ecspi1_2: ecspi1grp-2 {
440 MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000
441 MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000
442 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
443 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
444 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
445 MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000
451 pinctrl_ecspi2_1: ecspi2grp-1 {
453 MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000
454 MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
455 MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
461 pinctrl_esdhc1_1: esdhc1grp-1 {
463 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
464 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
465 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
466 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
467 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
468 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
472 pinctrl_esdhc1_2: esdhc1grp-2 {
474 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
475 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
476 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
477 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
478 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
479 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
480 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
481 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
482 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
483 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
489 pinctrl_esdhc2_1: esdhc2grp-1 {
491 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
492 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
493 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
494 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
495 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
496 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
502 pinctrl_esdhc3_1: esdhc3grp-1 {
504 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
505 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
506 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
507 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
508 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
509 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
510 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
511 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
512 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
513 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
519 pinctrl_can1_1: can1grp-1 {
521 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
522 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
526 pinctrl_can1_2: can1grp-2 {
528 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
529 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
533 pinctrl_can1_3: can1grp-3 {
535 MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
536 MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
542 pinctrl_can2_1: can2grp-1 {
544 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
545 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
551 pinctrl_i2c1_1: i2c1grp-1 {
553 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
554 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
558 pinctrl_i2c1_2: i2c1grp-2 {
560 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
561 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
567 pinctrl_i2c2_1: i2c2grp-1 {
569 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
570 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
574 pinctrl_i2c2_2: i2c2grp-2 {
576 MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
577 MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
583 pinctrl_i2c3_1: i2c3grp-1 {
585 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
586 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
592 pinctrl_ipu_disp0_1: ipudisp0grp-1 {
594 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
595 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
596 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
597 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
598 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
599 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
600 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
601 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
602 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
603 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
604 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
605 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
606 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
607 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
608 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
609 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
610 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
611 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
612 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
613 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
614 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
615 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
616 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
617 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
618 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
619 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
620 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
621 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
627 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
629 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
630 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
631 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
632 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
633 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
634 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
635 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
636 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
637 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
638 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
639 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
640 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
641 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
642 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
643 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
644 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
645 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
646 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
647 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
648 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
649 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
650 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
651 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
652 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
653 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
654 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
655 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
656 MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
657 MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
658 MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
659 MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
660 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
666 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
668 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
669 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
670 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
671 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
672 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
673 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
674 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
675 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
676 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
677 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
683 pinctrl_nand_1: nandgrp-1 {
685 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
686 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
687 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
688 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
689 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
690 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
691 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
692 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
693 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
694 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
695 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
696 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
697 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
698 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
699 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
705 pinctrl_owire_1: owiregrp-1 {
707 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
713 pinctrl_pwm1_1: pwm1grp-1 {
715 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
721 pinctrl_pwm2_1: pwm2grp-1 {
723 MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000
729 pinctrl_uart1_1: uart1grp-1 {
731 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
732 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
736 pinctrl_uart1_2: uart1grp-2 {
738 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
739 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
743 pinctrl_uart1_3: uart1grp-3 {
745 MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
746 MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5
752 pinctrl_uart2_1: uart2grp-1 {
754 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
755 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
759 pinctrl_uart2_2: uart2grp-2 {
761 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
762 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
763 MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5
764 MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5
770 pinctrl_uart3_1: uart3grp-1 {
772 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
773 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
774 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
775 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
779 pinctrl_uart3_2: uart3grp-2 {
781 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
782 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
789 pinctrl_uart4_1: uart4grp-1 {
791 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
792 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
798 pinctrl_uart5_1: uart5grp-1 {
800 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4
801 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
807 gpr: iomuxc-gpr@53fa8000 {
808 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
809 reg = <0x53fa8000 0xc>;
813 #address-cells = <1>;
815 compatible = "fsl,imx53-ldb";
816 reg = <0x53fa8008 0x4>;
818 clocks = <&clks 122>, <&clks 120>,
819 <&clks 115>, <&clks 116>,
820 <&clks 123>, <&clks 85>;
821 clock-names = "di0_pll", "di1_pll",
822 "di0_sel", "di1_sel",
841 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
842 reg = <0x53fb4000 0x4000>;
843 clocks = <&clks 37>, <&clks 38>;
844 clock-names = "ipg", "per";
850 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
851 reg = <0x53fb8000 0x4000>;
852 clocks = <&clks 39>, <&clks 40>;
853 clock-names = "ipg", "per";
857 uart1: serial@53fbc000 {
858 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
859 reg = <0x53fbc000 0x4000>;
861 clocks = <&clks 28>, <&clks 29>;
862 clock-names = "ipg", "per";
866 uart2: serial@53fc0000 {
867 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
868 reg = <0x53fc0000 0x4000>;
870 clocks = <&clks 30>, <&clks 31>;
871 clock-names = "ipg", "per";
876 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
877 reg = <0x53fc8000 0x4000>;
879 clocks = <&clks 158>, <&clks 157>;
880 clock-names = "ipg", "per";
885 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
886 reg = <0x53fcc000 0x4000>;
888 clocks = <&clks 87>, <&clks 86>;
889 clock-names = "ipg", "per";
894 compatible = "fsl,imx53-src", "fsl,imx51-src";
895 reg = <0x53fd0000 0x4000>;
900 compatible = "fsl,imx53-ccm";
901 reg = <0x53fd4000 0x4000>;
902 interrupts = <0 71 0x04 0 72 0x04>;
906 gpio5: gpio@53fdc000 {
907 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
908 reg = <0x53fdc000 0x4000>;
909 interrupts = <103 104>;
912 interrupt-controller;
913 #interrupt-cells = <2>;
916 gpio6: gpio@53fe0000 {
917 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
918 reg = <0x53fe0000 0x4000>;
919 interrupts = <105 106>;
922 interrupt-controller;
923 #interrupt-cells = <2>;
926 gpio7: gpio@53fe4000 {
927 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
928 reg = <0x53fe4000 0x4000>;
929 interrupts = <107 108>;
932 interrupt-controller;
933 #interrupt-cells = <2>;
937 #address-cells = <1>;
939 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
940 reg = <0x53fec000 0x4000>;
946 uart4: serial@53ff0000 {
947 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
948 reg = <0x53ff0000 0x4000>;
950 clocks = <&clks 65>, <&clks 66>;
951 clock-names = "ipg", "per";
956 aips@60000000 { /* AIPS2 */
957 compatible = "fsl,aips-bus", "simple-bus";
958 #address-cells = <1>;
960 reg = <0x60000000 0x10000000>;
964 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
965 reg = <0x63f98000 0x4000>;
967 clocks = <&clks 107>;
970 uart5: serial@63f90000 {
971 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
972 reg = <0x63f90000 0x4000>;
974 clocks = <&clks 67>, <&clks 68>;
975 clock-names = "ipg", "per";
979 owire: owire@63fa4000 {
980 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
981 reg = <0x63fa4000 0x4000>;
982 clocks = <&clks 159>;
986 ecspi2: ecspi@63fac000 {
987 #address-cells = <1>;
989 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
990 reg = <0x63fac000 0x4000>;
992 clocks = <&clks 53>, <&clks 54>;
993 clock-names = "ipg", "per";
997 sdma: sdma@63fb0000 {
998 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
999 reg = <0x63fb0000 0x4000>;
1001 clocks = <&clks 56>, <&clks 56>;
1002 clock-names = "ipg", "ahb";
1004 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
1007 cspi: cspi@63fc0000 {
1008 #address-cells = <1>;
1010 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
1011 reg = <0x63fc0000 0x4000>;
1013 clocks = <&clks 55>, <&clks 55>;
1014 clock-names = "ipg", "per";
1015 status = "disabled";
1018 i2c2: i2c@63fc4000 {
1019 #address-cells = <1>;
1021 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
1022 reg = <0x63fc4000 0x4000>;
1024 clocks = <&clks 35>;
1025 status = "disabled";
1028 i2c1: i2c@63fc8000 {
1029 #address-cells = <1>;
1031 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
1032 reg = <0x63fc8000 0x4000>;
1034 clocks = <&clks 34>;
1035 status = "disabled";
1038 ssi1: ssi@63fcc000 {
1039 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
1040 reg = <0x63fcc000 0x4000>;
1042 clocks = <&clks 48>;
1043 fsl,fifo-depth = <15>;
1044 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
1045 status = "disabled";
1048 audmux: audmux@63fd0000 {
1049 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
1050 reg = <0x63fd0000 0x4000>;
1051 status = "disabled";
1054 nfc: nand@63fdb000 {
1055 compatible = "fsl,imx53-nand";
1056 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
1058 clocks = <&clks 60>;
1059 status = "disabled";
1062 ssi3: ssi@63fe8000 {
1063 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
1064 reg = <0x63fe8000 0x4000>;
1066 clocks = <&clks 50>;
1067 fsl,fifo-depth = <15>;
1068 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
1069 status = "disabled";
1072 fec: ethernet@63fec000 {
1073 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
1074 reg = <0x63fec000 0x4000>;
1076 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
1077 clock-names = "ipg", "ahb", "ptp";
1078 status = "disabled";
1082 compatible = "fsl,imx53-tve";
1083 reg = <0x63ff0000 0x1000>;
1085 clocks = <&clks 69>, <&clks 116>;
1086 clock-names = "tve", "di_sel";
1088 status = "disabled";
1092 compatible = "fsl,imx53-vpu";
1093 reg = <0x63ff4000 0x1000>;
1095 clocks = <&clks 63>, <&clks 63>;
1096 clock-names = "per", "ahb";
1098 status = "disabled";
1102 ocram: sram@f8000000 {
1103 compatible = "mmio-sram";
1104 reg = <0xf8000000 0x20000>;