arch/arm/boot/dts/imx53-m53evk.dts

   1 /*
   2  * Copyright (C) 2013 Marek Vasut <marex@denx.de>
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 /dts-v1/;
  13 #include "imx53.dtsi"
  14
  15 / {
  16         model = "DENX M53EVK";
  17         compatible = "denx,imx53-m53evk", "fsl,imx53";
  18
  19         memory {
  20                 reg = <0x70000000 0x20000000>;
  21         };
  22
  23         soc {
  24                 display1: display@di1 {
  25                         compatible = "fsl,imx-parallel-display";
  26                         interface-pix-fmt = "bgr666";
  27                         pinctrl-names = "default";
  28                         pinctrl-0 = <&pinctrl_ipu_disp1>;
  29
  30                         display-timings {
  31                                 800x480p60 {
  32                                         native-mode;
  33                                         clock-frequency = <31500000>;
  34                                         hactive = <800>;
  35                                         vactive = <480>;
  36                                         hfront-porch = <40>;
  37                                         hback-porch = <88>;
  38                                         hsync-len = <128>;
  39                                         vback-porch = <33>;
  40                                         vfront-porch = <9>;
  41                                         vsync-len = <3>;
  42                                         vsync-active = <1>;
  43                                 };
  44                         };
  45                 };
  46
  47                 port {
  48                         display1_in: endpoint {
  49                                 remote-endpoint = <&ipu_di1_disp1>;
  50                         };
  51                 };
  52         };
  53
  54         backlight {
  55                 compatible = "pwm-backlight";
  56                 pwms = <&pwm1 0 3000>;
  57                 brightness-levels = <0 4 8 16 32 64 128 255>;
  58                 default-brightness-level = <6>;
  59                 power-supply = <&reg_backlight>;
  60         };
  61
  62         leds {
  63                 compatible = "gpio-leds";
  64                 pinctrl-names = "default";
  65                 pinctrl-0 = <&led_pin_gpio>;
  66
  67                 user1 {
  68                         label = "user1";
  69                         gpios = <&gpio2 8 0>;
  70                         linux,default-trigger = "heartbeat";
  71                 };
  72
  73                 user2 {
  74                         label = "user2";
  75                         gpios = <&gpio2 9 0>;
  76                         linux,default-trigger = "heartbeat";
  77                 };
  78         };
  79
  80         regulators {
  81                 compatible = "simple-bus";
  82                 #address-cells = <1>;
  83                 #size-cells = <0>;
  84
  85                 reg_3p2v: regulator@0 {
  86                         compatible = "regulator-fixed";
  87                         reg = <0>;
  88                         regulator-name = "3P2V";
  89                         regulator-min-microvolt = <3200000>;
  90                         regulator-max-microvolt = <3200000>;
  91                         regulator-always-on;
  92                 };
  93
  94
  95                 reg_backlight: regulator@1 {
  96                         compatible = "regulator-fixed";
  97                         reg = <1>;
  98                         regulator-name = "lcd-supply";
  99                         regulator-min-microvolt = <3200000>;
 100                         regulator-max-microvolt = <3200000>;
 101                         regulator-always-on;
 102                 };
 103
 104                 reg_usbh1_vbus: regulator@3 {
 105                         compatible = "regulator-fixed";
 106                         reg = <3>;
 107                         regulator-name = "vbus";
 108                         regulator-min-microvolt = <5000000>;
 109                         regulator-max-microvolt = <5000000>;
 110                         gpio = <&gpio1 2 0>;
 111                 };
 112         };
 113
 114         sound {
 115                 compatible = "fsl,imx53-m53evk-sgtl5000",
 116                              "fsl,imx-audio-sgtl5000";
 117                 model = "imx53-m53evk-sgtl5000";
 118                 ssi-controller = <&ssi2>;
 119                 audio-codec = <&sgtl5000>;
 120                 audio-routing =
 121                         "MIC_IN", "Mic Jack",
 122                         "Mic Jack", "Mic Bias",
 123                         "LINE_IN", "Line In Jack",
 124                         "Headphone Jack", "HP_OUT",
 125                         "Ext Spk", "LINE_OUT";
 126                 mux-int-port = <2>;
 127                 mux-ext-port = <4>;
 128         };
 129 };
 130
 131 &audmux {
 132         pinctrl-names = "default";
 133         pinctrl-0 = <&pinctrl_audmux>;
 134         status = "okay";
 135 };
 136
 137 &can1 {
 138         pinctrl-names = "default";
 139         pinctrl-0 = <&pinctrl_can1>;
 140         status = "okay";
 141 };
 142
 143 &can2 {
 144         pinctrl-names = "default";
 145         pinctrl-0 = <&pinctrl_can2>;
 146         status = "okay";
 147 };
 148
 149 &esdhc1 {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_esdhc1>;
 152         cd-gpios = <&gpio1 1 0>;
 153         wp-gpios = <&gpio1 9 0>;
 154         status = "okay";
 155 };
 156
 157 &fec {
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&pinctrl_fec>;
 160         phy-mode = "rmii";
 161         status = "okay";
 162 };
 163
 164 &i2c1 {
 165         pinctrl-names = "default";
 166         pinctrl-0 = <&pinctrl_i2c1>;
 167         status = "okay";
 168
 169         sgtl5000: codec@0a {
 170                 compatible = "fsl,sgtl5000";
 171                 reg = <0x0a>;
 172                 VDDA-supply = <&reg_3p2v>;
 173                 VDDIO-supply = <&reg_3p2v>;
 174                 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
 175         };
 176 };
 177
 178 &i2c2 {
 179         pinctrl-names = "default";
 180         pinctrl-0 = <&pinctrl_i2c2>;
 181         clock-frequency = <400000>;
 182         status = "okay";
 183
 184         stmpe610@41 {
 185                 compatible = "st,stmpe610";
 186                 #address-cells = <1>;
 187                 #size-cells = <0>;
 188                 reg = <0x41>;
 189                 id = <0>;
 190                 blocks = <0x5>;
 191                 interrupts = <6 0x0>;
 192                 interrupt-parent = <&gpio7>;
 193                 irq-trigger = <0x1>;
 194
 195                 stmpe_touchscreen {
 196                         compatible = "stmpe,ts";
 197                         reg = <0>;
 198                         ts,sample-time = <4>;
 199                         ts,mod-12b = <1>;
 200                         ts,ref-sel = <0>;
 201                         ts,adc-freq = <1>;
 202                         ts,ave-ctrl = <3>;
 203                         ts,touch-det-delay = <3>;
 204                         ts,settling = <4>;
 205                         ts,fraction-z = <7>;
 206                         ts,i-drive = <1>;
 207                 };
 208         };
 209
 210         eeprom: eeprom@50 {
 211                 compatible = "atmel,24c128";
 212                 reg = <0x50>;
 213                 pagesize = <32>;
 214         };
 215
 216         rtc: rtc@68 {
 217                 compatible = "stm,m41t62";
 218                 reg = <0x68>;
 219         };
 220 };
 221
 222 &i2c3 {
 223         pinctrl-names = "default";
 224         pinctrl-0 = <&pinctrl_i2c3>;
 225         status = "okay";
 226 };
 227
 228 &iomuxc {
 229         pinctrl-names = "default";
 230         pinctrl-0 = <&pinctrl_hog>;
 231
 232         imx53-m53evk {
 233                 pinctrl_hog: hoggrp {
 234                         fsl,pins = <
 235                                 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK       0x80000000
 236                                 MX53_PAD_EIM_EB3__GPIO2_31              0x80000000
 237                                 MX53_PAD_PATA_DA_0__GPIO7_6             0x80000000
 238                                 MX53_PAD_GPIO_2__GPIO1_2                0x80000000
 239                                 MX53_PAD_GPIO_3__USBOH3_USBH1_OC        0x80000000
 240                         >;
 241                 };
 242
 243                 led_pin_gpio: led_gpio@0 {
 244                         fsl,pins = <
 245                                 MX53_PAD_PATA_DATA8__GPIO2_8            0x80000000
 246                                 MX53_PAD_PATA_DATA9__GPIO2_9            0x80000000
 247                         >;
 248                 };
 249
 250                 pinctrl_audmux: audmuxgrp {
 251                         fsl,pins = <
 252                                 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC     0x80000000
 253                                 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD     0x80000000
 254                                 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS    0x80000000
 255                                 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD     0x80000000
 256                         >;
 257                 };
 258
 259                 pinctrl_can1: can1grp {
 260                         fsl,pins = <
 261                                 MX53_PAD_GPIO_7__CAN1_TXCAN             0x80000000
 262                                 MX53_PAD_GPIO_8__CAN1_RXCAN             0x80000000
 263                         >;
 264                 };
 265
 266                 pinctrl_can2: can2grp {
 267                         fsl,pins = <
 268                                 MX53_PAD_KEY_COL4__CAN2_TXCAN           0x80000000
 269                                 MX53_PAD_KEY_ROW4__CAN2_RXCAN           0x80000000
 270                         >;
 271                 };
 272
 273                 pinctrl_esdhc1: esdhc1grp {
 274                         fsl,pins = <
 275                                 MX53_PAD_SD1_DATA0__ESDHC1_DAT0         0x1d5
 276                                 MX53_PAD_SD1_DATA1__ESDHC1_DAT1         0x1d5
 277                                 MX53_PAD_SD1_DATA2__ESDHC1_DAT2         0x1d5
 278                                 MX53_PAD_SD1_DATA3__ESDHC1_DAT3         0x1d5
 279                                 MX53_PAD_SD1_CMD__ESDHC1_CMD            0x1d5
 280                                 MX53_PAD_SD1_CLK__ESDHC1_CLK            0x1d5
 281                         >;
 282                 };
 283
 284                 pinctrl_fec: fecgrp {
 285                         fsl,pins = <
 286                                 MX53_PAD_FEC_MDC__FEC_MDC               0x80000000
 287                                 MX53_PAD_FEC_MDIO__FEC_MDIO             0x80000000
 288                                 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK        0x80000000
 289                                 MX53_PAD_FEC_RX_ER__FEC_RX_ER           0x80000000
 290                                 MX53_PAD_FEC_CRS_DV__FEC_RX_DV          0x80000000
 291                                 MX53_PAD_FEC_RXD1__FEC_RDATA_1          0x80000000
 292                                 MX53_PAD_FEC_RXD0__FEC_RDATA_0          0x80000000
 293                                 MX53_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
 294                                 MX53_PAD_FEC_TXD1__FEC_TDATA_1          0x80000000
 295                                 MX53_PAD_FEC_TXD0__FEC_TDATA_0          0x80000000
 296                         >;
 297                 };
 298
 299                 pinctrl_i2c1: i2c1grp {
 300                         fsl,pins = <
 301                                 MX53_PAD_EIM_D21__I2C1_SCL              0xc0000000
 302                                 MX53_PAD_EIM_D28__I2C1_SDA              0xc0000000
 303                         >;
 304                 };
 305
 306                 pinctrl_i2c2: i2c2grp {
 307                         fsl,pins = <
 308                                 MX53_PAD_EIM_D16__I2C2_SDA              0xc0000000
 309                                 MX53_PAD_EIM_EB2__I2C2_SCL              0xc0000000
 310                         >;
 311                 };
 312
 313                 pinctrl_i2c3: i2c3grp {
 314                         fsl,pins = <
 315                                 MX53_PAD_GPIO_6__I2C3_SDA               0xc0000000
 316                                 MX53_PAD_GPIO_5__I2C3_SCL               0xc0000000
 317                         >;
 318                 };
 319
 320                 pinctrl_ipu_disp1: ipudisp1grp {
 321                         fsl,pins = <
 322                                 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0       0x5
 323                                 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1       0x5
 324                                 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2       0x5
 325                                 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3       0x5
 326                                 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4       0x5
 327                                 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5       0x5
 328                                 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6       0x5
 329                                 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7       0x5
 330                                 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8       0x5
 331                                 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9       0x5
 332                                 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10      0x5
 333                                 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11      0x5
 334                                 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12      0x5
 335                                 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13      0x5
 336                                 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14      0x5
 337                                 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15      0x5
 338                                 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16      0x5
 339                                 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17      0x5
 340                                 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18      0x5
 341                                 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19      0x5
 342                                 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20      0x5
 343                                 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21      0x5
 344                                 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22      0x5
 345                                 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23      0x5
 346                                 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK      0x5
 347                                 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS        0x5
 348                                 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS        0x5
 349                                 MX53_PAD_EIM_DA15__IPU_DI1_PIN1         0x5
 350                                 MX53_PAD_EIM_DA11__IPU_DI1_PIN2         0x5
 351                                 MX53_PAD_EIM_DA12__IPU_DI1_PIN3         0x5
 352                                 MX53_PAD_EIM_A25__IPU_DI1_PIN12         0x5
 353                                 MX53_PAD_EIM_DA10__IPU_DI1_PIN15        0x5
 354                         >;
 355                 };
 356
 357                 pinctrl_nand: nandgrp {
 358                         fsl,pins = <
 359                                 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B     0x4
 360                                 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B     0x4
 361                                 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE       0x4
 362                                 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE       0x4
 363                                 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B     0xe0
 364                                 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0      0xe0
 365                                 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0      0x4
 366                                 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0      0xa4
 367                                 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1      0xa4
 368                                 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2      0xa4
 369                                 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3      0xa4
 370                                 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4      0xa4
 371                                 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5      0xa4
 372                                 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6      0xa4
 373                                 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7      0xa4
 374                         >;
 375                 };
 376
 377                 pinctrl_pwm1: pwm1grp {
 378                         fsl,pins = <
 379                                 MX53_PAD_DISP0_DAT8__PWM1_PWMO          0x5
 380                         >;
 381                 };
 382
 383                 pinctrl_uart1: uart1grp {
 384                         fsl,pins = <
 385                                 MX53_PAD_PATA_DIOW__UART1_TXD_MUX       0x1e4
 386                                 MX53_PAD_PATA_DMACK__UART1_RXD_MUX      0x1e4
 387                         >;
 388                 };
 389
 390                 pinctrl_uart2: uart2grp {
 391                         fsl,pins = <
 392                                 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX  0x1e4
 393                                 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX      0x1e4
 394                         >;
 395                 };
 396
 397                 pinctrl_uart3: uart3grp {
 398                         fsl,pins = <
 399                                 MX53_PAD_PATA_CS_0__UART3_TXD_MUX       0x1e4
 400                                 MX53_PAD_PATA_CS_1__UART3_RXD_MUX       0x1e4
 401                                 MX53_PAD_PATA_DA_1__UART3_CTS           0x1e4
 402                                 MX53_PAD_PATA_DA_2__UART3_RTS           0x1e4
 403                         >;
 404                 };
 405         };
 406 };
 407
 408 &ipu_di1_disp1 {
 409         remote-endpoint = <&display1_in>;
 410 };
 411
 412 &nfc {
 413         pinctrl-names = "default";
 414         pinctrl-0 = <&pinctrl_nand>;
 415         nand-bus-width = <8>;
 416         nand-ecc-mode = "hw";
 417         status = "okay";
 418 };
 419
 420 &pwm1 {
 421         pinctrl-names = "default";
 422         pinctrl-0 = <&pinctrl_pwm1>;
 423         status = "okay";
 424 };
 425
 426 &sata {
 427         status = "okay";
 428 };
 429
 430 &ssi2 {
 431         fsl,mode = "i2s-slave";
 432         status = "okay";
 433 };
 434
 435 &uart1 {
 436         pinctrl-names = "default";
 437         pinctrl-0 = <&pinctrl_uart1>;
 438         status = "okay";
 439 };
 440
 441 &uart2 {
 442         pinctrl-names = "default";
 443         pinctrl-0 = <&pinctrl_uart2>;
 444         status = "okay";
 445 };
 446
 447 &uart3 {
 448         pinctrl-names = "default";
 449         pinctrl-0 = <&pinctrl_uart3>;
 450         status = "okay";
 451 };
 452
 453 &usbh1 {
 454         vbus-supply = <&reg_usbh1_vbus>;
 455         phy_type = "utmi";
 456         status = "okay";
 457 };
 458
 459 &usbotg {
 460         dr_mode = "peripheral";
 461         status = "okay";
 462 };