arch/arm/boot/dts/imx53-m53evk.dts

   1 /*
   2  * Copyright (C) 2013 Marek Vasut <marex@denx.de>
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 /dts-v1/;
  13 #include "imx53.dtsi"
  14
  15 / {
  16         model = "DENX M53EVK";
  17         compatible = "denx,imx53-m53evk", "fsl,imx53";
  18
  19         memory {
  20                 reg = <0x70000000 0x20000000>;
  21         };
  22
  23         soc {
  24                 display@di1 {
  25                         compatible = "fsl,imx-parallel-display";
  26                         crtcs = <&ipu 1>;
  27                         interface-pix-fmt = "bgr666";
  28                         pinctrl-names = "default";
  29                         pinctrl-0 = <&pinctrl_ipu_disp1>;
  30
  31                         display-timings {
  32                                 800x480p60 {
  33                                         native-mode;
  34                                         clock-frequency = <31500000>;
  35                                         hactive = <800>;
  36                                         vactive = <480>;
  37                                         hfront-porch = <40>;
  38                                         hback-porch = <88>;
  39                                         hsync-len = <128>;
  40                                         vback-porch = <33>;
  41                                         vfront-porch = <9>;
  42                                         vsync-len = <3>;
  43                                         vsync-active = <1>;
  44                                 };
  45                         };
  46                 };
  47         };
  48
  49         backlight {
  50                 compatible = "pwm-backlight";
  51                 pwms = <&pwm1 0 3000>;
  52                 brightness-levels = <0 4 8 16 32 64 128 255>;
  53                 default-brightness-level = <6>;
  54                 power-supply = <&reg_backlight>;
  55         };
  56
  57         leds {
  58                 compatible = "gpio-leds";
  59                 pinctrl-names = "default";
  60                 pinctrl-0 = <&led_pin_gpio>;
  61
  62                 user1 {
  63                         label = "user1";
  64                         gpios = <&gpio2 8 0>;
  65                         linux,default-trigger = "heartbeat";
  66                 };
  67
  68                 user2 {
  69                         label = "user2";
  70                         gpios = <&gpio2 9 0>;
  71                         linux,default-trigger = "heartbeat";
  72                 };
  73         };
  74
  75         regulators {
  76                 compatible = "simple-bus";
  77                 #address-cells = <1>;
  78                 #size-cells = <0>;
  79
  80                 reg_3p2v: regulator@0 {
  81                         compatible = "regulator-fixed";
  82                         reg = <0>;
  83                         regulator-name = "3P2V";
  84                         regulator-min-microvolt = <3200000>;
  85                         regulator-max-microvolt = <3200000>;
  86                         regulator-always-on;
  87                 };
  88
  89
  90                 reg_backlight: regulator@1 {
  91                         compatible = "regulator-fixed";
  92                         reg = <1>;
  93                         regulator-name = "lcd-supply";
  94                         regulator-min-microvolt = <3200000>;
  95                         regulator-max-microvolt = <3200000>;
  96                         regulator-always-on;
  97                 };
  98
  99                 reg_usbh1_vbus: regulator@3 {
 100                         compatible = "regulator-fixed";
 101                         reg = <3>;
 102                         regulator-name = "vbus";
 103                         regulator-min-microvolt = <5000000>;
 104                         regulator-max-microvolt = <5000000>;
 105                         gpio = <&gpio1 2 0>;
 106                         enable-active-low;
 107                 };
 108         };
 109
 110         sound {
 111                 compatible = "fsl,imx53-m53evk-sgtl5000",
 112                              "fsl,imx-audio-sgtl5000";
 113                 model = "imx53-m53evk-sgtl5000";
 114                 ssi-controller = <&ssi2>;
 115                 audio-codec = <&sgtl5000>;
 116                 audio-routing =
 117                         "MIC_IN", "Mic Jack",
 118                         "Mic Jack", "Mic Bias",
 119                         "LINE_IN", "Line In Jack",
 120                         "Headphone Jack", "HP_OUT",
 121                         "Ext Spk", "LINE_OUT";
 122                 mux-int-port = <2>;
 123                 mux-ext-port = <4>;
 124         };
 125 };
 126
 127 &audmux {
 128         pinctrl-names = "default";
 129         pinctrl-0 = <&pinctrl_audmux>;
 130         status = "okay";
 131 };
 132
 133 &can1 {
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&pinctrl_can1>;
 136         status = "okay";
 137 };
 138
 139 &can2 {
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&pinctrl_can2>;
 142         status = "okay";
 143 };
 144
 145 &esdhc1 {
 146         pinctrl-names = "default";
 147         pinctrl-0 = <&pinctrl_esdhc1>;
 148         cd-gpios = <&gpio1 1 0>;
 149         wp-gpios = <&gpio1 9 0>;
 150         status = "okay";
 151 };
 152
 153 &fec {
 154         pinctrl-names = "default";
 155         pinctrl-0 = <&pinctrl_fec>;
 156         phy-mode = "rmii";
 157         status = "okay";
 158 };
 159
 160 &i2c1 {
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&pinctrl_i2c1>;
 163         status = "okay";
 164
 165         sgtl5000: codec@0a {
 166                 compatible = "fsl,sgtl5000";
 167                 reg = <0x0a>;
 168                 VDDA-supply = <&reg_3p2v>;
 169                 VDDIO-supply = <&reg_3p2v>;
 170                 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
 171         };
 172 };
 173
 174 &i2c2 {
 175         pinctrl-names = "default";
 176         pinctrl-0 = <&pinctrl_i2c2>;
 177         clock-frequency = <400000>;
 178         status = "okay";
 179
 180         stmpe610@41 {
 181                 compatible = "st,stmpe610";
 182                 #address-cells = <1>;
 183                 #size-cells = <0>;
 184                 reg = <0x41>;
 185                 id = <0>;
 186                 blocks = <0x5>;
 187                 interrupts = <6 0x0>;
 188                 interrupt-parent = <&gpio7>;
 189                 irq-trigger = <0x1>;
 190
 191                 stmpe_touchscreen {
 192                         compatible = "stmpe,ts";
 193                         reg = <0>;
 194                         ts,sample-time = <4>;
 195                         ts,mod-12b = <1>;
 196                         ts,ref-sel = <0>;
 197                         ts,adc-freq = <1>;
 198                         ts,ave-ctrl = <3>;
 199                         ts,touch-det-delay = <3>;
 200                         ts,settling = <4>;
 201                         ts,fraction-z = <7>;
 202                         ts,i-drive = <1>;
 203                 };
 204         };
 205
 206         eeprom: eeprom@50 {
 207                 compatible = "atmel,24c128";
 208                 reg = <0x50>;
 209                 pagesize = <32>;
 210         };
 211
 212         rtc: rtc@68 {
 213                 compatible = "stm,m41t62";
 214                 reg = <0x68>;
 215         };
 216 };
 217
 218 &i2c3 {
 219         pinctrl-names = "default";
 220         pinctrl-0 = <&pinctrl_i2c3>;
 221         status = "okay";
 222 };
 223
 224 &iomuxc {
 225         pinctrl-names = "default";
 226         pinctrl-0 = <&pinctrl_hog>;
 227
 228         imx53-m53evk {
 229                 pinctrl_hog: hoggrp {
 230                         fsl,pins = <
 231                                 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK       0x80000000
 232                                 MX53_PAD_EIM_EB3__GPIO2_31              0x80000000
 233                                 MX53_PAD_PATA_DA_0__GPIO7_6             0x80000000
 234                                 MX53_PAD_GPIO_2__GPIO1_2                0x80000000
 235                                 MX53_PAD_GPIO_3__USBOH3_USBH1_OC        0x80000000
 236                         >;
 237                 };
 238
 239                 led_pin_gpio: led_gpio@0 {
 240                         fsl,pins = <
 241                                 MX53_PAD_PATA_DATA8__GPIO2_8            0x80000000
 242                                 MX53_PAD_PATA_DATA9__GPIO2_9            0x80000000
 243                         >;
 244                 };
 245
 246                 pinctrl_audmux: audmuxgrp {
 247                         fsl,pins = <
 248                                 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC     0x80000000
 249                                 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD     0x80000000
 250                                 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS    0x80000000
 251                                 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD     0x80000000
 252                         >;
 253                 };
 254
 255                 pinctrl_can1: can1grp {
 256                         fsl,pins = <
 257                                 MX53_PAD_GPIO_7__CAN1_TXCAN             0x80000000
 258                                 MX53_PAD_GPIO_8__CAN1_RXCAN             0x80000000
 259                         >;
 260                 };
 261
 262                 pinctrl_can2: can2grp {
 263                         fsl,pins = <
 264                                 MX53_PAD_KEY_COL4__CAN2_TXCAN           0x80000000
 265                                 MX53_PAD_KEY_ROW4__CAN2_RXCAN           0x80000000
 266                         >;
 267                 };
 268
 269                 pinctrl_esdhc1: esdhc1grp {
 270                         fsl,pins = <
 271                                 MX53_PAD_SD1_DATA0__ESDHC1_DAT0         0x1d5
 272                                 MX53_PAD_SD1_DATA1__ESDHC1_DAT1         0x1d5
 273                                 MX53_PAD_SD1_DATA2__ESDHC1_DAT2         0x1d5
 274                                 MX53_PAD_SD1_DATA3__ESDHC1_DAT3         0x1d5
 275                                 MX53_PAD_SD1_CMD__ESDHC1_CMD            0x1d5
 276                                 MX53_PAD_SD1_CLK__ESDHC1_CLK            0x1d5
 277                         >;
 278                 };
 279
 280                 pinctrl_fec: fecgrp {
 281                         fsl,pins = <
 282                                 MX53_PAD_FEC_MDC__FEC_MDC               0x80000000
 283                                 MX53_PAD_FEC_MDIO__FEC_MDIO             0x80000000
 284                                 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK        0x80000000
 285                                 MX53_PAD_FEC_RX_ER__FEC_RX_ER           0x80000000
 286                                 MX53_PAD_FEC_CRS_DV__FEC_RX_DV          0x80000000
 287                                 MX53_PAD_FEC_RXD1__FEC_RDATA_1          0x80000000
 288                                 MX53_PAD_FEC_RXD0__FEC_RDATA_0          0x80000000
 289                                 MX53_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
 290                                 MX53_PAD_FEC_TXD1__FEC_TDATA_1          0x80000000
 291                                 MX53_PAD_FEC_TXD0__FEC_TDATA_0          0x80000000
 292                         >;
 293                 };
 294
 295                 pinctrl_i2c1: i2c1grp {
 296                         fsl,pins = <
 297                                 MX53_PAD_EIM_D21__I2C1_SCL              0xc0000000
 298                                 MX53_PAD_EIM_D28__I2C1_SDA              0xc0000000
 299                         >;
 300                 };
 301
 302                 pinctrl_i2c2: i2c2grp {
 303                         fsl,pins = <
 304                                 MX53_PAD_EIM_D16__I2C2_SDA              0xc0000000
 305                                 MX53_PAD_EIM_EB2__I2C2_SCL              0xc0000000
 306                         >;
 307                 };
 308
 309                 pinctrl_i2c3: i2c3grp {
 310                         fsl,pins = <
 311                                 MX53_PAD_GPIO_6__I2C3_SDA               0xc0000000
 312                                 MX53_PAD_GPIO_5__I2C3_SCL               0xc0000000
 313                         >;
 314                 };
 315
 316                 pinctrl_ipu_disp1: ipudisp1grp {
 317                         fsl,pins = <
 318                                 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0       0x5
 319                                 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1       0x5
 320                                 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2       0x5
 321                                 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3       0x5
 322                                 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4       0x5
 323                                 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5       0x5
 324                                 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6       0x5
 325                                 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7       0x5
 326                                 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8       0x5
 327                                 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9       0x5
 328                                 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10      0x5
 329                                 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11      0x5
 330                                 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12      0x5
 331                                 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13      0x5
 332                                 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14      0x5
 333                                 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15      0x5
 334                                 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16      0x5
 335                                 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17      0x5
 336                                 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18      0x5
 337                                 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19      0x5
 338                                 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20      0x5
 339                                 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21      0x5
 340                                 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22      0x5
 341                                 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23      0x5
 342                                 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK      0x5
 343                                 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS        0x5
 344                                 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS        0x5
 345                                 MX53_PAD_EIM_DA15__IPU_DI1_PIN1         0x5
 346                                 MX53_PAD_EIM_DA11__IPU_DI1_PIN2         0x5
 347                                 MX53_PAD_EIM_DA12__IPU_DI1_PIN3         0x5
 348                                 MX53_PAD_EIM_A25__IPU_DI1_PIN12         0x5
 349                                 MX53_PAD_EIM_DA10__IPU_DI1_PIN15        0x5
 350                         >;
 351                 };
 352
 353                 pinctrl_nand: nandgrp {
 354                         fsl,pins = <
 355                                 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B     0x4
 356                                 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B     0x4
 357                                 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE       0x4
 358                                 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE       0x4
 359                                 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B     0xe0
 360                                 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0      0xe0
 361                                 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0      0x4
 362                                 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0      0xa4
 363                                 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1      0xa4
 364                                 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2      0xa4
 365                                 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3      0xa4
 366                                 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4      0xa4
 367                                 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5      0xa4
 368                                 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6      0xa4
 369                                 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7      0xa4
 370                         >;
 371                 };
 372
 373                 pinctrl_pwm1: pwm1grp {
 374                         fsl,pins = <
 375                                 MX53_PAD_DISP0_DAT8__PWM1_PWMO          0x5
 376                         >;
 377                 };
 378
 379                 pinctrl_uart1: uart1grp {
 380                         fsl,pins = <
 381                                 MX53_PAD_PATA_DIOW__UART1_TXD_MUX       0x1e4
 382                                 MX53_PAD_PATA_DMACK__UART1_RXD_MUX      0x1e4
 383                         >;
 384                 };
 385
 386                 pinctrl_uart2: uart2grp {
 387                         fsl,pins = <
 388                                 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX  0x1e4
 389                                 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX      0x1e4
 390                         >;
 391                 };
 392
 393                 pinctrl_uart3: uart3grp {
 394                         fsl,pins = <
 395                                 MX53_PAD_PATA_CS_0__UART3_TXD_MUX       0x1e4
 396                                 MX53_PAD_PATA_CS_1__UART3_RXD_MUX       0x1e4
 397                                 MX53_PAD_PATA_DA_1__UART3_CTS           0x1e4
 398                                 MX53_PAD_PATA_DA_2__UART3_RTS           0x1e4
 399                         >;
 400                 };
 401         };
 402 };
 403
 404 &nfc {
 405         pinctrl-names = "default";
 406         pinctrl-0 = <&pinctrl_nand>;
 407         nand-bus-width = <8>;
 408         nand-ecc-mode = "hw";
 409         status = "okay";
 410 };
 411
 412 &pwm1 {
 413         pinctrl-names = "default";
 414         pinctrl-0 = <&pinctrl_pwm1>;
 415         status = "okay";
 416 };
 417
 418 &sata {
 419         status = "okay";
 420 };
 421
 422 &ssi2 {
 423         fsl,mode = "i2s-slave";
 424         status = "okay";
 425 };
 426
 427 &uart1 {
 428         pinctrl-names = "default";
 429         pinctrl-0 = <&pinctrl_uart1>;
 430         status = "okay";
 431 };
 432
 433 &uart2 {
 434         pinctrl-names = "default";
 435         pinctrl-0 = <&pinctrl_uart2>;
 436         status = "okay";
 437 };
 438
 439 &uart3 {
 440         pinctrl-names = "default";
 441         pinctrl-0 = <&pinctrl_uart3>;
 442         status = "okay";
 443 };
 444
 445 &usbh1 {
 446         vbus-supply = <&reg_usbh1_vbus>;
 447         phy_type = "utmi";
 448         status = "okay";
 449 };
 450
 451 &usbotg {
 452         dr_mode = "peripheral";
 453         status = "okay";
 454 };