2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx51-pinfunc.h"
27 tzic: tz-interrupt-controller@e0000000 {
28 compatible = "fsl,imx51-tzic", "fsl,tzic";
30 #interrupt-cells = <1>;
31 reg = <0xe0000000 0x4000>;
39 compatible = "fsl,imx-ckil", "fixed-clock";
40 clock-frequency = <32768>;
44 compatible = "fsl,imx-ckih1", "fixed-clock";
45 clock-frequency = <22579200>;
49 compatible = "fsl,imx-ckih2", "fixed-clock";
50 clock-frequency = <0>;
54 compatible = "fsl,imx-osc", "fixed-clock";
55 clock-frequency = <24000000>;
62 compatible = "simple-bus";
63 interrupt-parent = <&tzic>;
68 compatible = "fsl,imx51-ipu";
69 reg = <0x40000000 0x20000000>;
71 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
72 clock-names = "bus", "di0", "di1";
76 aips@70000000 { /* AIPS1 */
77 compatible = "fsl,aips-bus", "simple-bus";
80 reg = <0x70000000 0x10000000>;
84 compatible = "fsl,spba-bus", "simple-bus";
87 reg = <0x70000000 0x40000>;
90 esdhc1: esdhc@70004000 {
91 compatible = "fsl,imx51-esdhc";
92 reg = <0x70004000 0x4000>;
94 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
95 clock-names = "ipg", "ahb", "per";
99 esdhc2: esdhc@70008000 {
100 compatible = "fsl,imx51-esdhc";
101 reg = <0x70008000 0x4000>;
103 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
104 clock-names = "ipg", "ahb", "per";
109 uart3: serial@7000c000 {
110 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
111 reg = <0x7000c000 0x4000>;
113 clocks = <&clks 32>, <&clks 33>;
114 clock-names = "ipg", "per";
118 ecspi1: ecspi@70010000 {
119 #address-cells = <1>;
121 compatible = "fsl,imx51-ecspi";
122 reg = <0x70010000 0x4000>;
124 clocks = <&clks 51>, <&clks 52>;
125 clock-names = "ipg", "per";
130 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
131 reg = <0x70014000 0x4000>;
134 fsl,fifo-depth = <15>;
135 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
139 esdhc3: esdhc@70020000 {
140 compatible = "fsl,imx51-esdhc";
141 reg = <0x70020000 0x4000>;
143 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
144 clock-names = "ipg", "ahb", "per";
149 esdhc4: esdhc@70024000 {
150 compatible = "fsl,imx51-esdhc";
151 reg = <0x70024000 0x4000>;
153 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
154 clock-names = "ipg", "ahb", "per";
160 usbotg: usb@73f80000 {
161 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
162 reg = <0x73f80000 0x0200>;
167 usbh1: usb@73f80200 {
168 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
169 reg = <0x73f80200 0x0200>;
174 usbh2: usb@73f80400 {
175 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
176 reg = <0x73f80400 0x0200>;
181 usbh3: usb@73f80600 {
182 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
183 reg = <0x73f80600 0x0200>;
188 gpio1: gpio@73f84000 {
189 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
190 reg = <0x73f84000 0x4000>;
191 interrupts = <50 51>;
194 interrupt-controller;
195 #interrupt-cells = <2>;
198 gpio2: gpio@73f88000 {
199 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
200 reg = <0x73f88000 0x4000>;
201 interrupts = <52 53>;
204 interrupt-controller;
205 #interrupt-cells = <2>;
208 gpio3: gpio@73f8c000 {
209 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
210 reg = <0x73f8c000 0x4000>;
211 interrupts = <54 55>;
214 interrupt-controller;
215 #interrupt-cells = <2>;
218 gpio4: gpio@73f90000 {
219 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
220 reg = <0x73f90000 0x4000>;
221 interrupts = <56 57>;
224 interrupt-controller;
225 #interrupt-cells = <2>;
229 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
230 reg = <0x73f94000 0x4000>;
236 wdog1: wdog@73f98000 {
237 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
238 reg = <0x73f98000 0x4000>;
243 wdog2: wdog@73f9c000 {
244 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
245 reg = <0x73f9c000 0x4000>;
251 gpt: timer@73fa0000 {
252 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
253 reg = <0x73fa0000 0x4000>;
255 clocks = <&clks 36>, <&clks 41>;
256 clock-names = "ipg", "per";
259 iomuxc: iomuxc@73fa8000 {
260 compatible = "fsl,imx51-iomuxc";
261 reg = <0x73fa8000 0x4000>;
264 pinctrl_audmux_1: audmuxgrp-1 {
266 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
267 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
268 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
269 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
275 pinctrl_fec_1: fecgrp-1 {
277 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
278 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
279 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
280 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
281 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
282 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
283 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
284 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
285 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
286 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
287 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
288 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
289 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
290 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
291 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
292 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
293 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
297 pinctrl_fec_2: fecgrp-2 {
299 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
300 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
301 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
302 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
303 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
304 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
305 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
306 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
307 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
308 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
309 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
310 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
311 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
312 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
313 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
314 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
315 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
316 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
322 pinctrl_ecspi1_1: ecspi1grp-1 {
324 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
325 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
326 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
332 pinctrl_ecspi2_1: ecspi2grp-1 {
334 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
335 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
336 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
342 pinctrl_esdhc1_1: esdhc1grp-1 {
344 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
345 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
346 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
347 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
348 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
349 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
355 pinctrl_esdhc2_1: esdhc2grp-1 {
357 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
358 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
359 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
360 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
361 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
362 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
368 pinctrl_i2c2_1: i2c2grp-1 {
370 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
371 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
375 pinctrl_i2c2_2: i2c2grp-2 {
377 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
378 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
384 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
386 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
387 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
388 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
389 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
390 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
391 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
392 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
393 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
394 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
395 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
396 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
397 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
398 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
399 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
400 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
401 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
402 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
403 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
404 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
405 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
406 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
407 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
408 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
409 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
410 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
411 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
417 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
419 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
420 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
421 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
422 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
423 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
424 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
425 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
426 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
427 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
428 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
429 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
430 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
431 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
432 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
433 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
434 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
435 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
436 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
437 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
438 MX51_PAD_DI_GP4__DI2_PIN15 0x5
444 pinctrl_uart1_1: uart1grp-1 {
446 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
447 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
448 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
449 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
455 pinctrl_uart2_1: uart2grp-1 {
457 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
458 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
464 pinctrl_uart3_1: uart3grp-1 {
466 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
467 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
468 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
469 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
473 pinctrl_uart3_2: uart3grp-2 {
475 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
476 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
482 pinctrl_kpp_1: kppgrp-1 {
484 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
485 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
486 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
487 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
488 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
489 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
490 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
491 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
499 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
500 reg = <0x73fb4000 0x4000>;
501 clocks = <&clks 37>, <&clks 38>;
502 clock-names = "ipg", "per";
508 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
509 reg = <0x73fb8000 0x4000>;
510 clocks = <&clks 39>, <&clks 40>;
511 clock-names = "ipg", "per";
515 uart1: serial@73fbc000 {
516 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
517 reg = <0x73fbc000 0x4000>;
519 clocks = <&clks 28>, <&clks 29>;
520 clock-names = "ipg", "per";
524 uart2: serial@73fc0000 {
525 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
526 reg = <0x73fc0000 0x4000>;
528 clocks = <&clks 30>, <&clks 31>;
529 clock-names = "ipg", "per";
534 compatible = "fsl,imx51-src";
535 reg = <0x73fd0000 0x4000>;
540 compatible = "fsl,imx51-ccm";
541 reg = <0x73fd4000 0x4000>;
542 interrupts = <0 71 0x04 0 72 0x04>;
547 aips@80000000 { /* AIPS2 */
548 compatible = "fsl,aips-bus", "simple-bus";
549 #address-cells = <1>;
551 reg = <0x80000000 0x10000000>;
554 ecspi2: ecspi@83fac000 {
555 #address-cells = <1>;
557 compatible = "fsl,imx51-ecspi";
558 reg = <0x83fac000 0x4000>;
560 clocks = <&clks 53>, <&clks 54>;
561 clock-names = "ipg", "per";
565 sdma: sdma@83fb0000 {
566 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
567 reg = <0x83fb0000 0x4000>;
569 clocks = <&clks 56>, <&clks 56>;
570 clock-names = "ipg", "ahb";
571 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
574 cspi: cspi@83fc0000 {
575 #address-cells = <1>;
577 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
578 reg = <0x83fc0000 0x4000>;
580 clocks = <&clks 55>, <&clks 0>;
581 clock-names = "ipg", "per";
586 #address-cells = <1>;
588 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
589 reg = <0x83fc4000 0x4000>;
596 #address-cells = <1>;
598 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
599 reg = <0x83fc8000 0x4000>;
606 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
607 reg = <0x83fcc000 0x4000>;
610 fsl,fifo-depth = <15>;
611 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
615 audmux: audmux@83fd0000 {
616 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
617 reg = <0x83fd0000 0x4000>;
622 compatible = "fsl,imx51-nand";
623 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
630 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
631 reg = <0x83fe8000 0x4000>;
634 fsl,fifo-depth = <15>;
635 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
639 fec: ethernet@83fec000 {
640 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
641 reg = <0x83fec000 0x4000>;
643 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
644 clock-names = "ipg", "ahb", "ptp";