arch/arm/boot/dts/imx51.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14 #include "imx51-pinfunc.h"
  15
  16 / {
  17         aliases {
  18                 serial0 = &uart1;
  19                 serial1 = &uart2;
  20                 serial2 = &uart3;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25         };
  26
  27         tzic: tz-interrupt-controller@e0000000 {
  28                 compatible = "fsl,imx51-tzic", "fsl,tzic";
  29                 interrupt-controller;
  30                 #interrupt-cells = <1>;
  31                 reg = <0xe0000000 0x4000>;
  32         };
  33
  34         clocks {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 ckil {
  39                         compatible = "fsl,imx-ckil", "fixed-clock";
  40                         clock-frequency = <32768>;
  41                 };
  42
  43                 ckih1 {
  44                         compatible = "fsl,imx-ckih1", "fixed-clock";
  45                         clock-frequency = <22579200>;
  46                 };
  47
  48                 ckih2 {
  49                         compatible = "fsl,imx-ckih2", "fixed-clock";
  50                         clock-frequency = <0>;
  51                 };
  52
  53                 osc {
  54                         compatible = "fsl,imx-osc", "fixed-clock";
  55                         clock-frequency = <24000000>;
  56                 };
  57         };
  58
  59         cpus {
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62                 cpu@0 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a8";
  65                         reg = <0>;
  66                         clock-latency = <61036>; /* two CLK32 periods */
  67                         clocks = <&clks 24>;
  68                         clock-names = "cpu";
  69                         operating-points = <
  70                                 /* kHz  uV (No regulator support) */
  71                                 160000  0
  72                                 800000  0
  73                         >;
  74                 };
  75         };
  76
  77         soc {
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80                 compatible = "simple-bus";
  81                 interrupt-parent = <&tzic>;
  82                 ranges;
  83
  84                 ipu: ipu@40000000 {
  85                         #crtc-cells = <1>;
  86                         compatible = "fsl,imx51-ipu";
  87                         reg = <0x40000000 0x20000000>;
  88                         interrupts = <11 10>;
  89                         clocks = <&clks 59>, <&clks 110>, <&clks 61>;
  90                         clock-names = "bus", "di0", "di1";
  91                         resets = <&src 2>;
  92                 };
  93
  94                 aips@70000000 { /* AIPS1 */
  95                         compatible = "fsl,aips-bus", "simple-bus";
  96                         #address-cells = <1>;
  97                         #size-cells = <1>;
  98                         reg = <0x70000000 0x10000000>;
  99                         ranges;
 100
 101                         spba@70000000 {
 102                                 compatible = "fsl,spba-bus", "simple-bus";
 103                                 #address-cells = <1>;
 104                                 #size-cells = <1>;
 105                                 reg = <0x70000000 0x40000>;
 106                                 ranges;
 107
 108                                 esdhc1: esdhc@70004000 {
 109                                         compatible = "fsl,imx51-esdhc";
 110                                         reg = <0x70004000 0x4000>;
 111                                         interrupts = <1>;
 112                                         clocks = <&clks 44>, <&clks 0>, <&clks 71>;
 113                                         clock-names = "ipg", "ahb", "per";
 114                                         status = "disabled";
 115                                 };
 116
 117                                 esdhc2: esdhc@70008000 {
 118                                         compatible = "fsl,imx51-esdhc";
 119                                         reg = <0x70008000 0x4000>;
 120                                         interrupts = <2>;
 121                                         clocks = <&clks 45>, <&clks 0>, <&clks 72>;
 122                                         clock-names = "ipg", "ahb", "per";
 123                                         bus-width = <4>;
 124                                         status = "disabled";
 125                                 };
 126
 127                                 uart3: serial@7000c000 {
 128                                         compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 129                                         reg = <0x7000c000 0x4000>;
 130                                         interrupts = <33>;
 131                                         clocks = <&clks 32>, <&clks 33>;
 132                                         clock-names = "ipg", "per";
 133                                         status = "disabled";
 134                                 };
 135
 136                                 ecspi1: ecspi@70010000 {
 137                                         #address-cells = <1>;
 138                                         #size-cells = <0>;
 139                                         compatible = "fsl,imx51-ecspi";
 140                                         reg = <0x70010000 0x4000>;
 141                                         interrupts = <36>;
 142                                         clocks = <&clks 51>, <&clks 52>;
 143                                         clock-names = "ipg", "per";
 144                                         status = "disabled";
 145                                 };
 146
 147                                 ssi2: ssi@70014000 {
 148                                         compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 149                                         reg = <0x70014000 0x4000>;
 150                                         interrupts = <30>;
 151                                         clocks = <&clks 49>;
 152                                         fsl,fifo-depth = <15>;
 153                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 154                                         status = "disabled";
 155                                 };
 156
 157                                 esdhc3: esdhc@70020000 {
 158                                         compatible = "fsl,imx51-esdhc";
 159                                         reg = <0x70020000 0x4000>;
 160                                         interrupts = <3>;
 161                                         clocks = <&clks 46>, <&clks 0>, <&clks 73>;
 162                                         clock-names = "ipg", "ahb", "per";
 163                                         bus-width = <4>;
 164                                         status = "disabled";
 165                                 };
 166
 167                                 esdhc4: esdhc@70024000 {
 168                                         compatible = "fsl,imx51-esdhc";
 169                                         reg = <0x70024000 0x4000>;
 170                                         interrupts = <4>;
 171                                         clocks = <&clks 47>, <&clks 0>, <&clks 74>;
 172                                         clock-names = "ipg", "ahb", "per";
 173                                         bus-width = <4>;
 174                                         status = "disabled";
 175                                 };
 176                         };
 177
 178                         usbotg: usb@73f80000 {
 179                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 180                                 reg = <0x73f80000 0x0200>;
 181                                 interrupts = <18>;
 182                                 status = "disabled";
 183                         };
 184
 185                         usbh1: usb@73f80200 {
 186                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 187                                 reg = <0x73f80200 0x0200>;
 188                                 interrupts = <14>;
 189                                 status = "disabled";
 190                         };
 191
 192                         usbh2: usb@73f80400 {
 193                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 194                                 reg = <0x73f80400 0x0200>;
 195                                 interrupts = <16>;
 196                                 status = "disabled";
 197                         };
 198
 199                         usbh3: usb@73f80600 {
 200                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 201                                 reg = <0x73f80600 0x0200>;
 202                                 interrupts = <17>;
 203                                 status = "disabled";
 204                         };
 205
 206                         gpio1: gpio@73f84000 {
 207                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 208                                 reg = <0x73f84000 0x4000>;
 209                                 interrupts = <50 51>;
 210                                 gpio-controller;
 211                                 #gpio-cells = <2>;
 212                                 interrupt-controller;
 213                                 #interrupt-cells = <2>;
 214                         };
 215
 216                         gpio2: gpio@73f88000 {
 217                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 218                                 reg = <0x73f88000 0x4000>;
 219                                 interrupts = <52 53>;
 220                                 gpio-controller;
 221                                 #gpio-cells = <2>;
 222                                 interrupt-controller;
 223                                 #interrupt-cells = <2>;
 224                         };
 225
 226                         gpio3: gpio@73f8c000 {
 227                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 228                                 reg = <0x73f8c000 0x4000>;
 229                                 interrupts = <54 55>;
 230                                 gpio-controller;
 231                                 #gpio-cells = <2>;
 232                                 interrupt-controller;
 233                                 #interrupt-cells = <2>;
 234                         };
 235
 236                         gpio4: gpio@73f90000 {
 237                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 238                                 reg = <0x73f90000 0x4000>;
 239                                 interrupts = <56 57>;
 240                                 gpio-controller;
 241                                 #gpio-cells = <2>;
 242                                 interrupt-controller;
 243                                 #interrupt-cells = <2>;
 244                         };
 245
 246                         kpp: kpp@73f94000 {
 247                                 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
 248                                 reg = <0x73f94000 0x4000>;
 249                                 interrupts = <60>;
 250                                 clocks = <&clks 0>;
 251                                 status = "disabled";
 252                         };
 253
 254                         wdog1: wdog@73f98000 {
 255                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 256                                 reg = <0x73f98000 0x4000>;
 257                                 interrupts = <58>;
 258                                 clocks = <&clks 0>;
 259                         };
 260
 261                         wdog2: wdog@73f9c000 {
 262                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 263                                 reg = <0x73f9c000 0x4000>;
 264                                 interrupts = <59>;
 265                                 clocks = <&clks 0>;
 266                                 status = "disabled";
 267                         };
 268
 269                         gpt: timer@73fa0000 {
 270                                 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
 271                                 reg = <0x73fa0000 0x4000>;
 272                                 interrupts = <39>;
 273                                 clocks = <&clks 36>, <&clks 41>;
 274                                 clock-names = "ipg", "per";
 275                         };
 276
 277                         iomuxc: iomuxc@73fa8000 {
 278                                 compatible = "fsl,imx51-iomuxc";
 279                                 reg = <0x73fa8000 0x4000>;
 280
 281                                 audmux {
 282                                         pinctrl_audmux_1: audmuxgrp-1 {
 283                                                 fsl,pins = <
 284                                                         MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
 285                                                         MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
 286                                                         MX51_PAD_AUD3_BB_CK__AUD3_TXC  0x80000000
 287                                                         MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
 288                                                 >;
 289                                         };
 290                                 };
 291
 292                                 fec {
 293                                         pinctrl_fec_1: fecgrp-1 {
 294                                                 fsl,pins = <
 295                                                         MX51_PAD_EIM_EB2__FEC_MDIO         0x80000000
 296                                                         MX51_PAD_EIM_EB3__FEC_RDATA1       0x80000000
 297                                                         MX51_PAD_EIM_CS2__FEC_RDATA2       0x80000000
 298                                                         MX51_PAD_EIM_CS3__FEC_RDATA3       0x80000000
 299                                                         MX51_PAD_EIM_CS4__FEC_RX_ER        0x80000000
 300                                                         MX51_PAD_EIM_CS5__FEC_CRS          0x80000000
 301                                                         MX51_PAD_NANDF_RB2__FEC_COL        0x80000000
 302                                                         MX51_PAD_NANDF_RB3__FEC_RX_CLK     0x80000000
 303                                                         MX51_PAD_NANDF_D9__FEC_RDATA0      0x80000000
 304                                                         MX51_PAD_NANDF_D8__FEC_TDATA0      0x80000000
 305                                                         MX51_PAD_NANDF_CS2__FEC_TX_ER      0x80000000
 306                                                         MX51_PAD_NANDF_CS3__FEC_MDC        0x80000000
 307                                                         MX51_PAD_NANDF_CS4__FEC_TDATA1     0x80000000
 308                                                         MX51_PAD_NANDF_CS5__FEC_TDATA2     0x80000000
 309                                                         MX51_PAD_NANDF_CS6__FEC_TDATA3     0x80000000
 310                                                         MX51_PAD_NANDF_CS7__FEC_TX_EN      0x80000000
 311                                                         MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
 312                                                 >;
 313                                         };
 314
 315                                         pinctrl_fec_2: fecgrp-2 {
 316                                                 fsl,pins = <
 317                                                         MX51_PAD_DI_GP3__FEC_TX_ER        0x80000000
 318                                                         MX51_PAD_DI2_PIN4__FEC_CRS        0x80000000
 319                                                         MX51_PAD_DI2_PIN2__FEC_MDC        0x80000000
 320                                                         MX51_PAD_DI2_PIN3__FEC_MDIO       0x80000000
 321                                                         MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
 322                                                         MX51_PAD_DI_GP4__FEC_RDATA2       0x80000000
 323                                                         MX51_PAD_DISP2_DAT0__FEC_RDATA3   0x80000000
 324                                                         MX51_PAD_DISP2_DAT1__FEC_RX_ER    0x80000000
 325                                                         MX51_PAD_DISP2_DAT6__FEC_TDATA1   0x80000000
 326                                                         MX51_PAD_DISP2_DAT7__FEC_TDATA2   0x80000000
 327                                                         MX51_PAD_DISP2_DAT8__FEC_TDATA3   0x80000000
 328                                                         MX51_PAD_DISP2_DAT9__FEC_TX_EN    0x80000000
 329                                                         MX51_PAD_DISP2_DAT10__FEC_COL     0x80000000
 330                                                         MX51_PAD_DISP2_DAT11__FEC_RX_CLK  0x80000000
 331                                                         MX51_PAD_DISP2_DAT12__FEC_RX_DV   0x80000000
 332                                                         MX51_PAD_DISP2_DAT13__FEC_TX_CLK  0x80000000
 333                                                         MX51_PAD_DISP2_DAT14__FEC_RDATA0  0x80000000
 334                                                         MX51_PAD_DISP2_DAT15__FEC_TDATA0  0x80000000
 335                                                 >;
 336                                         };
 337                                 };
 338
 339                                 ecspi1 {
 340                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 341                                                 fsl,pins = <
 342                                                         MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
 343                                                         MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
 344                                                         MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
 345                                                 >;
 346                                         };
 347                                 };
 348
 349                                 ecspi2 {
 350                                         pinctrl_ecspi2_1: ecspi2grp-1 {
 351                                                 fsl,pins = <
 352                                                         MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
 353                                                         MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
 354                                                         MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
 355                                                 >;
 356                                         };
 357                                 };
 358
 359                                 esdhc1 {
 360                                         pinctrl_esdhc1_1: esdhc1grp-1 {
 361                                                 fsl,pins = <
 362                                                         MX51_PAD_SD1_CMD__SD1_CMD     0x400020d5
 363                                                         MX51_PAD_SD1_CLK__SD1_CLK     0x20d5
 364                                                         MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
 365                                                         MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
 366                                                         MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
 367                                                         MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
 368                                                 >;
 369                                         };
 370                                 };
 371
 372                                 esdhc2 {
 373                                         pinctrl_esdhc2_1: esdhc2grp-1 {
 374                                                 fsl,pins = <
 375                                                         MX51_PAD_SD2_CMD__SD2_CMD     0x400020d5
 376                                                         MX51_PAD_SD2_CLK__SD2_CLK     0x20d5
 377                                                         MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
 378                                                         MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
 379                                                         MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
 380                                                         MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
 381                                                 >;
 382                                         };
 383                                 };
 384
 385                                 i2c2 {
 386                                         pinctrl_i2c2_1: i2c2grp-1 {
 387                                                 fsl,pins = <
 388                                                         MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
 389                                                         MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
 390                                                 >;
 391                                         };
 392
 393                                         pinctrl_i2c2_2: i2c2grp-2 {
 394                                                 fsl,pins = <
 395                                                         MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
 396                                                         MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
 397                                                 >;
 398                                         };
 399                                 };
 400
 401                                 ipu_disp1 {
 402                                         pinctrl_ipu_disp1_1: ipudisp1grp-1 {
 403                                                 fsl,pins = <
 404                                                         MX51_PAD_DISP1_DAT0__DISP1_DAT0   0x5
 405                                                         MX51_PAD_DISP1_DAT1__DISP1_DAT1   0x5
 406                                                         MX51_PAD_DISP1_DAT2__DISP1_DAT2   0x5
 407                                                         MX51_PAD_DISP1_DAT3__DISP1_DAT3   0x5
 408                                                         MX51_PAD_DISP1_DAT4__DISP1_DAT4   0x5
 409                                                         MX51_PAD_DISP1_DAT5__DISP1_DAT5   0x5
 410                                                         MX51_PAD_DISP1_DAT6__DISP1_DAT6   0x5
 411                                                         MX51_PAD_DISP1_DAT7__DISP1_DAT7   0x5
 412                                                         MX51_PAD_DISP1_DAT8__DISP1_DAT8   0x5
 413                                                         MX51_PAD_DISP1_DAT9__DISP1_DAT9   0x5
 414                                                         MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
 415                                                         MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
 416                                                         MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
 417                                                         MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
 418                                                         MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
 419                                                         MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
 420                                                         MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
 421                                                         MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
 422                                                         MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
 423                                                         MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
 424                                                         MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
 425                                                         MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
 426                                                         MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
 427                                                         MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
 428                                                         MX51_PAD_DI1_PIN2__DI1_PIN2       0x5 /* hsync */
 429                                                         MX51_PAD_DI1_PIN3__DI1_PIN3       0x5 /* vsync */
 430                                                 >;
 431                                         };
 432                                 };
 433
 434                                 ipu_disp2 {
 435                                         pinctrl_ipu_disp2_1: ipudisp2grp-1 {
 436                                                 fsl,pins = <
 437                                                         MX51_PAD_DISP2_DAT0__DISP2_DAT0     0x5
 438                                                         MX51_PAD_DISP2_DAT1__DISP2_DAT1     0x5
 439                                                         MX51_PAD_DISP2_DAT2__DISP2_DAT2     0x5
 440                                                         MX51_PAD_DISP2_DAT3__DISP2_DAT3     0x5
 441                                                         MX51_PAD_DISP2_DAT4__DISP2_DAT4     0x5
 442                                                         MX51_PAD_DISP2_DAT5__DISP2_DAT5     0x5
 443                                                         MX51_PAD_DISP2_DAT6__DISP2_DAT6     0x5
 444                                                         MX51_PAD_DISP2_DAT7__DISP2_DAT7     0x5
 445                                                         MX51_PAD_DISP2_DAT8__DISP2_DAT8     0x5
 446                                                         MX51_PAD_DISP2_DAT9__DISP2_DAT9     0x5
 447                                                         MX51_PAD_DISP2_DAT10__DISP2_DAT10   0x5
 448                                                         MX51_PAD_DISP2_DAT11__DISP2_DAT11   0x5
 449                                                         MX51_PAD_DISP2_DAT12__DISP2_DAT12   0x5
 450                                                         MX51_PAD_DISP2_DAT13__DISP2_DAT13   0x5
 451                                                         MX51_PAD_DISP2_DAT14__DISP2_DAT14   0x5
 452                                                         MX51_PAD_DISP2_DAT15__DISP2_DAT15   0x5
 453                                                         MX51_PAD_DI2_PIN2__DI2_PIN2         0x5 /* hsync */
 454                                                         MX51_PAD_DI2_PIN3__DI2_PIN3         0x5 /* vsync */
 455                                                         MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
 456                                                         MX51_PAD_DI_GP4__DI2_PIN15          0x5
 457                                                 >;
 458                                         };
 459                                 };
 460
 461                                 pata {
 462                                         pinctrl_pata_1: patagrp-1 {
 463                                                 fsl,pins = <
 464                                                         MX51_PAD_NANDF_WE_B__PATA_DIOW          0x2004
 465                                                         MX51_PAD_NANDF_RE_B__PATA_DIOR          0x2004
 466                                                         MX51_PAD_NANDF_ALE__PATA_BUFFER_EN      0x2004
 467                                                         MX51_PAD_NANDF_CLE__PATA_RESET_B        0x2004
 468                                                         MX51_PAD_NANDF_WP_B__PATA_DMACK         0x2004
 469                                                         MX51_PAD_NANDF_RB0__PATA_DMARQ          0x2004
 470                                                         MX51_PAD_NANDF_RB1__PATA_IORDY          0x2004
 471                                                         MX51_PAD_GPIO_NAND__PATA_INTRQ          0x2004
 472                                                         MX51_PAD_NANDF_CS2__PATA_CS_0           0x2004
 473                                                         MX51_PAD_NANDF_CS3__PATA_CS_1           0x2004
 474                                                         MX51_PAD_NANDF_CS4__PATA_DA_0           0x2004
 475                                                         MX51_PAD_NANDF_CS5__PATA_DA_1           0x2004
 476                                                         MX51_PAD_NANDF_CS6__PATA_DA_2           0x2004
 477                                                         MX51_PAD_NANDF_D15__PATA_DATA15         0x2004
 478                                                         MX51_PAD_NANDF_D14__PATA_DATA14         0x2004
 479                                                         MX51_PAD_NANDF_D13__PATA_DATA13         0x2004
 480                                                         MX51_PAD_NANDF_D12__PATA_DATA12         0x2004
 481                                                         MX51_PAD_NANDF_D11__PATA_DATA11         0x2004
 482                                                         MX51_PAD_NANDF_D10__PATA_DATA10         0x2004
 483                                                         MX51_PAD_NANDF_D9__PATA_DATA9           0x2004
 484                                                         MX51_PAD_NANDF_D8__PATA_DATA8           0x2004
 485                                                         MX51_PAD_NANDF_D7__PATA_DATA7           0x2004
 486                                                         MX51_PAD_NANDF_D6__PATA_DATA6           0x2004
 487                                                         MX51_PAD_NANDF_D5__PATA_DATA5           0x2004
 488                                                         MX51_PAD_NANDF_D4__PATA_DATA4           0x2004
 489                                                         MX51_PAD_NANDF_D3__PATA_DATA3           0x2004
 490                                                         MX51_PAD_NANDF_D2__PATA_DATA2           0x2004
 491                                                         MX51_PAD_NANDF_D1__PATA_DATA1           0x2004
 492                                                         MX51_PAD_NANDF_D0__PATA_DATA0           0x2004
 493                                                 >;
 494                                         };
 495                                 };
 496
 497                                 uart1 {
 498                                         pinctrl_uart1_1: uart1grp-1 {
 499                                                 fsl,pins = <
 500                                                         MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
 501                                                         MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
 502                                                         MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
 503                                                         MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
 504                                                 >;
 505                                         };
 506                                 };
 507
 508                                 uart2 {
 509                                         pinctrl_uart2_1: uart2grp-1 {
 510                                                 fsl,pins = <
 511                                                         MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
 512                                                         MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
 513                                                 >;
 514                                         };
 515                                 };
 516
 517                                 uart3 {
 518                                         pinctrl_uart3_1: uart3grp-1 {
 519                                                 fsl,pins = <
 520                                                         MX51_PAD_EIM_D25__UART3_RXD 0x1c5
 521                                                         MX51_PAD_EIM_D26__UART3_TXD 0x1c5
 522                                                         MX51_PAD_EIM_D27__UART3_RTS 0x1c5
 523                                                         MX51_PAD_EIM_D24__UART3_CTS 0x1c5
 524                                                 >;
 525                                         };
 526
 527                                         pinctrl_uart3_2: uart3grp-2 {
 528                                                 fsl,pins = <
 529                                                         MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
 530                                                         MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
 531                                                 >;
 532                                         };
 533                                 };
 534
 535                                 kpp {
 536                                         pinctrl_kpp_1: kppgrp-1 {
 537                                                 fsl,pins = <
 538                                                         MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
 539                                                         MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
 540                                                         MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
 541                                                         MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
 542                                                         MX51_PAD_KEY_COL0__KEY_COL0 0xe8
 543                                                         MX51_PAD_KEY_COL1__KEY_COL1 0xe8
 544                                                         MX51_PAD_KEY_COL2__KEY_COL2 0xe8
 545                                                         MX51_PAD_KEY_COL3__KEY_COL3 0xe8
 546                                                 >;
 547                                         };
 548                                 };
 549                         };
 550
 551                         pwm1: pwm@73fb4000 {
 552                                 #pwm-cells = <2>;
 553                                 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
 554                                 reg = <0x73fb4000 0x4000>;
 555                                 clocks = <&clks 37>, <&clks 38>;
 556                                 clock-names = "ipg", "per";
 557                                 interrupts = <61>;
 558                         };
 559
 560                         pwm2: pwm@73fb8000 {
 561                                 #pwm-cells = <2>;
 562                                 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
 563                                 reg = <0x73fb8000 0x4000>;
 564                                 clocks = <&clks 39>, <&clks 40>;
 565                                 clock-names = "ipg", "per";
 566                                 interrupts = <94>;
 567                         };
 568
 569                         uart1: serial@73fbc000 {
 570                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 571                                 reg = <0x73fbc000 0x4000>;
 572                                 interrupts = <31>;
 573                                 clocks = <&clks 28>, <&clks 29>;
 574                                 clock-names = "ipg", "per";
 575                                 status = "disabled";
 576                         };
 577
 578                         uart2: serial@73fc0000 {
 579                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 580                                 reg = <0x73fc0000 0x4000>;
 581                                 interrupts = <32>;
 582                                 clocks = <&clks 30>, <&clks 31>;
 583                                 clock-names = "ipg", "per";
 584                                 status = "disabled";
 585                         };
 586
 587                         src: src@73fd0000 {
 588                                 compatible = "fsl,imx51-src";
 589                                 reg = <0x73fd0000 0x4000>;
 590                                 #reset-cells = <1>;
 591                         };
 592
 593                         clks: ccm@73fd4000{
 594                                 compatible = "fsl,imx51-ccm";
 595                                 reg = <0x73fd4000 0x4000>;
 596                                 interrupts = <0 71 0x04 0 72 0x04>;
 597                                 #clock-cells = <1>;
 598                         };
 599                 };
 600
 601                 aips@80000000 { /* AIPS2 */
 602                         compatible = "fsl,aips-bus", "simple-bus";
 603                         #address-cells = <1>;
 604                         #size-cells = <1>;
 605                         reg = <0x80000000 0x10000000>;
 606                         ranges;
 607
 608                         ecspi2: ecspi@83fac000 {
 609                                 #address-cells = <1>;
 610                                 #size-cells = <0>;
 611                                 compatible = "fsl,imx51-ecspi";
 612                                 reg = <0x83fac000 0x4000>;
 613                                 interrupts = <37>;
 614                                 clocks = <&clks 53>, <&clks 54>;
 615                                 clock-names = "ipg", "per";
 616                                 status = "disabled";
 617                         };
 618
 619                         sdma: sdma@83fb0000 {
 620                                 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
 621                                 reg = <0x83fb0000 0x4000>;
 622                                 interrupts = <6>;
 623                                 clocks = <&clks 56>, <&clks 56>;
 624                                 clock-names = "ipg", "ahb";
 625                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
 626                         };
 627
 628                         cspi: cspi@83fc0000 {
 629                                 #address-cells = <1>;
 630                                 #size-cells = <0>;
 631                                 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
 632                                 reg = <0x83fc0000 0x4000>;
 633                                 interrupts = <38>;
 634                                 clocks = <&clks 55>, <&clks 55>;
 635                                 clock-names = "ipg", "per";
 636                                 status = "disabled";
 637                         };
 638
 639                         i2c2: i2c@83fc4000 {
 640                                 #address-cells = <1>;
 641                                 #size-cells = <0>;
 642                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
 643                                 reg = <0x83fc4000 0x4000>;
 644                                 interrupts = <63>;
 645                                 clocks = <&clks 35>;
 646                                 status = "disabled";
 647                         };
 648
 649                         i2c1: i2c@83fc8000 {
 650                                 #address-cells = <1>;
 651                                 #size-cells = <0>;
 652                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
 653                                 reg = <0x83fc8000 0x4000>;
 654                                 interrupts = <62>;
 655                                 clocks = <&clks 34>;
 656                                 status = "disabled";
 657                         };
 658
 659                         ssi1: ssi@83fcc000 {
 660                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 661                                 reg = <0x83fcc000 0x4000>;
 662                                 interrupts = <29>;
 663                                 clocks = <&clks 48>;
 664                                 fsl,fifo-depth = <15>;
 665                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
 666                                 status = "disabled";
 667                         };
 668
 669                         audmux: audmux@83fd0000 {
 670                                 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
 671                                 reg = <0x83fd0000 0x4000>;
 672                                 status = "disabled";
 673                         };
 674
 675                         nfc: nand@83fdb000 {
 676                                 compatible = "fsl,imx51-nand";
 677                                 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
 678                                 interrupts = <8>;
 679                                 clocks = <&clks 60>;
 680                                 status = "disabled";
 681                         };
 682
 683                         pata: pata@83fe0000 {
 684                                 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
 685                                 reg = <0x83fe0000 0x4000>;
 686                                 interrupts = <70>;
 687                                 clocks = <&clks 161>;
 688                                 status = "disabled";
 689                         };
 690
 691                         ssi3: ssi@83fe8000 {
 692                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 693                                 reg = <0x83fe8000 0x4000>;
 694                                 interrupts = <96>;
 695                                 clocks = <&clks 50>;
 696                                 fsl,fifo-depth = <15>;
 697                                 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
 698                                 status = "disabled";
 699                         };
 700
 701                         fec: ethernet@83fec000 {
 702                                 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
 703                                 reg = <0x83fec000 0x4000>;
 704                                 interrupts = <87>;
 705                                 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
 706                                 clock-names = "ipg", "ahb", "ptp";
 707                                 status = "disabled";
 708                         };
 709                 };
 710         };
 711 };