arch/arm/boot/dts/imx51.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 serial0 = &uart1;
  18                 serial1 = &uart2;
  19                 serial2 = &uart3;
  20         };
  21
  22         tzic: tz-interrupt-controller@e0000000 {
  23                 compatible = "fsl,imx51-tzic", "fsl,tzic";
  24                 interrupt-controller;
  25                 #interrupt-cells = <1>;
  26                 reg = <0xe0000000 0x4000>;
  27         };
  28
  29         clocks {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 ckil {
  34                         compatible = "fsl,imx-ckil", "fixed-clock";
  35                         clock-frequency = <32768>;
  36                 };
  37
  38                 ckih1 {
  39                         compatible = "fsl,imx-ckih1", "fixed-clock";
  40                         clock-frequency = <22579200>;
  41                 };
  42
  43                 ckih2 {
  44                         compatible = "fsl,imx-ckih2", "fixed-clock";
  45                         clock-frequency = <0>;
  46                 };
  47
  48                 osc {
  49                         compatible = "fsl,imx-osc", "fixed-clock";
  50                         clock-frequency = <24000000>;
  51                 };
  52         };
  53
  54         soc {
  55                 #address-cells = <1>;
  56                 #size-cells = <1>;
  57                 compatible = "simple-bus";
  58                 interrupt-parent = <&tzic>;
  59                 ranges;
  60
  61                 aips@70000000 { /* AIPS1 */
  62                         compatible = "fsl,aips-bus", "simple-bus";
  63                         #address-cells = <1>;
  64                         #size-cells = <1>;
  65                         reg = <0x70000000 0x10000000>;
  66                         ranges;
  67
  68                         spba@70000000 {
  69                                 compatible = "fsl,spba-bus", "simple-bus";
  70                                 #address-cells = <1>;
  71                                 #size-cells = <1>;
  72                                 reg = <0x70000000 0x40000>;
  73                                 ranges;
  74
  75                                 esdhc@70004000 { /* ESDHC1 */
  76                                         compatible = "fsl,imx51-esdhc";
  77                                         reg = <0x70004000 0x4000>;
  78                                         interrupts = <1>;
  79                                         status = "disabled";
  80                                 };
  81
  82                                 esdhc@70008000 { /* ESDHC2 */
  83                                         compatible = "fsl,imx51-esdhc";
  84                                         reg = <0x70008000 0x4000>;
  85                                         interrupts = <2>;
  86                                         status = "disabled";
  87                                 };
  88
  89                                 uart3: serial@7000c000 {
  90                                         compatible = "fsl,imx51-uart", "fsl,imx21-uart";
  91                                         reg = <0x7000c000 0x4000>;
  92                                         interrupts = <33>;
  93                                         status = "disabled";
  94                                 };
  95
  96                                 ecspi@70010000 { /* ECSPI1 */
  97                                         #address-cells = <1>;
  98                                         #size-cells = <0>;
  99                                         compatible = "fsl,imx51-ecspi";
 100                                         reg = <0x70010000 0x4000>;
 101                                         interrupts = <36>;
 102                                         status = "disabled";
 103                                 };
 104
 105                                 ssi2: ssi@70014000 {
 106                                         compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 107                                         reg = <0x70014000 0x4000>;
 108                                         interrupts = <30>;
 109                                         fsl,fifo-depth = <15>;
 110                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 111                                         status = "disabled";
 112                                 };
 113
 114                                 esdhc@70020000 { /* ESDHC3 */
 115                                         compatible = "fsl,imx51-esdhc";
 116                                         reg = <0x70020000 0x4000>;
 117                                         interrupts = <3>;
 118                                         status = "disabled";
 119                                 };
 120
 121                                 esdhc@70024000 { /* ESDHC4 */
 122                                         compatible = "fsl,imx51-esdhc";
 123                                         reg = <0x70024000 0x4000>;
 124                                         interrupts = <4>;
 125                                         status = "disabled";
 126                                 };
 127                         };
 128
 129                         gpio1: gpio@73f84000 {
 130                                 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
 131                                 reg = <0x73f84000 0x4000>;
 132                                 interrupts = <50 51>;
 133                                 gpio-controller;
 134                                 #gpio-cells = <2>;
 135                                 interrupt-controller;
 136                                 #interrupt-cells = <1>;
 137                         };
 138
 139                         gpio2: gpio@73f88000 {
 140                                 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
 141                                 reg = <0x73f88000 0x4000>;
 142                                 interrupts = <52 53>;
 143                                 gpio-controller;
 144                                 #gpio-cells = <2>;
 145                                 interrupt-controller;
 146                                 #interrupt-cells = <1>;
 147                         };
 148
 149                         gpio3: gpio@73f8c000 {
 150                                 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
 151                                 reg = <0x73f8c000 0x4000>;
 152                                 interrupts = <54 55>;
 153                                 gpio-controller;
 154                                 #gpio-cells = <2>;
 155                                 interrupt-controller;
 156                                 #interrupt-cells = <1>;
 157                         };
 158
 159                         gpio4: gpio@73f90000 {
 160                                 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
 161                                 reg = <0x73f90000 0x4000>;
 162                                 interrupts = <56 57>;
 163                                 gpio-controller;
 164                                 #gpio-cells = <2>;
 165                                 interrupt-controller;
 166                                 #interrupt-cells = <1>;
 167                         };
 168
 169                         wdog@73f98000 { /* WDOG1 */
 170                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 171                                 reg = <0x73f98000 0x4000>;
 172                                 interrupts = <58>;
 173                                 status = "disabled";
 174                         };
 175
 176                         wdog@73f9c000 { /* WDOG2 */
 177                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 178                                 reg = <0x73f9c000 0x4000>;
 179                                 interrupts = <59>;
 180                                 status = "disabled";
 181                         };
 182
 183                         uart1: serial@73fbc000 {
 184                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 185                                 reg = <0x73fbc000 0x4000>;
 186                                 interrupts = <31>;
 187                                 status = "disabled";
 188                         };
 189
 190                         uart2: serial@73fc0000 {
 191                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 192                                 reg = <0x73fc0000 0x4000>;
 193                                 interrupts = <32>;
 194                                 status = "disabled";
 195                         };
 196                 };
 197
 198                 aips@80000000 { /* AIPS2 */
 199                         compatible = "fsl,aips-bus", "simple-bus";
 200                         #address-cells = <1>;
 201                         #size-cells = <1>;
 202                         reg = <0x80000000 0x10000000>;
 203                         ranges;
 204
 205                         ecspi@83fac000 { /* ECSPI2 */
 206                                 #address-cells = <1>;
 207                                 #size-cells = <0>;
 208                                 compatible = "fsl,imx51-ecspi";
 209                                 reg = <0x83fac000 0x4000>;
 210                                 interrupts = <37>;
 211                                 status = "disabled";
 212                         };
 213
 214                         sdma@83fb0000 {
 215                                 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
 216                                 reg = <0x83fb0000 0x4000>;
 217                                 interrupts = <6>;
 218                         };
 219
 220                         cspi@83fc0000 {
 221                                 #address-cells = <1>;
 222                                 #size-cells = <0>;
 223                                 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
 224                                 reg = <0x83fc0000 0x4000>;
 225                                 interrupts = <38>;
 226                                 status = "disabled";
 227                         };
 228
 229                         i2c@83fc4000 { /* I2C2 */
 230                                 #address-cells = <1>;
 231                                 #size-cells = <0>;
 232                                 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
 233                                 reg = <0x83fc4000 0x4000>;
 234                                 interrupts = <63>;
 235                                 status = "disabled";
 236                         };
 237
 238                         i2c@83fc8000 { /* I2C1 */
 239                                 #address-cells = <1>;
 240                                 #size-cells = <0>;
 241                                 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
 242                                 reg = <0x83fc8000 0x4000>;
 243                                 interrupts = <62>;
 244                                 status = "disabled";
 245                         };
 246
 247                         ssi1: ssi@83fcc000 {
 248                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 249                                 reg = <0x83fcc000 0x4000>;
 250                                 interrupts = <29>;
 251                                 fsl,fifo-depth = <15>;
 252                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
 253                                 status = "disabled";
 254                         };
 255
 256                         audmux@83fd0000 {
 257                                 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
 258                                 reg = <0x83fd0000 0x4000>;
 259                                 status = "disabled";
 260                         };
 261
 262                         ssi3: ssi@83fe8000 {
 263                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 264                                 reg = <0x83fe8000 0x4000>;
 265                                 interrupts = <96>;
 266                                 fsl,fifo-depth = <15>;
 267                                 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
 268                                 status = "disabled";
 269                         };
 270
 271                         ethernet@83fec000 {
 272                                 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
 273                                 reg = <0x83fec000 0x4000>;
 274                                 interrupts = <87>;
 275                                 status = "disabled";
 276                         };
 277                 };
 278         };
 279 };