arch/arm/boot/dts/imx51.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14 #include "imx51-pinfunc.h"
  15
  16 / {
  17         aliases {
  18                 serial0 = &uart1;
  19                 serial1 = &uart2;
  20                 serial2 = &uart3;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25         };
  26
  27         tzic: tz-interrupt-controller@e0000000 {
  28                 compatible = "fsl,imx51-tzic", "fsl,tzic";
  29                 interrupt-controller;
  30                 #interrupt-cells = <1>;
  31                 reg = <0xe0000000 0x4000>;
  32         };
  33
  34         clocks {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 ckil {
  39                         compatible = "fsl,imx-ckil", "fixed-clock";
  40                         clock-frequency = <32768>;
  41                 };
  42
  43                 ckih1 {
  44                         compatible = "fsl,imx-ckih1", "fixed-clock";
  45                         clock-frequency = <22579200>;
  46                 };
  47
  48                 ckih2 {
  49                         compatible = "fsl,imx-ckih2", "fixed-clock";
  50                         clock-frequency = <0>;
  51                 };
  52
  53                 osc {
  54                         compatible = "fsl,imx-osc", "fixed-clock";
  55                         clock-frequency = <24000000>;
  56                 };
  57         };
  58
  59         cpus {
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62                 cpu@0 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a8";
  65                         reg = <0>;
  66                         clock-latency = <61036>; /* two CLK32 periods */
  67                         clocks = <&clks 24>;
  68                         clock-names = "cpu";
  69                         operating-points = <
  70                                 /* kHz  uV (No regulator support) */
  71                                 160000  0
  72                                 800000  0
  73                         >;
  74                 };
  75         };
  76
  77         soc {
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80                 compatible = "simple-bus";
  81                 interrupt-parent = <&tzic>;
  82                 ranges;
  83
  84                 ipu: ipu@40000000 {
  85                         #crtc-cells = <1>;
  86                         compatible = "fsl,imx51-ipu";
  87                         reg = <0x40000000 0x20000000>;
  88                         interrupts = <11 10>;
  89                         clocks = <&clks 59>, <&clks 110>, <&clks 61>;
  90                         clock-names = "bus", "di0", "di1";
  91                         resets = <&src 2>;
  92                 };
  93
  94                 aips@70000000 { /* AIPS1 */
  95                         compatible = "fsl,aips-bus", "simple-bus";
  96                         #address-cells = <1>;
  97                         #size-cells = <1>;
  98                         reg = <0x70000000 0x10000000>;
  99                         ranges;
 100
 101                         spba@70000000 {
 102                                 compatible = "fsl,spba-bus", "simple-bus";
 103                                 #address-cells = <1>;
 104                                 #size-cells = <1>;
 105                                 reg = <0x70000000 0x40000>;
 106                                 ranges;
 107
 108                                 esdhc1: esdhc@70004000 {
 109                                         compatible = "fsl,imx51-esdhc";
 110                                         reg = <0x70004000 0x4000>;
 111                                         interrupts = <1>;
 112                                         clocks = <&clks 44>, <&clks 0>, <&clks 71>;
 113                                         clock-names = "ipg", "ahb", "per";
 114                                         status = "disabled";
 115                                 };
 116
 117                                 esdhc2: esdhc@70008000 {
 118                                         compatible = "fsl,imx51-esdhc";
 119                                         reg = <0x70008000 0x4000>;
 120                                         interrupts = <2>;
 121                                         clocks = <&clks 45>, <&clks 0>, <&clks 72>;
 122                                         clock-names = "ipg", "ahb", "per";
 123                                         bus-width = <4>;
 124                                         status = "disabled";
 125                                 };
 126
 127                                 uart3: serial@7000c000 {
 128                                         compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 129                                         reg = <0x7000c000 0x4000>;
 130                                         interrupts = <33>;
 131                                         clocks = <&clks 32>, <&clks 33>;
 132                                         clock-names = "ipg", "per";
 133                                         status = "disabled";
 134                                 };
 135
 136                                 ecspi1: ecspi@70010000 {
 137                                         #address-cells = <1>;
 138                                         #size-cells = <0>;
 139                                         compatible = "fsl,imx51-ecspi";
 140                                         reg = <0x70010000 0x4000>;
 141                                         interrupts = <36>;
 142                                         clocks = <&clks 51>, <&clks 52>;
 143                                         clock-names = "ipg", "per";
 144                                         status = "disabled";
 145                                 };
 146
 147                                 ssi2: ssi@70014000 {
 148                                         compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 149                                         reg = <0x70014000 0x4000>;
 150                                         interrupts = <30>;
 151                                         clocks = <&clks 49>;
 152                                         fsl,fifo-depth = <15>;
 153                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 154                                         status = "disabled";
 155                                 };
 156
 157                                 esdhc3: esdhc@70020000 {
 158                                         compatible = "fsl,imx51-esdhc";
 159                                         reg = <0x70020000 0x4000>;
 160                                         interrupts = <3>;
 161                                         clocks = <&clks 46>, <&clks 0>, <&clks 73>;
 162                                         clock-names = "ipg", "ahb", "per";
 163                                         bus-width = <4>;
 164                                         status = "disabled";
 165                                 };
 166
 167                                 esdhc4: esdhc@70024000 {
 168                                         compatible = "fsl,imx51-esdhc";
 169                                         reg = <0x70024000 0x4000>;
 170                                         interrupts = <4>;
 171                                         clocks = <&clks 47>, <&clks 0>, <&clks 74>;
 172                                         clock-names = "ipg", "ahb", "per";
 173                                         bus-width = <4>;
 174                                         status = "disabled";
 175                                 };
 176                         };
 177
 178                         usbphy0: usbphy@0 {
 179                                 compatible = "usb-nop-xceiv";
 180                                 clocks = <&clks 124>;
 181                                 clock-names = "main_clk";
 182                                 status = "okay";
 183                         };
 184
 185                         usbotg: usb@73f80000 {
 186                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 187                                 reg = <0x73f80000 0x0200>;
 188                                 interrupts = <18>;
 189                                 clocks = <&clks 108>;
 190                                 fsl,usbmisc = <&usbmisc 0>;
 191                                 fsl,usbphy = <&usbphy0>;
 192                                 status = "disabled";
 193                         };
 194
 195                         usbh1: usb@73f80200 {
 196                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 197                                 reg = <0x73f80200 0x0200>;
 198                                 interrupts = <14>;
 199                                 clocks = <&clks 108>;
 200                                 fsl,usbmisc = <&usbmisc 1>;
 201                                 status = "disabled";
 202                         };
 203
 204                         usbh2: usb@73f80400 {
 205                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 206                                 reg = <0x73f80400 0x0200>;
 207                                 interrupts = <16>;
 208                                 clocks = <&clks 108>;
 209                                 fsl,usbmisc = <&usbmisc 2>;
 210                                 status = "disabled";
 211                         };
 212
 213                         usbh3: usb@73f80600 {
 214                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 215                                 reg = <0x73f80600 0x0200>;
 216                                 interrupts = <17>;
 217                                 clocks = <&clks 108>;
 218                                 fsl,usbmisc = <&usbmisc 3>;
 219                                 status = "disabled";
 220                         };
 221
 222                         usbmisc: usbmisc@73f80800 {
 223                                 #index-cells = <1>;
 224                                 compatible = "fsl,imx51-usbmisc";
 225                                 reg = <0x73f80800 0x200>;
 226                                 clocks = <&clks 108>;
 227                         };
 228
 229                         gpio1: gpio@73f84000 {
 230                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 231                                 reg = <0x73f84000 0x4000>;
 232                                 interrupts = <50 51>;
 233                                 gpio-controller;
 234                                 #gpio-cells = <2>;
 235                                 interrupt-controller;
 236                                 #interrupt-cells = <2>;
 237                         };
 238
 239                         gpio2: gpio@73f88000 {
 240                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 241                                 reg = <0x73f88000 0x4000>;
 242                                 interrupts = <52 53>;
 243                                 gpio-controller;
 244                                 #gpio-cells = <2>;
 245                                 interrupt-controller;
 246                                 #interrupt-cells = <2>;
 247                         };
 248
 249                         gpio3: gpio@73f8c000 {
 250                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 251                                 reg = <0x73f8c000 0x4000>;
 252                                 interrupts = <54 55>;
 253                                 gpio-controller;
 254                                 #gpio-cells = <2>;
 255                                 interrupt-controller;
 256                                 #interrupt-cells = <2>;
 257                         };
 258
 259                         gpio4: gpio@73f90000 {
 260                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 261                                 reg = <0x73f90000 0x4000>;
 262                                 interrupts = <56 57>;
 263                                 gpio-controller;
 264                                 #gpio-cells = <2>;
 265                                 interrupt-controller;
 266                                 #interrupt-cells = <2>;
 267                         };
 268
 269                         kpp: kpp@73f94000 {
 270                                 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
 271                                 reg = <0x73f94000 0x4000>;
 272                                 interrupts = <60>;
 273                                 clocks = <&clks 0>;
 274                                 status = "disabled";
 275                         };
 276
 277                         wdog1: wdog@73f98000 {
 278                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 279                                 reg = <0x73f98000 0x4000>;
 280                                 interrupts = <58>;
 281                                 clocks = <&clks 0>;
 282                         };
 283
 284                         wdog2: wdog@73f9c000 {
 285                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 286                                 reg = <0x73f9c000 0x4000>;
 287                                 interrupts = <59>;
 288                                 clocks = <&clks 0>;
 289                                 status = "disabled";
 290                         };
 291
 292                         gpt: timer@73fa0000 {
 293                                 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
 294                                 reg = <0x73fa0000 0x4000>;
 295                                 interrupts = <39>;
 296                                 clocks = <&clks 36>, <&clks 41>;
 297                                 clock-names = "ipg", "per";
 298                         };
 299
 300                         iomuxc: iomuxc@73fa8000 {
 301                                 compatible = "fsl,imx51-iomuxc";
 302                                 reg = <0x73fa8000 0x4000>;
 303
 304                                 audmux {
 305                                         pinctrl_audmux_1: audmuxgrp-1 {
 306                                                 fsl,pins = <
 307                                                         MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
 308                                                         MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
 309                                                         MX51_PAD_AUD3_BB_CK__AUD3_TXC  0x80000000
 310                                                         MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
 311                                                 >;
 312                                         };
 313                                 };
 314
 315                                 fec {
 316                                         pinctrl_fec_1: fecgrp-1 {
 317                                                 fsl,pins = <
 318                                                         MX51_PAD_EIM_EB2__FEC_MDIO         0x80000000
 319                                                         MX51_PAD_EIM_EB3__FEC_RDATA1       0x80000000
 320                                                         MX51_PAD_EIM_CS2__FEC_RDATA2       0x80000000
 321                                                         MX51_PAD_EIM_CS3__FEC_RDATA3       0x80000000
 322                                                         MX51_PAD_EIM_CS4__FEC_RX_ER        0x80000000
 323                                                         MX51_PAD_EIM_CS5__FEC_CRS          0x80000000
 324                                                         MX51_PAD_NANDF_RB2__FEC_COL        0x80000000
 325                                                         MX51_PAD_NANDF_RB3__FEC_RX_CLK     0x80000000
 326                                                         MX51_PAD_NANDF_D9__FEC_RDATA0      0x80000000
 327                                                         MX51_PAD_NANDF_D8__FEC_TDATA0      0x80000000
 328                                                         MX51_PAD_NANDF_CS2__FEC_TX_ER      0x80000000
 329                                                         MX51_PAD_NANDF_CS3__FEC_MDC        0x80000000
 330                                                         MX51_PAD_NANDF_CS4__FEC_TDATA1     0x80000000
 331                                                         MX51_PAD_NANDF_CS5__FEC_TDATA2     0x80000000
 332                                                         MX51_PAD_NANDF_CS6__FEC_TDATA3     0x80000000
 333                                                         MX51_PAD_NANDF_CS7__FEC_TX_EN      0x80000000
 334                                                         MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
 335                                                 >;
 336                                         };
 337
 338                                         pinctrl_fec_2: fecgrp-2 {
 339                                                 fsl,pins = <
 340                                                         MX51_PAD_DI_GP3__FEC_TX_ER        0x80000000
 341                                                         MX51_PAD_DI2_PIN4__FEC_CRS        0x80000000
 342                                                         MX51_PAD_DI2_PIN2__FEC_MDC        0x80000000
 343                                                         MX51_PAD_DI2_PIN3__FEC_MDIO       0x80000000
 344                                                         MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
 345                                                         MX51_PAD_DI_GP4__FEC_RDATA2       0x80000000
 346                                                         MX51_PAD_DISP2_DAT0__FEC_RDATA3   0x80000000
 347                                                         MX51_PAD_DISP2_DAT1__FEC_RX_ER    0x80000000
 348                                                         MX51_PAD_DISP2_DAT6__FEC_TDATA1   0x80000000
 349                                                         MX51_PAD_DISP2_DAT7__FEC_TDATA2   0x80000000
 350                                                         MX51_PAD_DISP2_DAT8__FEC_TDATA3   0x80000000
 351                                                         MX51_PAD_DISP2_DAT9__FEC_TX_EN    0x80000000
 352                                                         MX51_PAD_DISP2_DAT10__FEC_COL     0x80000000
 353                                                         MX51_PAD_DISP2_DAT11__FEC_RX_CLK  0x80000000
 354                                                         MX51_PAD_DISP2_DAT12__FEC_RX_DV   0x80000000
 355                                                         MX51_PAD_DISP2_DAT13__FEC_TX_CLK  0x80000000
 356                                                         MX51_PAD_DISP2_DAT14__FEC_RDATA0  0x80000000
 357                                                         MX51_PAD_DISP2_DAT15__FEC_TDATA0  0x80000000
 358                                                 >;
 359                                         };
 360                                 };
 361
 362                                 ecspi1 {
 363                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 364                                                 fsl,pins = <
 365                                                         MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
 366                                                         MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
 367                                                         MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
 368                                                 >;
 369                                         };
 370                                 };
 371
 372                                 ecspi2 {
 373                                         pinctrl_ecspi2_1: ecspi2grp-1 {
 374                                                 fsl,pins = <
 375                                                         MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
 376                                                         MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
 377                                                         MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
 378                                                 >;
 379                                         };
 380                                 };
 381
 382                                 esdhc1 {
 383                                         pinctrl_esdhc1_1: esdhc1grp-1 {
 384                                                 fsl,pins = <
 385                                                         MX51_PAD_SD1_CMD__SD1_CMD     0x400020d5
 386                                                         MX51_PAD_SD1_CLK__SD1_CLK     0x20d5
 387                                                         MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
 388                                                         MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
 389                                                         MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
 390                                                         MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
 391                                                 >;
 392                                         };
 393                                 };
 394
 395                                 esdhc2 {
 396                                         pinctrl_esdhc2_1: esdhc2grp-1 {
 397                                                 fsl,pins = <
 398                                                         MX51_PAD_SD2_CMD__SD2_CMD     0x400020d5
 399                                                         MX51_PAD_SD2_CLK__SD2_CLK     0x20d5
 400                                                         MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
 401                                                         MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
 402                                                         MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
 403                                                         MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
 404                                                 >;
 405                                         };
 406                                 };
 407
 408                                 i2c2 {
 409                                         pinctrl_i2c2_1: i2c2grp-1 {
 410                                                 fsl,pins = <
 411                                                         MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
 412                                                         MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
 413                                                 >;
 414                                         };
 415
 416                                         pinctrl_i2c2_2: i2c2grp-2 {
 417                                                 fsl,pins = <
 418                                                         MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
 419                                                         MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
 420                                                 >;
 421                                         };
 422                                 };
 423
 424                                 ipu_disp1 {
 425                                         pinctrl_ipu_disp1_1: ipudisp1grp-1 {
 426                                                 fsl,pins = <
 427                                                         MX51_PAD_DISP1_DAT0__DISP1_DAT0   0x5
 428                                                         MX51_PAD_DISP1_DAT1__DISP1_DAT1   0x5
 429                                                         MX51_PAD_DISP1_DAT2__DISP1_DAT2   0x5
 430                                                         MX51_PAD_DISP1_DAT3__DISP1_DAT3   0x5
 431                                                         MX51_PAD_DISP1_DAT4__DISP1_DAT4   0x5
 432                                                         MX51_PAD_DISP1_DAT5__DISP1_DAT5   0x5
 433                                                         MX51_PAD_DISP1_DAT6__DISP1_DAT6   0x5
 434                                                         MX51_PAD_DISP1_DAT7__DISP1_DAT7   0x5
 435                                                         MX51_PAD_DISP1_DAT8__DISP1_DAT8   0x5
 436                                                         MX51_PAD_DISP1_DAT9__DISP1_DAT9   0x5
 437                                                         MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
 438                                                         MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
 439                                                         MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
 440                                                         MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
 441                                                         MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
 442                                                         MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
 443                                                         MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
 444                                                         MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
 445                                                         MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
 446                                                         MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
 447                                                         MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
 448                                                         MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
 449                                                         MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
 450                                                         MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
 451                                                         MX51_PAD_DI1_PIN2__DI1_PIN2       0x5 /* hsync */
 452                                                         MX51_PAD_DI1_PIN3__DI1_PIN3       0x5 /* vsync */
 453                                                 >;
 454                                         };
 455                                 };
 456
 457                                 ipu_disp2 {
 458                                         pinctrl_ipu_disp2_1: ipudisp2grp-1 {
 459                                                 fsl,pins = <
 460                                                         MX51_PAD_DISP2_DAT0__DISP2_DAT0     0x5
 461                                                         MX51_PAD_DISP2_DAT1__DISP2_DAT1     0x5
 462                                                         MX51_PAD_DISP2_DAT2__DISP2_DAT2     0x5
 463                                                         MX51_PAD_DISP2_DAT3__DISP2_DAT3     0x5
 464                                                         MX51_PAD_DISP2_DAT4__DISP2_DAT4     0x5
 465                                                         MX51_PAD_DISP2_DAT5__DISP2_DAT5     0x5
 466                                                         MX51_PAD_DISP2_DAT6__DISP2_DAT6     0x5
 467                                                         MX51_PAD_DISP2_DAT7__DISP2_DAT7     0x5
 468                                                         MX51_PAD_DISP2_DAT8__DISP2_DAT8     0x5
 469                                                         MX51_PAD_DISP2_DAT9__DISP2_DAT9     0x5
 470                                                         MX51_PAD_DISP2_DAT10__DISP2_DAT10   0x5
 471                                                         MX51_PAD_DISP2_DAT11__DISP2_DAT11   0x5
 472                                                         MX51_PAD_DISP2_DAT12__DISP2_DAT12   0x5
 473                                                         MX51_PAD_DISP2_DAT13__DISP2_DAT13   0x5
 474                                                         MX51_PAD_DISP2_DAT14__DISP2_DAT14   0x5
 475                                                         MX51_PAD_DISP2_DAT15__DISP2_DAT15   0x5
 476                                                         MX51_PAD_DI2_PIN2__DI2_PIN2         0x5 /* hsync */
 477                                                         MX51_PAD_DI2_PIN3__DI2_PIN3         0x5 /* vsync */
 478                                                         MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
 479                                                         MX51_PAD_DI_GP4__DI2_PIN15          0x5
 480                                                 >;
 481                                         };
 482                                 };
 483
 484                                 pata {
 485                                         pinctrl_pata_1: patagrp-1 {
 486                                                 fsl,pins = <
 487                                                         MX51_PAD_NANDF_WE_B__PATA_DIOW          0x2004
 488                                                         MX51_PAD_NANDF_RE_B__PATA_DIOR          0x2004
 489                                                         MX51_PAD_NANDF_ALE__PATA_BUFFER_EN      0x2004
 490                                                         MX51_PAD_NANDF_CLE__PATA_RESET_B        0x2004
 491                                                         MX51_PAD_NANDF_WP_B__PATA_DMACK         0x2004
 492                                                         MX51_PAD_NANDF_RB0__PATA_DMARQ          0x2004
 493                                                         MX51_PAD_NANDF_RB1__PATA_IORDY          0x2004
 494                                                         MX51_PAD_GPIO_NAND__PATA_INTRQ          0x2004
 495                                                         MX51_PAD_NANDF_CS2__PATA_CS_0           0x2004
 496                                                         MX51_PAD_NANDF_CS3__PATA_CS_1           0x2004
 497                                                         MX51_PAD_NANDF_CS4__PATA_DA_0           0x2004
 498                                                         MX51_PAD_NANDF_CS5__PATA_DA_1           0x2004
 499                                                         MX51_PAD_NANDF_CS6__PATA_DA_2           0x2004
 500                                                         MX51_PAD_NANDF_D15__PATA_DATA15         0x2004
 501                                                         MX51_PAD_NANDF_D14__PATA_DATA14         0x2004
 502                                                         MX51_PAD_NANDF_D13__PATA_DATA13         0x2004
 503                                                         MX51_PAD_NANDF_D12__PATA_DATA12         0x2004
 504                                                         MX51_PAD_NANDF_D11__PATA_DATA11         0x2004
 505                                                         MX51_PAD_NANDF_D10__PATA_DATA10         0x2004
 506                                                         MX51_PAD_NANDF_D9__PATA_DATA9           0x2004
 507                                                         MX51_PAD_NANDF_D8__PATA_DATA8           0x2004
 508                                                         MX51_PAD_NANDF_D7__PATA_DATA7           0x2004
 509                                                         MX51_PAD_NANDF_D6__PATA_DATA6           0x2004
 510                                                         MX51_PAD_NANDF_D5__PATA_DATA5           0x2004
 511                                                         MX51_PAD_NANDF_D4__PATA_DATA4           0x2004
 512                                                         MX51_PAD_NANDF_D3__PATA_DATA3           0x2004
 513                                                         MX51_PAD_NANDF_D2__PATA_DATA2           0x2004
 514                                                         MX51_PAD_NANDF_D1__PATA_DATA1           0x2004
 515                                                         MX51_PAD_NANDF_D0__PATA_DATA0           0x2004
 516                                                 >;
 517                                         };
 518                                 };
 519
 520                                 uart1 {
 521                                         pinctrl_uart1_1: uart1grp-1 {
 522                                                 fsl,pins = <
 523                                                         MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
 524                                                         MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
 525                                                         MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
 526                                                         MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
 527                                                 >;
 528                                         };
 529                                 };
 530
 531                                 uart2 {
 532                                         pinctrl_uart2_1: uart2grp-1 {
 533                                                 fsl,pins = <
 534                                                         MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
 535                                                         MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
 536                                                 >;
 537                                         };
 538                                 };
 539
 540                                 uart3 {
 541                                         pinctrl_uart3_1: uart3grp-1 {
 542                                                 fsl,pins = <
 543                                                         MX51_PAD_EIM_D25__UART3_RXD 0x1c5
 544                                                         MX51_PAD_EIM_D26__UART3_TXD 0x1c5
 545                                                         MX51_PAD_EIM_D27__UART3_RTS 0x1c5
 546                                                         MX51_PAD_EIM_D24__UART3_CTS 0x1c5
 547                                                 >;
 548                                         };
 549
 550                                         pinctrl_uart3_2: uart3grp-2 {
 551                                                 fsl,pins = <
 552                                                         MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
 553                                                         MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
 554                                                 >;
 555                                         };
 556                                 };
 557
 558                                 kpp {
 559                                         pinctrl_kpp_1: kppgrp-1 {
 560                                                 fsl,pins = <
 561                                                         MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
 562                                                         MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
 563                                                         MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
 564                                                         MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
 565                                                         MX51_PAD_KEY_COL0__KEY_COL0 0xe8
 566                                                         MX51_PAD_KEY_COL1__KEY_COL1 0xe8
 567                                                         MX51_PAD_KEY_COL2__KEY_COL2 0xe8
 568                                                         MX51_PAD_KEY_COL3__KEY_COL3 0xe8
 569                                                 >;
 570                                         };
 571                                 };
 572                         };
 573
 574                         pwm1: pwm@73fb4000 {
 575                                 #pwm-cells = <2>;
 576                                 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
 577                                 reg = <0x73fb4000 0x4000>;
 578                                 clocks = <&clks 37>, <&clks 38>;
 579                                 clock-names = "ipg", "per";
 580                                 interrupts = <61>;
 581                         };
 582
 583                         pwm2: pwm@73fb8000 {
 584                                 #pwm-cells = <2>;
 585                                 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
 586                                 reg = <0x73fb8000 0x4000>;
 587                                 clocks = <&clks 39>, <&clks 40>;
 588                                 clock-names = "ipg", "per";
 589                                 interrupts = <94>;
 590                         };
 591
 592                         uart1: serial@73fbc000 {
 593                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 594                                 reg = <0x73fbc000 0x4000>;
 595                                 interrupts = <31>;
 596                                 clocks = <&clks 28>, <&clks 29>;
 597                                 clock-names = "ipg", "per";
 598                                 status = "disabled";
 599                         };
 600
 601                         uart2: serial@73fc0000 {
 602                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 603                                 reg = <0x73fc0000 0x4000>;
 604                                 interrupts = <32>;
 605                                 clocks = <&clks 30>, <&clks 31>;
 606                                 clock-names = "ipg", "per";
 607                                 status = "disabled";
 608                         };
 609
 610                         src: src@73fd0000 {
 611                                 compatible = "fsl,imx51-src";
 612                                 reg = <0x73fd0000 0x4000>;
 613                                 #reset-cells = <1>;
 614                         };
 615
 616                         clks: ccm@73fd4000{
 617                                 compatible = "fsl,imx51-ccm";
 618                                 reg = <0x73fd4000 0x4000>;
 619                                 interrupts = <0 71 0x04 0 72 0x04>;
 620                                 #clock-cells = <1>;
 621                         };
 622                 };
 623
 624                 aips@80000000 { /* AIPS2 */
 625                         compatible = "fsl,aips-bus", "simple-bus";
 626                         #address-cells = <1>;
 627                         #size-cells = <1>;
 628                         reg = <0x80000000 0x10000000>;
 629                         ranges;
 630
 631                         ecspi2: ecspi@83fac000 {
 632                                 #address-cells = <1>;
 633                                 #size-cells = <0>;
 634                                 compatible = "fsl,imx51-ecspi";
 635                                 reg = <0x83fac000 0x4000>;
 636                                 interrupts = <37>;
 637                                 clocks = <&clks 53>, <&clks 54>;
 638                                 clock-names = "ipg", "per";
 639                                 status = "disabled";
 640                         };
 641
 642                         sdma: sdma@83fb0000 {
 643                                 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
 644                                 reg = <0x83fb0000 0x4000>;
 645                                 interrupts = <6>;
 646                                 clocks = <&clks 56>, <&clks 56>;
 647                                 clock-names = "ipg", "ahb";
 648                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
 649                         };
 650
 651                         cspi: cspi@83fc0000 {
 652                                 #address-cells = <1>;
 653                                 #size-cells = <0>;
 654                                 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
 655                                 reg = <0x83fc0000 0x4000>;
 656                                 interrupts = <38>;
 657                                 clocks = <&clks 55>, <&clks 55>;
 658                                 clock-names = "ipg", "per";
 659                                 status = "disabled";
 660                         };
 661
 662                         i2c2: i2c@83fc4000 {
 663                                 #address-cells = <1>;
 664                                 #size-cells = <0>;
 665                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
 666                                 reg = <0x83fc4000 0x4000>;
 667                                 interrupts = <63>;
 668                                 clocks = <&clks 35>;
 669                                 status = "disabled";
 670                         };
 671
 672                         i2c1: i2c@83fc8000 {
 673                                 #address-cells = <1>;
 674                                 #size-cells = <0>;
 675                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
 676                                 reg = <0x83fc8000 0x4000>;
 677                                 interrupts = <62>;
 678                                 clocks = <&clks 34>;
 679                                 status = "disabled";
 680                         };
 681
 682                         ssi1: ssi@83fcc000 {
 683                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 684                                 reg = <0x83fcc000 0x4000>;
 685                                 interrupts = <29>;
 686                                 clocks = <&clks 48>;
 687                                 fsl,fifo-depth = <15>;
 688                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
 689                                 status = "disabled";
 690                         };
 691
 692                         audmux: audmux@83fd0000 {
 693                                 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
 694                                 reg = <0x83fd0000 0x4000>;
 695                                 status = "disabled";
 696                         };
 697
 698                         nfc: nand@83fdb000 {
 699                                 compatible = "fsl,imx51-nand";
 700                                 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
 701                                 interrupts = <8>;
 702                                 clocks = <&clks 60>;
 703                                 status = "disabled";
 704                         };
 705
 706                         pata: pata@83fe0000 {
 707                                 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
 708                                 reg = <0x83fe0000 0x4000>;
 709                                 interrupts = <70>;
 710                                 clocks = <&clks 161>;
 711                                 status = "disabled";
 712                         };
 713
 714                         ssi3: ssi@83fe8000 {
 715                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 716                                 reg = <0x83fe8000 0x4000>;
 717                                 interrupts = <96>;
 718                                 clocks = <&clks 50>;
 719                                 fsl,fifo-depth = <15>;
 720                                 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
 721                                 status = "disabled";
 722                         };
 723
 724                         fec: ethernet@83fec000 {
 725                                 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
 726                                 reg = <0x83fec000 0x4000>;
 727                                 interrupts = <87>;
 728                                 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
 729                                 clock-names = "ipg", "ahb", "ptp";
 730                                 status = "disabled";
 731                         };
 732                 };
 733         };
 734 };