2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
26 tzic: tz-interrupt-controller@e0000000 {
27 compatible = "fsl,imx51-tzic", "fsl,tzic";
29 #interrupt-cells = <1>;
30 reg = <0xe0000000 0x4000>;
38 compatible = "fsl,imx-ckil", "fixed-clock";
39 clock-frequency = <32768>;
43 compatible = "fsl,imx-ckih1", "fixed-clock";
44 clock-frequency = <22579200>;
48 compatible = "fsl,imx-ckih2", "fixed-clock";
49 clock-frequency = <0>;
53 compatible = "fsl,imx-osc", "fixed-clock";
54 clock-frequency = <24000000>;
61 compatible = "simple-bus";
62 interrupt-parent = <&tzic>;
67 compatible = "fsl,imx51-ipu";
68 reg = <0x40000000 0x20000000>;
72 aips@70000000 { /* AIPS1 */
73 compatible = "fsl,aips-bus", "simple-bus";
76 reg = <0x70000000 0x10000000>;
80 compatible = "fsl,spba-bus", "simple-bus";
83 reg = <0x70000000 0x40000>;
86 esdhc1: esdhc@70004000 {
87 compatible = "fsl,imx51-esdhc";
88 reg = <0x70004000 0x4000>;
90 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
91 clock-names = "ipg", "ahb", "per";
95 esdhc2: esdhc@70008000 {
96 compatible = "fsl,imx51-esdhc";
97 reg = <0x70008000 0x4000>;
99 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
100 clock-names = "ipg", "ahb", "per";
105 uart3: serial@7000c000 {
106 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
107 reg = <0x7000c000 0x4000>;
109 clocks = <&clks 32>, <&clks 33>;
110 clock-names = "ipg", "per";
114 ecspi1: ecspi@70010000 {
115 #address-cells = <1>;
117 compatible = "fsl,imx51-ecspi";
118 reg = <0x70010000 0x4000>;
120 clocks = <&clks 51>, <&clks 52>;
121 clock-names = "ipg", "per";
126 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
127 reg = <0x70014000 0x4000>;
130 fsl,fifo-depth = <15>;
131 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
135 esdhc3: esdhc@70020000 {
136 compatible = "fsl,imx51-esdhc";
137 reg = <0x70020000 0x4000>;
139 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
140 clock-names = "ipg", "ahb", "per";
145 esdhc4: esdhc@70024000 {
146 compatible = "fsl,imx51-esdhc";
147 reg = <0x70024000 0x4000>;
149 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
150 clock-names = "ipg", "ahb", "per";
156 usbotg: usb@73f80000 {
157 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
158 reg = <0x73f80000 0x0200>;
163 usbh1: usb@73f80200 {
164 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
165 reg = <0x73f80200 0x0200>;
170 usbh2: usb@73f80400 {
171 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
172 reg = <0x73f80400 0x0200>;
177 usbh3: usb@73f80600 {
178 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
179 reg = <0x73f80600 0x0200>;
184 gpio1: gpio@73f84000 {
185 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
186 reg = <0x73f84000 0x4000>;
187 interrupts = <50 51>;
190 interrupt-controller;
191 #interrupt-cells = <2>;
194 gpio2: gpio@73f88000 {
195 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
196 reg = <0x73f88000 0x4000>;
197 interrupts = <52 53>;
200 interrupt-controller;
201 #interrupt-cells = <2>;
204 gpio3: gpio@73f8c000 {
205 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
206 reg = <0x73f8c000 0x4000>;
207 interrupts = <54 55>;
210 interrupt-controller;
211 #interrupt-cells = <2>;
214 gpio4: gpio@73f90000 {
215 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
216 reg = <0x73f90000 0x4000>;
217 interrupts = <56 57>;
220 interrupt-controller;
221 #interrupt-cells = <2>;
224 wdog1: wdog@73f98000 {
225 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
226 reg = <0x73f98000 0x4000>;
231 wdog2: wdog@73f9c000 {
232 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
233 reg = <0x73f9c000 0x4000>;
239 iomuxc: iomuxc@73fa8000 {
240 compatible = "fsl,imx51-iomuxc";
241 reg = <0x73fa8000 0x4000>;
244 pinctrl_audmux_1: audmuxgrp-1 {
246 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
247 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
248 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
249 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
255 pinctrl_fec_1: fecgrp-1 {
257 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
258 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
259 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
260 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
261 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
262 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
263 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
264 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
265 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
266 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
267 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
268 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
269 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
270 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
271 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
272 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
273 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
279 pinctrl_ecspi1_1: ecspi1grp-1 {
281 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
282 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
283 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
289 pinctrl_esdhc1_1: esdhc1grp-1 {
291 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
292 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
293 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
294 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
295 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
296 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
302 pinctrl_esdhc2_1: esdhc2grp-1 {
304 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
305 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
306 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
307 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
308 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
309 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
315 pinctrl_i2c2_1: i2c2grp-1 {
317 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
318 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
324 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
326 528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
327 529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
328 530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
329 531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
330 532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
331 533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
332 535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
333 537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
334 539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
335 541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
336 543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
337 545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
338 547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
339 549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
340 551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
341 553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
342 555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
343 557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
344 559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
345 563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
346 567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
347 571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
348 575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
349 579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
350 584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */
351 583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */
357 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
359 603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
360 608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
361 613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
362 614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
363 615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
364 616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
365 617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
366 622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
367 627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
368 633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
369 637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
370 643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
371 648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
372 652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
373 656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
374 661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
375 593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */
376 595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */
377 597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
378 599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */
384 pinctrl_uart1_1: uart1grp-1 {
386 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
387 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
388 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
389 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
395 pinctrl_uart2_1: uart2grp-1 {
397 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
398 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
404 pinctrl_uart3_1: uart3grp-1 {
406 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
407 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
408 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
409 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
417 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
418 reg = <0x73fb4000 0x4000>;
419 clocks = <&clks 37>, <&clks 38>;
420 clock-names = "ipg", "per";
426 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
427 reg = <0x73fb8000 0x4000>;
428 clocks = <&clks 39>, <&clks 40>;
429 clock-names = "ipg", "per";
433 uart1: serial@73fbc000 {
434 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
435 reg = <0x73fbc000 0x4000>;
437 clocks = <&clks 28>, <&clks 29>;
438 clock-names = "ipg", "per";
442 uart2: serial@73fc0000 {
443 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
444 reg = <0x73fc0000 0x4000>;
446 clocks = <&clks 30>, <&clks 31>;
447 clock-names = "ipg", "per";
452 compatible = "fsl,imx51-ccm";
453 reg = <0x73fd4000 0x4000>;
454 interrupts = <0 71 0x04 0 72 0x04>;
459 aips@80000000 { /* AIPS2 */
460 compatible = "fsl,aips-bus", "simple-bus";
461 #address-cells = <1>;
463 reg = <0x80000000 0x10000000>;
466 ecspi2: ecspi@83fac000 {
467 #address-cells = <1>;
469 compatible = "fsl,imx51-ecspi";
470 reg = <0x83fac000 0x4000>;
472 clocks = <&clks 53>, <&clks 54>;
473 clock-names = "ipg", "per";
477 sdma: sdma@83fb0000 {
478 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
479 reg = <0x83fb0000 0x4000>;
481 clocks = <&clks 56>, <&clks 56>;
482 clock-names = "ipg", "ahb";
483 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
486 cspi: cspi@83fc0000 {
487 #address-cells = <1>;
489 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
490 reg = <0x83fc0000 0x4000>;
492 clocks = <&clks 55>, <&clks 0>;
493 clock-names = "ipg", "per";
498 #address-cells = <1>;
500 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
501 reg = <0x83fc4000 0x4000>;
508 #address-cells = <1>;
510 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
511 reg = <0x83fc8000 0x4000>;
518 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
519 reg = <0x83fcc000 0x4000>;
522 fsl,fifo-depth = <15>;
523 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
527 audmux: audmux@83fd0000 {
528 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
529 reg = <0x83fd0000 0x4000>;
534 compatible = "fsl,imx51-nand";
535 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
542 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
543 reg = <0x83fe8000 0x4000>;
546 fsl,fifo-depth = <15>;
547 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
551 fec: ethernet@83fec000 {
552 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
553 reg = <0x83fec000 0x4000>;
555 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
556 clock-names = "ipg", "ahb", "ptp";