2 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include "skeleton.dtsi"
15 #include "imx50-pinfunc.h"
16 #include <dt-bindings/clock/imx5-clock.h>
38 compatible = "arm,cortex-a8";
43 tzic: tz-interrupt-controller@0fffc000 {
44 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
46 #interrupt-cells = <1>;
47 reg = <0x0fffc000 0x4000>;
55 compatible = "fsl,imx-ckil", "fixed-clock";
57 clock-frequency = <32768>;
61 compatible = "fsl,imx-ckih1", "fixed-clock";
63 clock-frequency = <22579200>;
67 compatible = "fsl,imx-ckih2", "fixed-clock";
69 clock-frequency = <0>;
73 compatible = "fsl,imx-osc", "fixed-clock";
75 clock-frequency = <24000000>;
82 compatible = "simple-bus";
83 interrupt-parent = <&tzic>;
86 aips@50000000 { /* AIPS1 */
87 compatible = "fsl,aips-bus", "simple-bus";
90 reg = <0x50000000 0x10000000>;
94 compatible = "fsl,spba-bus", "simple-bus";
97 reg = <0x50000000 0x40000>;
100 esdhc1: esdhc@50004000 {
101 compatible = "fsl,imx50-esdhc";
102 reg = <0x50004000 0x4000>;
104 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
105 <&clks IMX5_CLK_DUMMY>,
106 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
107 clock-names = "ipg", "ahb", "per";
112 esdhc2: esdhc@50008000 {
113 compatible = "fsl,imx50-esdhc";
114 reg = <0x50008000 0x4000>;
116 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
117 <&clks IMX5_CLK_DUMMY>,
118 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
119 clock-names = "ipg", "ahb", "per";
124 uart3: serial@5000c000 {
125 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
126 reg = <0x5000c000 0x4000>;
128 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
129 <&clks IMX5_CLK_UART3_PER_GATE>;
130 clock-names = "ipg", "per";
134 ecspi1: ecspi@50010000 {
135 #address-cells = <1>;
137 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
138 reg = <0x50010000 0x4000>;
140 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
141 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
142 clock-names = "ipg", "per";
147 compatible = "fsl,imx50-ssi",
150 reg = <0x50014000 0x4000>;
152 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
153 fsl,fifo-depth = <15>;
154 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
158 esdhc3: esdhc@50020000 {
159 compatible = "fsl,imx50-esdhc";
160 reg = <0x50020000 0x4000>;
162 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
163 <&clks IMX5_CLK_DUMMY>,
164 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
165 clock-names = "ipg", "ahb", "per";
170 esdhc4: esdhc@50024000 {
171 compatible = "fsl,imx50-esdhc";
172 reg = <0x50024000 0x4000>;
174 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
175 <&clks IMX5_CLK_DUMMY>,
176 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
177 clock-names = "ipg", "ahb", "per";
183 usbotg: usb@53f80000 {
184 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
185 reg = <0x53f80000 0x0200>;
187 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
191 usbh1: usb@53f80200 {
192 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
193 reg = <0x53f80200 0x0200>;
195 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
199 usbh2: usb@53f80400 {
200 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
201 reg = <0x53f80400 0x0200>;
203 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
207 usbh3: usb@53f80600 {
208 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
209 reg = <0x53f80600 0x0200>;
211 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
215 gpio1: gpio@53f84000 {
216 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
217 reg = <0x53f84000 0x4000>;
218 interrupts = <50 51>;
221 interrupt-controller;
222 #interrupt-cells = <2>;
225 gpio2: gpio@53f88000 {
226 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
227 reg = <0x53f88000 0x4000>;
228 interrupts = <52 53>;
231 interrupt-controller;
232 #interrupt-cells = <2>;
235 gpio3: gpio@53f8c000 {
236 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
237 reg = <0x53f8c000 0x4000>;
238 interrupts = <54 55>;
241 interrupt-controller;
242 #interrupt-cells = <2>;
245 gpio4: gpio@53f90000 {
246 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
247 reg = <0x53f90000 0x4000>;
248 interrupts = <56 57>;
251 interrupt-controller;
252 #interrupt-cells = <2>;
255 wdog1: wdog@53f98000 {
256 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
257 reg = <0x53f98000 0x4000>;
259 clocks = <&clks IMX5_CLK_DUMMY>;
262 gpt: timer@53fa0000 {
263 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
264 reg = <0x53fa0000 0x4000>;
266 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
267 <&clks IMX5_CLK_GPT_HF_GATE>;
268 clock-names = "ipg", "per";
271 iomuxc: iomuxc@53fa8000 {
272 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
273 reg = <0x53fa8000 0x4000>;
276 gpr: iomuxc-gpr@53fa8000 {
277 compatible = "fsl,imx50-iomuxc-gpr", "syscon";
278 reg = <0x53fa8000 0xc>;
283 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
284 reg = <0x53fb4000 0x4000>;
285 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
286 <&clks IMX5_CLK_PWM1_HF_GATE>;
287 clock-names = "ipg", "per";
293 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
294 reg = <0x53fb8000 0x4000>;
295 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
296 <&clks IMX5_CLK_PWM2_HF_GATE>;
297 clock-names = "ipg", "per";
301 uart1: serial@53fbc000 {
302 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
303 reg = <0x53fbc000 0x4000>;
305 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
306 <&clks IMX5_CLK_UART1_PER_GATE>;
307 clock-names = "ipg", "per";
311 uart2: serial@53fc0000 {
312 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
313 reg = <0x53fc0000 0x4000>;
315 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
316 <&clks IMX5_CLK_UART2_PER_GATE>;
317 clock-names = "ipg", "per";
322 compatible = "fsl,imx50-src", "fsl,imx51-src";
323 reg = <0x53fd0000 0x4000>;
328 compatible = "fsl,imx50-ccm";
329 reg = <0x53fd4000 0x4000>;
330 interrupts = <0 71 0x04 0 72 0x04>;
334 gpio5: gpio@53fdc000 {
335 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
336 reg = <0x53fdc000 0x4000>;
337 interrupts = <103 104>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
344 gpio6: gpio@53fe0000 {
345 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
346 reg = <0x53fe0000 0x4000>;
347 interrupts = <105 106>;
350 interrupt-controller;
351 #interrupt-cells = <2>;
355 #address-cells = <1>;
357 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
358 reg = <0x53fec000 0x4000>;
360 clocks = <&clks IMX5_CLK_I2C3_GATE>;
364 uart4: serial@53ff0000 {
365 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
366 reg = <0x53ff0000 0x4000>;
368 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
369 <&clks IMX5_CLK_UART4_PER_GATE>;
370 clock-names = "ipg", "per";
375 aips@60000000 { /* AIPS2 */
376 compatible = "fsl,aips-bus", "simple-bus";
377 #address-cells = <1>;
379 reg = <0x60000000 0x10000000>;
382 uart5: serial@63f90000 {
383 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
384 reg = <0x63f90000 0x4000>;
386 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
387 <&clks IMX5_CLK_UART5_PER_GATE>;
388 clock-names = "ipg", "per";
392 owire: owire@63fa4000 {
393 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
394 reg = <0x63fa4000 0x4000>;
395 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
399 ecspi2: ecspi@63fac000 {
400 #address-cells = <1>;
402 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
403 reg = <0x63fac000 0x4000>;
405 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
406 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
407 clock-names = "ipg", "per";
411 sdma: sdma@63fb0000 {
412 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
413 reg = <0x63fb0000 0x4000>;
415 clocks = <&clks IMX5_CLK_SDMA_GATE>,
416 <&clks IMX5_CLK_SDMA_GATE>;
417 clock-names = "ipg", "ahb";
418 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
421 cspi: cspi@63fc0000 {
422 #address-cells = <1>;
424 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
425 reg = <0x63fc0000 0x4000>;
427 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
428 <&clks IMX5_CLK_CSPI_IPG_GATE>;
429 clock-names = "ipg", "per";
434 #address-cells = <1>;
436 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
437 reg = <0x63fc4000 0x4000>;
439 clocks = <&clks IMX5_CLK_I2C2_GATE>;
444 #address-cells = <1>;
446 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
447 reg = <0x63fc8000 0x4000>;
449 clocks = <&clks IMX5_CLK_I2C1_GATE>;
454 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
456 reg = <0x63fcc000 0x4000>;
458 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
459 fsl,fifo-depth = <15>;
460 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
464 audmux: audmux@63fd0000 {
465 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
466 reg = <0x63fd0000 0x4000>;
470 fec: ethernet@63fec000 {
471 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
472 reg = <0x63fec000 0x4000>;
474 clocks = <&clks IMX5_CLK_FEC_GATE>,
475 <&clks IMX5_CLK_FEC_GATE>,
476 <&clks IMX5_CLK_FEC_GATE>;
477 clock-names = "ipg", "ahb", "ptp";