2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 /include/ "skeleton.dtsi"
15 interrupt-parent = <&icoll>;
39 compatible = "arm,arm926ej-s";
45 compatible = "simple-bus";
48 reg = <0x80000000 0x80000>;
52 compatible = "simple-bus";
55 reg = <0x80000000 0x3c900>;
58 icoll: interrupt-controller@80000000 {
59 compatible = "fsl,imx28-icoll", "fsl,icoll";
61 #interrupt-cells = <1>;
62 reg = <0x80000000 0x2000>;
66 reg = <0x80002000 0x2000>;
68 dmas = <&dma_apbh 12>;
73 dma_apbh: dma-apbh@80004000 {
74 compatible = "fsl,imx28-dma-apbh";
75 reg = <0x80004000 0x2000>;
76 interrupts = <82 83 84 85
80 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
81 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
82 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
83 "hsadc", "lcdif", "empty", "empty";
90 reg = <0x80006000 0x800>;
96 compatible = "fsl,imx28-gpmi-nand";
99 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
100 reg-names = "gpmi-nand", "bch";
101 interrupts = <88>, <41>;
102 interrupt-names = "gpmi-dma", "bch";
104 clock-names = "gpmi_io";
105 dmas = <&dma_apbh 4>;
107 fsl,gpmi-dma-channel = <4>;
112 #address-cells = <1>;
114 reg = <0x80010000 0x2000>;
115 interrupts = <96 82>;
117 dmas = <&dma_apbh 0>;
119 fsl,ssp-dma-channel = <0>;
124 #address-cells = <1>;
126 reg = <0x80012000 0x2000>;
127 interrupts = <97 83>;
129 dmas = <&dma_apbh 1>;
131 fsl,ssp-dma-channel = <1>;
136 #address-cells = <1>;
138 reg = <0x80014000 0x2000>;
139 interrupts = <98 84>;
141 dmas = <&dma_apbh 2>;
143 fsl,ssp-dma-channel = <2>;
148 #address-cells = <1>;
150 reg = <0x80016000 0x2000>;
151 interrupts = <99 85>;
153 dmas = <&dma_apbh 3>;
155 fsl,ssp-dma-channel = <3>;
160 #address-cells = <1>;
162 compatible = "fsl,imx28-pinctrl", "simple-bus";
163 reg = <0x80018000 0x2000>;
166 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
170 interrupt-controller;
171 #interrupt-cells = <2>;
175 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
179 interrupt-controller;
180 #interrupt-cells = <2>;
184 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
188 interrupt-controller;
189 #interrupt-cells = <2>;
193 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
197 interrupt-controller;
198 #interrupt-cells = <2>;
202 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
206 interrupt-controller;
207 #interrupt-cells = <2>;
210 duart_pins_a: duart@0 {
213 0x3102 /* MX28_PAD_PWM0__DUART_RX */
214 0x3112 /* MX28_PAD_PWM1__DUART_TX */
216 fsl,drive-strength = <0>;
221 duart_pins_b: duart@1 {
224 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
225 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
227 fsl,drive-strength = <0>;
232 duart_4pins_a: duart-4pins@0 {
235 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
236 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
237 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
238 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
240 fsl,drive-strength = <0>;
245 gpmi_pins_a: gpmi-nand@0 {
248 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
249 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
250 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
251 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
252 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
253 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
254 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
255 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
256 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
257 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
258 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
259 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
260 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
261 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
262 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
264 fsl,drive-strength = <0>;
269 gpmi_status_cfg: gpmi-status-cfg {
271 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
272 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
273 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
275 fsl,drive-strength = <2>;
278 auart0_pins_a: auart0@0 {
281 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
282 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
283 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
284 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
286 fsl,drive-strength = <0>;
291 auart0_2pins_a: auart0-2pins@0 {
294 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
295 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
297 fsl,drive-strength = <0>;
302 auart1_pins_a: auart1@0 {
305 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
306 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
307 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
308 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
310 fsl,drive-strength = <0>;
315 auart1_2pins_a: auart1-2pins@0 {
318 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
319 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
321 fsl,drive-strength = <0>;
326 auart2_2pins_a: auart2-2pins@0 {
329 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
330 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
332 fsl,drive-strength = <0>;
337 auart3_pins_a: auart3@0 {
340 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
341 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
342 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
343 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
345 fsl,drive-strength = <0>;
350 auart3_2pins_a: auart3-2pins@0 {
353 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
354 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
356 fsl,drive-strength = <0>;
361 mac0_pins_a: mac0@0 {
364 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
365 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
366 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
367 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
368 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
369 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
370 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
371 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
372 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
374 fsl,drive-strength = <1>;
379 mac1_pins_a: mac1@0 {
382 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
383 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
384 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
385 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
386 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
387 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
389 fsl,drive-strength = <1>;
394 mmc0_8bit_pins_a: mmc0-8bit@0 {
397 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
398 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
399 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
400 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
401 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
402 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
403 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
404 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
405 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
406 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
407 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
409 fsl,drive-strength = <1>;
414 mmc0_4bit_pins_a: mmc0-4bit@0 {
417 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
418 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
419 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
420 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
421 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
422 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
423 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
425 fsl,drive-strength = <1>;
430 mmc0_cd_cfg: mmc0-cd-cfg {
432 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
437 mmc0_sck_cfg: mmc0-sck-cfg {
439 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
441 fsl,drive-strength = <2>;
445 i2c0_pins_a: i2c0@0 {
448 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
449 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
451 fsl,drive-strength = <1>;
456 i2c0_pins_b: i2c0@1 {
459 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
460 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
462 fsl,drive-strength = <1>;
467 i2c1_pins_a: i2c1@0 {
470 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
471 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
473 fsl,drive-strength = <1>;
478 saif0_pins_a: saif0@0 {
481 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
482 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
483 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
484 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
486 fsl,drive-strength = <2>;
491 saif1_pins_a: saif1@0 {
494 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
496 fsl,drive-strength = <2>;
501 pwm0_pins_a: pwm0@0 {
504 0x3100 /* MX28_PAD_PWM0__PWM_0 */
506 fsl,drive-strength = <0>;
511 pwm2_pins_a: pwm2@0 {
514 0x3120 /* MX28_PAD_PWM2__PWM_2 */
516 fsl,drive-strength = <0>;
521 pwm3_pins_a: pwm3@0 {
524 0x31c0 /* MX28_PAD_PWM3__PWM_3 */
526 fsl,drive-strength = <0>;
531 pwm3_pins_b: pwm3@1 {
534 0x3141 /* MX28_PAD_SAIF0_MCLK__PWM3 */
536 fsl,drive-strength = <0>;
541 pwm4_pins_a: pwm4@0 {
544 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
546 fsl,drive-strength = <0>;
551 lcdif_24bit_pins_a: lcdif-24bit@0 {
554 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
555 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
556 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
557 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
558 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
559 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
560 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
561 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
562 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
563 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
564 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
565 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
566 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
567 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
568 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
569 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
570 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
571 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
572 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
573 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
574 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
575 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
576 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
577 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
579 fsl,drive-strength = <0>;
584 lcdif_16bit_pins_a: lcdif-16bit@0 {
587 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
588 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
589 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
590 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
591 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
592 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
593 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
594 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
595 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
596 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
597 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
598 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
599 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
600 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
601 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
602 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
604 fsl,drive-strength = <0>;
609 can0_pins_a: can0@0 {
612 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
613 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
615 fsl,drive-strength = <0>;
620 can1_pins_a: can1@0 {
623 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
624 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
626 fsl,drive-strength = <0>;
631 spi2_pins_a: spi2@0 {
634 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
635 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
636 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
637 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
639 fsl,drive-strength = <1>;
644 usbphy0_pins_a: usbphy0@0 {
647 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
649 fsl,drive-strength = <2>;
654 usbphy0_pins_b: usbphy0@1 {
657 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
659 fsl,drive-strength = <2>;
664 usbphy1_pins_a: usbphy1@0 {
667 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
669 fsl,drive-strength = <2>;
676 compatible = "fsl,imx28-digctl";
677 reg = <0x8001c000 0x2000>;
683 reg = <0x80022000 0x2000>;
687 dma_apbx: dma-apbx@80024000 {
688 compatible = "fsl,imx28-dma-apbx";
689 reg = <0x80024000 0x2000>;
690 interrupts = <78 79 66 0
694 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
695 "saif0", "saif1", "i2c0", "i2c1",
696 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
697 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
704 reg = <0x80028000 0x2000>;
705 interrupts = <52 53 54>;
710 reg = <0x8002a000 0x2000>;
716 compatible = "fsl,ocotp";
717 reg = <0x8002c000 0x2000>;
722 reg = <0x8002e000 0x2000>;
727 compatible = "fsl,imx28-lcdif";
728 reg = <0x80030000 0x2000>;
729 interrupts = <38 86>;
731 dmas = <&dma_apbh 13>;
737 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
738 reg = <0x80032000 0x2000>;
740 clocks = <&clks 58>, <&clks 58>;
741 clock-names = "ipg", "per";
746 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
747 reg = <0x80034000 0x2000>;
749 clocks = <&clks 59>, <&clks 59>;
750 clock-names = "ipg", "per";
755 reg = <0x8003c000 0x200>;
759 simgpmisel@8003c200 {
760 reg = <0x8003c200 0x100>;
765 reg = <0x8003c300 0x100>;
770 reg = <0x8003c400 0x100>;
775 reg = <0x8003c500 0x100>;
780 reg = <0x8003c700 0x100>;
785 reg = <0x8003c800 0x100>;
791 compatible = "simple-bus";
792 #address-cells = <1>;
794 reg = <0x80040000 0x40000>;
797 clks: clkctrl@80040000 {
798 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
799 reg = <0x80040000 0x2000>;
803 saif0: saif@80042000 {
804 compatible = "fsl,imx28-saif";
805 reg = <0x80042000 0x2000>;
806 interrupts = <59 80>;
808 dmas = <&dma_apbx 4>;
810 fsl,saif-dma-channel = <4>;
815 reg = <0x80044000 0x2000>;
819 saif1: saif@80046000 {
820 compatible = "fsl,imx28-saif";
821 reg = <0x80046000 0x2000>;
822 interrupts = <58 81>;
824 dmas = <&dma_apbx 5>;
826 fsl,saif-dma-channel = <5>;
831 compatible = "fsl,imx28-lradc";
832 reg = <0x80050000 0x2000>;
833 interrupts = <10 14 15 16 17 18 19
839 reg = <0x80054000 0x2000>;
840 interrupts = <45 66>;
841 dmas = <&dma_apbx 2>;
847 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
848 reg = <0x80056000 0x2000>;
853 #address-cells = <1>;
855 compatible = "fsl,imx28-i2c";
856 reg = <0x80058000 0x2000>;
857 interrupts = <111 68>;
858 clock-frequency = <100000>;
859 dmas = <&dma_apbx 6>;
861 fsl,i2c-dma-channel = <6>;
866 #address-cells = <1>;
868 compatible = "fsl,imx28-i2c";
869 reg = <0x8005a000 0x2000>;
870 interrupts = <110 69>;
871 clock-frequency = <100000>;
872 dmas = <&dma_apbx 7>;
874 fsl,i2c-dma-channel = <7>;
879 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
880 reg = <0x80064000 0x2000>;
883 fsl,pwm-number = <8>;
888 compatible = "fsl,imx28-timrot", "fsl,timrot";
889 reg = <0x80068000 0x2000>;
890 interrupts = <48 49 50 51>;
894 auart0: serial@8006a000 {
895 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
896 reg = <0x8006a000 0x2000>;
897 interrupts = <112 70 71>;
898 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
899 dma-names = "rx", "tx";
900 fsl,auart-dma-channel = <8 9>;
905 auart1: serial@8006c000 {
906 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
907 reg = <0x8006c000 0x2000>;
908 interrupts = <113 72 73>;
909 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
910 dma-names = "rx", "tx";
915 auart2: serial@8006e000 {
916 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
917 reg = <0x8006e000 0x2000>;
918 interrupts = <114 74 75>;
919 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
920 dma-names = "rx", "tx";
925 auart3: serial@80070000 {
926 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
927 reg = <0x80070000 0x2000>;
928 interrupts = <115 76 77>;
929 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
930 dma-names = "rx", "tx";
935 auart4: serial@80072000 {
936 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
937 reg = <0x80072000 0x2000>;
938 interrupts = <116 78 79>;
939 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
940 dma-names = "rx", "tx";
945 duart: serial@80074000 {
946 compatible = "arm,pl011", "arm,primecell";
947 reg = <0x80074000 0x1000>;
949 clocks = <&clks 45>, <&clks 26>;
950 clock-names = "uart", "apb_pclk";
954 usbphy0: usbphy@8007c000 {
955 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
956 reg = <0x8007c000 0x2000>;
961 usbphy1: usbphy@8007e000 {
962 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
963 reg = <0x8007e000 0x2000>;
971 compatible = "simple-bus";
972 #address-cells = <1>;
974 reg = <0x80080000 0x80000>;
978 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
979 reg = <0x80080000 0x10000>;
982 fsl,usbphy = <&usbphy0>;
987 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
988 reg = <0x80090000 0x10000>;
991 fsl,usbphy = <&usbphy1>;
996 reg = <0x800c0000 0x10000>;
1000 mac0: ethernet@800f0000 {
1001 compatible = "fsl,imx28-fec";
1002 reg = <0x800f0000 0x4000>;
1004 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1005 clock-names = "ipg", "ahb", "enet_out";
1006 status = "disabled";
1009 mac1: ethernet@800f4000 {
1010 compatible = "fsl,imx28-fec";
1011 reg = <0x800f4000 0x4000>;
1013 clocks = <&clks 57>, <&clks 57>;
1014 clock-names = "ipg", "ahb";
1015 status = "disabled";
1019 reg = <0x800f8000 0x8000>;
1020 status = "disabled";