2 * Copyright 2012 Sascha Hauer, Pengutronix
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include "skeleton.dtsi"
13 #include "imx27-pinfunc.h"
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/gpio/gpio.h>
38 aitc: aitc-interrupt-controller@e0000000 {
39 compatible = "fsl,imx27-aitc", "fsl,avic";
41 #interrupt-cells = <1>;
42 reg = <0x10040000 0x1000>;
50 compatible = "fsl,imx-osc26m", "fixed-clock";
51 clock-frequency = <26000000>;
61 compatible = "arm,arm926ej-s";
67 clock-latency = <62500>;
69 voltage-tolerance = <5>;
76 compatible = "simple-bus";
77 interrupt-parent = <&aitc>;
80 aipi@10000000 { /* AIPI1 */
81 compatible = "fsl,aipi-bus", "simple-bus";
84 reg = <0x10000000 0x20000>;
88 compatible = "fsl,imx27-dma";
89 reg = <0x10001000 0x1000>;
91 clocks = <&clks 50>, <&clks 70>;
92 clock-names = "ipg", "ahb";
98 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
99 reg = <0x10002000 0x1000>;
104 gpt1: timer@10003000 {
105 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
106 reg = <0x10003000 0x1000>;
108 clocks = <&clks 46>, <&clks 61>;
109 clock-names = "ipg", "per";
112 gpt2: timer@10004000 {
113 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
114 reg = <0x10004000 0x1000>;
116 clocks = <&clks 45>, <&clks 61>;
117 clock-names = "ipg", "per";
120 gpt3: timer@10005000 {
121 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
122 reg = <0x10005000 0x1000>;
124 clocks = <&clks 44>, <&clks 61>;
125 clock-names = "ipg", "per";
130 compatible = "fsl,imx27-pwm";
131 reg = <0x10006000 0x1000>;
133 clocks = <&clks 34>, <&clks 61>;
134 clock-names = "ipg", "per";
138 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
139 reg = <0x10008000 0x1000>;
145 owire: owire@10009000 {
146 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
147 reg = <0x10009000 0x1000>;
152 uart1: serial@1000a000 {
153 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
154 reg = <0x1000a000 0x1000>;
156 clocks = <&clks 81>, <&clks 61>;
157 clock-names = "ipg", "per";
161 uart2: serial@1000b000 {
162 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
163 reg = <0x1000b000 0x1000>;
165 clocks = <&clks 80>, <&clks 61>;
166 clock-names = "ipg", "per";
170 uart3: serial@1000c000 {
171 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
172 reg = <0x1000c000 0x1000>;
174 clocks = <&clks 79>, <&clks 61>;
175 clock-names = "ipg", "per";
179 uart4: serial@1000d000 {
180 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
181 reg = <0x1000d000 0x1000>;
183 clocks = <&clks 78>, <&clks 61>;
184 clock-names = "ipg", "per";
188 cspi1: cspi@1000e000 {
189 #address-cells = <1>;
191 compatible = "fsl,imx27-cspi";
192 reg = <0x1000e000 0x1000>;
194 clocks = <&clks 53>, <&clks 60>;
195 clock-names = "ipg", "per";
199 cspi2: cspi@1000f000 {
200 #address-cells = <1>;
202 compatible = "fsl,imx27-cspi";
203 reg = <0x1000f000 0x1000>;
205 clocks = <&clks 52>, <&clks 60>;
206 clock-names = "ipg", "per";
211 #sound-dai-cells = <0>;
212 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
213 reg = <0x10010000 0x1000>;
216 dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
217 dma-names = "rx0", "tx0", "rx1", "tx1";
218 fsl,fifo-depth = <8>;
223 #sound-dai-cells = <0>;
224 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
225 reg = <0x10011000 0x1000>;
228 dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
229 dma-names = "rx0", "tx0", "rx1", "tx1";
230 fsl,fifo-depth = <8>;
235 #address-cells = <1>;
237 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
238 reg = <0x10012000 0x1000>;
244 sdhci1: sdhci@10013000 {
245 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
246 reg = <0x10013000 0x1000>;
248 clocks = <&clks 30>, <&clks 60>;
249 clock-names = "ipg", "per";
255 sdhci2: sdhci@10014000 {
256 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
257 reg = <0x10014000 0x1000>;
259 clocks = <&clks 29>, <&clks 60>;
260 clock-names = "ipg", "per";
266 iomuxc: iomuxc@10015000 {
267 compatible = "fsl,imx27-iomuxc";
268 reg = <0x10015000 0x600>;
269 #address-cells = <1>;
273 gpio1: gpio@10015000 {
274 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
275 reg = <0x10015000 0x100>;
279 interrupt-controller;
280 #interrupt-cells = <2>;
283 gpio2: gpio@10015100 {
284 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
285 reg = <0x10015100 0x100>;
289 interrupt-controller;
290 #interrupt-cells = <2>;
293 gpio3: gpio@10015200 {
294 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
295 reg = <0x10015200 0x100>;
299 interrupt-controller;
300 #interrupt-cells = <2>;
303 gpio4: gpio@10015300 {
304 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
305 reg = <0x10015300 0x100>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
313 gpio5: gpio@10015400 {
314 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
315 reg = <0x10015400 0x100>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
323 gpio6: gpio@10015500 {
324 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
325 reg = <0x10015500 0x100>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
334 audmux: audmux@10016000 {
335 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
336 reg = <0x10016000 0x1000>;
338 clock-names = "audmux";
342 cspi3: cspi@10017000 {
343 #address-cells = <1>;
345 compatible = "fsl,imx27-cspi";
346 reg = <0x10017000 0x1000>;
348 clocks = <&clks 51>, <&clks 60>;
349 clock-names = "ipg", "per";
353 gpt4: timer@10019000 {
354 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
355 reg = <0x10019000 0x1000>;
357 clocks = <&clks 43>, <&clks 61>;
358 clock-names = "ipg", "per";
361 gpt5: timer@1001a000 {
362 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
363 reg = <0x1001a000 0x1000>;
365 clocks = <&clks 42>, <&clks 61>;
366 clock-names = "ipg", "per";
369 uart5: serial@1001b000 {
370 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
371 reg = <0x1001b000 0x1000>;
373 clocks = <&clks 77>, <&clks 61>;
374 clock-names = "ipg", "per";
378 uart6: serial@1001c000 {
379 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
380 reg = <0x1001c000 0x1000>;
382 clocks = <&clks 78>, <&clks 61>;
383 clock-names = "ipg", "per";
388 #address-cells = <1>;
390 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
391 reg = <0x1001d000 0x1000>;
397 sdhci3: sdhci@1001e000 {
398 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
399 reg = <0x1001e000 0x1000>;
401 clocks = <&clks 28>, <&clks 60>;
402 clock-names = "ipg", "per";
408 gpt6: timer@1001f000 {
409 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
410 reg = <0x1001f000 0x1000>;
412 clocks = <&clks 41>, <&clks 61>;
413 clock-names = "ipg", "per";
417 aipi@10020000 { /* AIPI2 */
418 compatible = "fsl,aipi-bus", "simple-bus";
419 #address-cells = <1>;
421 reg = <0x10020000 0x20000>;
425 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
427 reg = <0x10021000 0x1000>;
428 clocks = <&clks 36>, <&clks 65>, <&clks 59>;
429 clock-names = "ipg", "ahb", "per";
433 coda: coda@10023000 {
434 compatible = "fsl,imx27-vpu";
435 reg = <0x10023000 0x0200>;
437 clocks = <&clks 57>, <&clks 66>;
438 clock-names = "per", "ahb";
442 sahara2: sahara@10025000 {
443 compatible = "fsl,imx27-sahara";
444 reg = <0x10025000 0x1000>;
446 clocks = <&clks 32>, <&clks 64>;
447 clock-names = "ipg", "ahb";
451 compatible = "fsl,imx27-ccm";
452 reg = <0x10027000 0x1000>;
457 compatible = "fsl,imx27-iim";
458 reg = <0x10028000 0x1000>;
463 fec: ethernet@1002b000 {
464 compatible = "fsl,imx27-fec";
465 reg = <0x1002b000 0x4000>;
467 clocks = <&clks 48>, <&clks 67>;
468 clock-names = "ipg", "ahb";
474 #address-cells = <1>;
476 compatible = "fsl,imx27-nand";
477 reg = <0xd8000000 0x1000>;
483 weim: weim@d8002000 {
484 #address-cells = <2>;
486 compatible = "fsl,imx27-weim";
487 reg = <0xd8002000 0x1000>;
490 0 0 0xc0000000 0x08000000
491 1 0 0xc8000000 0x08000000
492 2 0 0xd0000000 0x02000000
493 3 0 0xd2000000 0x02000000
494 4 0 0xd4000000 0x02000000
495 5 0 0xd6000000 0x02000000
500 iram: iram@ffff4c00 {
501 compatible = "mmio-sram";
502 reg = <0xffff4c00 0xb400>;