arch/arm/boot/dts/imx27.dtsi

   1 /*
   2  * Copyright 2012 Sascha Hauer, Pengutronix
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include "skeleton.dtsi"
  13
  14 / {
  15         aliases {
  16                 serial0 = &uart1;
  17                 serial1 = &uart2;
  18                 serial2 = &uart3;
  19                 serial3 = &uart4;
  20                 serial4 = &uart5;
  21                 serial5 = &uart6;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 gpio5 = &gpio6;
  28                 spi0 = &cspi1;
  29                 spi1 = &cspi2;
  30                 spi2 = &cspi3;
  31         };
  32
  33         avic: avic-interrupt-controller@e0000000 {
  34                 compatible = "fsl,imx27-avic", "fsl,avic";
  35                 interrupt-controller;
  36                 #interrupt-cells = <1>;
  37                 reg = <0x10040000 0x1000>;
  38         };
  39
  40         clocks {
  41                 #address-cells = <1>;
  42                 #size-cells = <0>;
  43
  44                 osc26m {
  45                         compatible = "fsl,imx-osc26m", "fixed-clock";
  46                         clock-frequency = <26000000>;
  47                 };
  48         };
  49
  50         soc {
  51                 #address-cells = <1>;
  52                 #size-cells = <1>;
  53                 compatible = "simple-bus";
  54                 interrupt-parent = <&avic>;
  55                 ranges;
  56
  57                 aipi@10000000 { /* AIPI1 */
  58                         compatible = "fsl,aipi-bus", "simple-bus";
  59                         #address-cells = <1>;
  60                         #size-cells = <1>;
  61                         reg = <0x10000000 0x20000>;
  62                         ranges;
  63
  64                         dma: dma@10001000 {
  65                                 compatible = "fsl,imx27-dma";
  66                                 reg = <0x10001000 0x1000>;
  67                                 interrupts = <32>;
  68                                 clocks = <&clks 50>, <&clks 70>;
  69                                 clock-names = "ipg", "ahb";
  70                                 #dma-cells = <1>;
  71                                 #dma-channels = <16>;
  72                         };
  73
  74                         wdog: wdog@10002000 {
  75                                 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
  76                                 reg = <0x10002000 0x1000>;
  77                                 interrupts = <27>;
  78                                 clocks = <&clks 0>;
  79                         };
  80
  81                         gpt1: timer@10003000 {
  82                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
  83                                 reg = <0x10003000 0x1000>;
  84                                 interrupts = <26>;
  85                                 clocks = <&clks 46>, <&clks 61>;
  86                                 clock-names = "ipg", "per";
  87                         };
  88
  89                         gpt2: timer@10004000 {
  90                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
  91                                 reg = <0x10004000 0x1000>;
  92                                 interrupts = <25>;
  93                                 clocks = <&clks 45>, <&clks 61>;
  94                                 clock-names = "ipg", "per";
  95                         };
  96
  97                         gpt3: timer@10005000 {
  98                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
  99                                 reg = <0x10005000 0x1000>;
 100                                 interrupts = <24>;
 101                                 clocks = <&clks 44>, <&clks 61>;
 102                                 clock-names = "ipg", "per";
 103                         };
 104
 105                         pwm: pwm@10006000 {
 106                                 compatible = "fsl,imx27-pwm";
 107                                 reg = <0x10006000 0x1000>;
 108                                 interrupts = <23>;
 109                                 clocks = <&clks 34>, <&clks 61>;
 110                                 clock-names = "ipg", "per";
 111                         };
 112
 113                         uart1: serial@1000a000 {
 114                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 115                                 reg = <0x1000a000 0x1000>;
 116                                 interrupts = <20>;
 117                                 clocks = <&clks 81>, <&clks 61>;
 118                                 clock-names = "ipg", "per";
 119                                 status = "disabled";
 120                         };
 121
 122                         uart2: serial@1000b000 {
 123                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 124                                 reg = <0x1000b000 0x1000>;
 125                                 interrupts = <19>;
 126                                 clocks = <&clks 80>, <&clks 61>;
 127                                 clock-names = "ipg", "per";
 128                                 status = "disabled";
 129                         };
 130
 131                         uart3: serial@1000c000 {
 132                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 133                                 reg = <0x1000c000 0x1000>;
 134                                 interrupts = <18>;
 135                                 clocks = <&clks 79>, <&clks 61>;
 136                                 clock-names = "ipg", "per";
 137                                 status = "disabled";
 138                         };
 139
 140                         uart4: serial@1000d000 {
 141                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 142                                 reg = <0x1000d000 0x1000>;
 143                                 interrupts = <17>;
 144                                 clocks = <&clks 78>, <&clks 61>;
 145                                 clock-names = "ipg", "per";
 146                                 status = "disabled";
 147                         };
 148
 149                         cspi1: cspi@1000e000 {
 150                                 #address-cells = <1>;
 151                                 #size-cells = <0>;
 152                                 compatible = "fsl,imx27-cspi";
 153                                 reg = <0x1000e000 0x1000>;
 154                                 interrupts = <16>;
 155                                 clocks = <&clks 53>, <&clks 53>;
 156                                 clock-names = "ipg", "per";
 157                                 status = "disabled";
 158                         };
 159
 160                         cspi2: cspi@1000f000 {
 161                                 #address-cells = <1>;
 162                                 #size-cells = <0>;
 163                                 compatible = "fsl,imx27-cspi";
 164                                 reg = <0x1000f000 0x1000>;
 165                                 interrupts = <15>;
 166                                 clocks = <&clks 52>, <&clks 52>;
 167                                 clock-names = "ipg", "per";
 168                                 status = "disabled";
 169                         };
 170
 171                         i2c1: i2c@10012000 {
 172                                 #address-cells = <1>;
 173                                 #size-cells = <0>;
 174                                 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
 175                                 reg = <0x10012000 0x1000>;
 176                                 interrupts = <12>;
 177                                 clocks = <&clks 40>;
 178                                 status = "disabled";
 179                         };
 180
 181                         sdhci1: sdhci@10013000 {
 182                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 183                                 reg = <0x10013000 0x1000>;
 184                                 interrupts = <11>;
 185                                 clocks = <&clks 30>, <&clks 60>;
 186                                 clock-names = "ipg", "per";
 187                                 dmas = <&dma 7>;
 188                                 dma-names = "rx-tx";
 189                                 status = "disabled";
 190                         };
 191
 192                         sdhci2: sdhci@10014000 {
 193                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 194                                 reg = <0x10014000 0x1000>;
 195                                 interrupts = <10>;
 196                                 clocks = <&clks 29>, <&clks 60>;
 197                                 clock-names = "ipg", "per";
 198                                 dmas = <&dma 6>;
 199                                 dma-names = "rx-tx";
 200                                 status = "disabled";
 201                         };
 202
 203                         gpio1: gpio@10015000 {
 204                                 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 205                                 reg = <0x10015000 0x100>;
 206                                 interrupts = <8>;
 207                                 gpio-controller;
 208                                 #gpio-cells = <2>;
 209                                 interrupt-controller;
 210                                 #interrupt-cells = <2>;
 211                         };
 212
 213                         gpio2: gpio@10015100 {
 214                                 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 215                                 reg = <0x10015100 0x100>;
 216                                 interrupts = <8>;
 217                                 gpio-controller;
 218                                 #gpio-cells = <2>;
 219                                 interrupt-controller;
 220                                 #interrupt-cells = <2>;
 221                         };
 222
 223                         gpio3: gpio@10015200 {
 224                                 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 225                                 reg = <0x10015200 0x100>;
 226                                 interrupts = <8>;
 227                                 gpio-controller;
 228                                 #gpio-cells = <2>;
 229                                 interrupt-controller;
 230                                 #interrupt-cells = <2>;
 231                         };
 232
 233                         gpio4: gpio@10015300 {
 234                                 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 235                                 reg = <0x10015300 0x100>;
 236                                 interrupts = <8>;
 237                                 gpio-controller;
 238                                 #gpio-cells = <2>;
 239                                 interrupt-controller;
 240                                 #interrupt-cells = <2>;
 241                         };
 242
 243                         gpio5: gpio@10015400 {
 244                                 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 245                                 reg = <0x10015400 0x100>;
 246                                 interrupts = <8>;
 247                                 gpio-controller;
 248                                 #gpio-cells = <2>;
 249                                 interrupt-controller;
 250                                 #interrupt-cells = <2>;
 251                         };
 252
 253                         gpio6: gpio@10015500 {
 254                                 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 255                                 reg = <0x10015500 0x100>;
 256                                 interrupts = <8>;
 257                                 gpio-controller;
 258                                 #gpio-cells = <2>;
 259                                 interrupt-controller;
 260                                 #interrupt-cells = <2>;
 261                         };
 262
 263                         audmux: audmux@10016000 {
 264                                 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
 265                                 reg = <0x10016000 0x1000>;
 266                                 clocks = <&clks 0>;
 267                                 clock-names = "audmux";
 268                         };
 269
 270                         cspi3: cspi@10017000 {
 271                                 #address-cells = <1>;
 272                                 #size-cells = <0>;
 273                                 compatible = "fsl,imx27-cspi";
 274                                 reg = <0x10017000 0x1000>;
 275                                 interrupts = <6>;
 276                                 clocks = <&clks 51>, <&clks 51>;
 277                                 clock-names = "ipg", "per";
 278                                 status = "disabled";
 279                         };
 280
 281                         gpt4: timer@10019000 {
 282                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
 283                                 reg = <0x10019000 0x1000>;
 284                                 interrupts = <4>;
 285                                 clocks = <&clks 43>, <&clks 61>;
 286                                 clock-names = "ipg", "per";
 287                         };
 288
 289                         gpt5: timer@1001a000 {
 290                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
 291                                 reg = <0x1001a000 0x1000>;
 292                                 interrupts = <3>;
 293                                 clocks = <&clks 42>, <&clks 61>;
 294                                 clock-names = "ipg", "per";
 295                         };
 296
 297                         uart5: serial@1001b000 {
 298                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 299                                 reg = <0x1001b000 0x1000>;
 300                                 interrupts = <49>;
 301                                 clocks = <&clks 77>, <&clks 61>;
 302                                 clock-names = "ipg", "per";
 303                                 status = "disabled";
 304                         };
 305
 306                         uart6: serial@1001c000 {
 307                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 308                                 reg = <0x1001c000 0x1000>;
 309                                 interrupts = <48>;
 310                                 clocks = <&clks 78>, <&clks 61>;
 311                                 clock-names = "ipg", "per";
 312                                 status = "disabled";
 313                         };
 314
 315                         i2c2: i2c@1001d000 {
 316                                 #address-cells = <1>;
 317                                 #size-cells = <0>;
 318                                 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
 319                                 reg = <0x1001d000 0x1000>;
 320                                 interrupts = <1>;
 321                                 clocks = <&clks 39>;
 322                                 status = "disabled";
 323                         };
 324
 325                         sdhci3: sdhci@1001e000 {
 326                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 327                                 reg = <0x1001e000 0x1000>;
 328                                 interrupts = <9>;
 329                                 clocks = <&clks 28>, <&clks 60>;
 330                                 clock-names = "ipg", "per";
 331                                 dmas = <&dma 36>;
 332                                 dma-names = "rx-tx";
 333                                 status = "disabled";
 334                         };
 335
 336                         gpt6: timer@1001f000 {
 337                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
 338                                 reg = <0x1001f000 0x1000>;
 339                                 interrupts = <2>;
 340                                 clocks = <&clks 41>, <&clks 61>;
 341                                 clock-names = "ipg", "per";
 342                         };
 343                 };
 344
 345                 aipi@10020000 { /* AIPI2 */
 346                         compatible = "fsl,aipi-bus", "simple-bus";
 347                         #address-cells = <1>;
 348                         #size-cells = <1>;
 349                         reg = <0x10020000 0x20000>;
 350                         ranges;
 351
 352                         coda: coda@10023000 {
 353                                 compatible = "fsl,imx27-vpu";
 354                                 reg = <0x10023000 0x0200>;
 355                                 interrupts = <53>;
 356                                 clocks = <&clks 57>, <&clks 66>;
 357                                 clock-names = "per", "ahb";
 358                                 iram = <&iram>;
 359                         };
 360
 361                         sahara2: sahara@10025000 {
 362                                 compatible = "fsl,imx27-sahara";
 363                                 reg = <0x10025000 0x1000>;
 364                                 interrupts = <59>;
 365                                 clocks = <&clks 32>, <&clks 64>;
 366                                 clock-names = "ipg", "ahb";
 367                         };
 368
 369                         clks: ccm@10027000{
 370                                 compatible = "fsl,imx27-ccm";
 371                                 reg = <0x10027000 0x1000>;
 372                                 #clock-cells = <1>;
 373                         };
 374
 375                         fec: ethernet@1002b000 {
 376                                 compatible = "fsl,imx27-fec";
 377                                 reg = <0x1002b000 0x4000>;
 378                                 interrupts = <50>;
 379                                 clocks = <&clks 48>, <&clks 67>, <&clks 0>;
 380                                 clock-names = "ipg", "ahb", "ptp";
 381                                 status = "disabled";
 382                         };
 383                 };
 384
 385                 nfc: nand@d8000000 {
 386                         #address-cells = <1>;
 387                         #size-cells = <1>;
 388                         compatible = "fsl,imx27-nand";
 389                         reg = <0xd8000000 0x1000>;
 390                         interrupts = <29>;
 391                         clocks = <&clks 54>;
 392                         status = "disabled";
 393                 };
 394
 395                 iram: iram@ffff4c00 {
 396                         compatible = "mmio-sram";
 397                         reg = <0xffff4c00 0xb400>;
 398                 };
 399         };
 400 };