2 * Hisilicon Ltd. HiP04 SoC
4 * Copyright (C) 2013-2014 Hisilicon Ltd.
5 * Copyright (C) 2013-2014 Linaro Ltd.
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 /* memory bus is 64-bit */
24 compatible = "hisilicon,hip04-bootwrapper";
25 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
92 compatible = "arm,cortex-a15";
97 compatible = "arm,cortex-a15";
102 compatible = "arm,cortex-a15";
107 compatible = "arm,cortex-a15";
112 compatible = "arm,cortex-a15";
117 compatible = "arm,cortex-a15";
122 compatible = "arm,cortex-a15";
127 compatible = "arm,cortex-a15";
132 compatible = "arm,cortex-a15";
137 compatible = "arm,cortex-a15";
142 compatible = "arm,cortex-a15";
147 compatible = "arm,cortex-a15";
152 compatible = "arm,cortex-a15";
157 compatible = "arm,cortex-a15";
162 compatible = "arm,cortex-a15";
167 compatible = "arm,cortex-a15";
173 compatible = "arm,armv7-timer";
174 interrupt-parent = <&gic>;
175 interrupts = <1 13 0xf08>,
183 compatible = "fixed-clock";
184 clock-frequency = <50000000>;
189 compatible = "fixed-clock";
190 clock-frequency = <168000000>;
194 /* It's a 32-bit SoC. */
195 #address-cells = <1>;
197 compatible = "simple-bus";
198 interrupt-parent = <&gic>;
199 ranges = <0 0 0xe0000000 0x10000000>;
201 gic: interrupt-controller@c01000 {
202 compatible = "hisilicon,hip04-intc";
203 #interrupt-cells = <3>;
204 #address-cells = <0>;
205 interrupt-controller;
206 interrupts = <1 9 0xf04>;
208 reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
209 <0xc04000 0x2000>, <0xc06000 0x2000>;
213 compatible = "hisilicon,sysctrl";
214 reg = <0x3e00000 0x00100000>;
218 compatible = "hisilicon,hip04-fabric";
219 reg = <0x302a000 0x1000>;
222 dual_timer0: dual_timer@3000000 {
223 compatible = "arm,sp804", "arm,primecell";
224 reg = <0x3000000 0x1000>;
225 interrupts = <0 224 4>;
226 clocks = <&clk_50m>, <&clk_50m>;
227 clock-names = "apb_pclk";
231 compatible = "arm,cortex-a15-pmu";
232 interrupts = <0 64 4>,
250 uart0: uart@4007000 {
251 compatible = "snps,dw-apb-uart";
252 reg = <0x4007000 0x1000>;
253 interrupts = <0 381 4>;
254 clocks = <&clk_168m>;
255 clock-names = "uartclk";
260 sata0: sata@a000000 {
261 compatible = "hisilicon,hisi-ahci";
262 reg = <0xa000000 0x1000000>;
263 interrupts = <0 372 4>;