2 * SAMSUNG EXYNOS5420 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <dt-bindings/clock/exynos5420.h>
17 #include "exynos5.dtsi"
18 #include "exynos5420-pinctrl.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
23 compatible = "samsung,exynos5420", "samsung,exynos5";
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2;
32 pinctrl3 = &pinctrl_3;
33 pinctrl4 = &pinctrl_4;
50 usbdrdphy0 = &usbdrd_phy0;
51 usbdrdphy1 = &usbdrd_phy1;
60 compatible = "arm,cortex-a15";
62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>;
68 compatible = "arm,cortex-a15";
70 clock-frequency = <1800000000>;
71 cci-control-port = <&cci_control1>;
76 compatible = "arm,cortex-a15";
78 clock-frequency = <1800000000>;
79 cci-control-port = <&cci_control1>;
84 compatible = "arm,cortex-a15";
86 clock-frequency = <1800000000>;
87 cci-control-port = <&cci_control1>;
92 compatible = "arm,cortex-a7";
94 clock-frequency = <1000000000>;
95 cci-control-port = <&cci_control0>;
100 compatible = "arm,cortex-a7";
102 clock-frequency = <1000000000>;
103 cci-control-port = <&cci_control0>;
108 compatible = "arm,cortex-a7";
110 clock-frequency = <1000000000>;
111 cci-control-port = <&cci_control0>;
116 compatible = "arm,cortex-a7";
118 clock-frequency = <1000000000>;
119 cci-control-port = <&cci_control0>;
124 compatible = "arm,cci-400";
125 #address-cells = <1>;
127 reg = <0x10d20000 0x1000>;
128 ranges = <0x0 0x10d20000 0x6000>;
130 cci_control0: slave-if@4000 {
131 compatible = "arm,cci-400-ctrl-if";
132 interface-type = "ace";
133 reg = <0x4000 0x1000>;
135 cci_control1: slave-if@5000 {
136 compatible = "arm,cci-400-ctrl-if";
137 interface-type = "ace";
138 reg = <0x5000 0x1000>;
143 compatible = "mmio-sram";
144 reg = <0x02020000 0x54000>;
145 #address-cells = <1>;
147 ranges = <0 0x02020000 0x54000>;
150 compatible = "samsung,exynos4210-sysram";
155 compatible = "samsung,exynos4210-sysram-ns";
156 reg = <0x53000 0x1000>;
160 clock: clock-controller@10010000 {
161 compatible = "samsung,exynos5420-clock";
162 reg = <0x10010000 0x30000>;
166 clock_audss: audss-clock-controller@3810000 {
167 compatible = "samsung,exynos5420-audss-clock";
168 reg = <0x03810000 0x0C>;
170 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
171 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
172 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
175 mfc: codec@11000000 {
176 compatible = "samsung,mfc-v7";
177 reg = <0x11000000 0x10000>;
178 interrupts = <0 96 0>;
179 clocks = <&clock CLK_MFC>;
181 power-domains = <&mfc_pd>;
184 mmc_0: mmc@12200000 {
185 compatible = "samsung,exynos5420-dw-mshc-smu";
186 interrupts = <0 75 0>;
187 #address-cells = <1>;
189 reg = <0x12200000 0x2000>;
190 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
191 clock-names = "biu", "ciu";
196 mmc_1: mmc@12210000 {
197 compatible = "samsung,exynos5420-dw-mshc-smu";
198 interrupts = <0 76 0>;
199 #address-cells = <1>;
201 reg = <0x12210000 0x2000>;
202 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
203 clock-names = "biu", "ciu";
208 mmc_2: mmc@12220000 {
209 compatible = "samsung,exynos5420-dw-mshc";
210 interrupts = <0 77 0>;
211 #address-cells = <1>;
213 reg = <0x12220000 0x1000>;
214 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
215 clock-names = "biu", "ciu";
221 compatible = "samsung,exynos4210-mct";
222 reg = <0x101C0000 0x800>;
223 interrupt-controller;
224 #interrups-cells = <1>;
225 interrupt-parent = <&mct_map>;
226 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
227 <8>, <9>, <10>, <11>;
228 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
229 clock-names = "fin_pll", "mct";
232 #interrupt-cells = <1>;
233 #address-cells = <0>;
235 interrupt-map = <0 &combiner 23 3>,
250 gsc_pd: power-domain@10044000 {
251 compatible = "samsung,exynos4210-pd";
252 reg = <0x10044000 0x20>;
253 #power-domain-cells = <0>;
256 isp_pd: power-domain@10044020 {
257 compatible = "samsung,exynos4210-pd";
258 reg = <0x10044020 0x20>;
259 #power-domain-cells = <0>;
262 mfc_pd: power-domain@10044060 {
263 compatible = "samsung,exynos4210-pd";
264 reg = <0x10044060 0x20>;
265 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
266 <&clock CLK_MOUT_USER_ACLK333>;
267 clock-names = "oscclk", "pclk0", "clk0";
268 #power-domain-cells = <0>;
271 msc_pd: power-domain@10044120 {
272 compatible = "samsung,exynos4210-pd";
273 reg = <0x10044120 0x20>;
274 #power-domain-cells = <0>;
277 disp_pd: power-domain@100440C0 {
278 compatible = "samsung,exynos4210-pd";
279 reg = <0x100440C0 0x20>;
280 #power-domain-cells = <0>;
281 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>,
282 <&clock CLK_MOUT_USER_ACLK200_DISP1>,
283 <&clock CLK_MOUT_SW_ACLK300>,
284 <&clock CLK_MOUT_USER_ACLK300_DISP1>,
285 <&clock CLK_MOUT_SW_ACLK400>,
286 <&clock CLK_MOUT_USER_ACLK400_DISP1>;
287 clock-names = "oscclk", "pclk0", "clk0",
288 "pclk1", "clk1", "pclk2", "clk2";
291 pinctrl_0: pinctrl@13400000 {
292 compatible = "samsung,exynos5420-pinctrl";
293 reg = <0x13400000 0x1000>;
294 interrupts = <0 45 0>;
296 wakeup-interrupt-controller {
297 compatible = "samsung,exynos4210-wakeup-eint";
298 interrupt-parent = <&gic>;
299 interrupts = <0 32 0>;
303 pinctrl_1: pinctrl@13410000 {
304 compatible = "samsung,exynos5420-pinctrl";
305 reg = <0x13410000 0x1000>;
306 interrupts = <0 78 0>;
309 pinctrl_2: pinctrl@14000000 {
310 compatible = "samsung,exynos5420-pinctrl";
311 reg = <0x14000000 0x1000>;
312 interrupts = <0 46 0>;
315 pinctrl_3: pinctrl@14010000 {
316 compatible = "samsung,exynos5420-pinctrl";
317 reg = <0x14010000 0x1000>;
318 interrupts = <0 50 0>;
321 pinctrl_4: pinctrl@03860000 {
322 compatible = "samsung,exynos5420-pinctrl";
323 reg = <0x03860000 0x1000>;
324 interrupts = <0 47 0>;
328 clocks = <&clock CLK_RTC>;
330 interrupt-parent = <&pmu_system_controller>;
335 #address-cells = <1>;
337 compatible = "arm,amba-bus";
338 interrupt-parent = <&gic>;
341 adma: adma@03880000 {
342 compatible = "arm,pl330", "arm,primecell";
343 reg = <0x03880000 0x1000>;
344 interrupts = <0 110 0>;
345 clocks = <&clock_audss EXYNOS_ADMA>;
346 clock-names = "apb_pclk";
349 #dma-requests = <16>;
352 pdma0: pdma@121A0000 {
353 compatible = "arm,pl330", "arm,primecell";
354 reg = <0x121A0000 0x1000>;
355 interrupts = <0 34 0>;
356 clocks = <&clock CLK_PDMA0>;
357 clock-names = "apb_pclk";
360 #dma-requests = <32>;
363 pdma1: pdma@121B0000 {
364 compatible = "arm,pl330", "arm,primecell";
365 reg = <0x121B0000 0x1000>;
366 interrupts = <0 35 0>;
367 clocks = <&clock CLK_PDMA1>;
368 clock-names = "apb_pclk";
371 #dma-requests = <32>;
374 mdma0: mdma@10800000 {
375 compatible = "arm,pl330", "arm,primecell";
376 reg = <0x10800000 0x1000>;
377 interrupts = <0 33 0>;
378 clocks = <&clock CLK_MDMA0>;
379 clock-names = "apb_pclk";
385 mdma1: mdma@11C10000 {
386 compatible = "arm,pl330", "arm,primecell";
387 reg = <0x11C10000 0x1000>;
388 interrupts = <0 124 0>;
389 clocks = <&clock CLK_MDMA1>;
390 clock-names = "apb_pclk";
395 * MDMA1 can support both secure and non-secure
396 * AXI transactions. When this is enabled in the kernel
397 * for boards that run in secure mode, we are getting
398 * imprecise external aborts causing the kernel to oops.
405 compatible = "samsung,exynos5420-i2s";
406 reg = <0x03830000 0x100>;
410 dma-names = "tx", "rx", "tx-sec";
411 clocks = <&clock_audss EXYNOS_I2S_BUS>,
412 <&clock_audss EXYNOS_I2S_BUS>,
413 <&clock_audss EXYNOS_SCLK_I2S>;
414 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
415 samsung,idma-addr = <0x03000000>;
416 pinctrl-names = "default";
417 pinctrl-0 = <&i2s0_bus>;
422 compatible = "samsung,exynos5420-i2s";
423 reg = <0x12D60000 0x100>;
426 dma-names = "tx", "rx";
427 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
428 clock-names = "iis", "i2s_opclk0";
429 pinctrl-names = "default";
430 pinctrl-0 = <&i2s1_bus>;
435 compatible = "samsung,exynos5420-i2s";
436 reg = <0x12D70000 0x100>;
439 dma-names = "tx", "rx";
440 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
441 clock-names = "iis", "i2s_opclk0";
442 pinctrl-names = "default";
443 pinctrl-0 = <&i2s2_bus>;
447 spi_0: spi@12d20000 {
448 compatible = "samsung,exynos4210-spi";
449 reg = <0x12d20000 0x100>;
450 interrupts = <0 68 0>;
453 dma-names = "tx", "rx";
454 #address-cells = <1>;
456 pinctrl-names = "default";
457 pinctrl-0 = <&spi0_bus>;
458 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
459 clock-names = "spi", "spi_busclk0";
463 spi_1: spi@12d30000 {
464 compatible = "samsung,exynos4210-spi";
465 reg = <0x12d30000 0x100>;
466 interrupts = <0 69 0>;
469 dma-names = "tx", "rx";
470 #address-cells = <1>;
472 pinctrl-names = "default";
473 pinctrl-0 = <&spi1_bus>;
474 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
475 clock-names = "spi", "spi_busclk0";
479 spi_2: spi@12d40000 {
480 compatible = "samsung,exynos4210-spi";
481 reg = <0x12d40000 0x100>;
482 interrupts = <0 70 0>;
485 dma-names = "tx", "rx";
486 #address-cells = <1>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&spi2_bus>;
490 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
491 clock-names = "spi", "spi_busclk0";
495 uart_0: serial@12C00000 {
496 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
497 clock-names = "uart", "clk_uart_baud0";
500 uart_1: serial@12C10000 {
501 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
502 clock-names = "uart", "clk_uart_baud0";
505 uart_2: serial@12C20000 {
506 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
507 clock-names = "uart", "clk_uart_baud0";
510 uart_3: serial@12C30000 {
511 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
512 clock-names = "uart", "clk_uart_baud0";
516 compatible = "samsung,exynos4210-pwm";
517 reg = <0x12dd0000 0x100>;
518 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
520 clocks = <&clock CLK_PWM>;
521 clock-names = "timers";
524 dp_phy: video-phy@10040728 {
525 compatible = "samsung,exynos5420-dp-video-phy";
526 samsung,pmu-syscon = <&pmu_system_controller>;
530 dp: dp-controller@145B0000 {
531 clocks = <&clock CLK_DP1>;
537 mipi_phy: video-phy@10040714 {
538 compatible = "samsung,s5pv210-mipi-video-phy";
539 reg = <0x10040714 12>;
544 compatible = "samsung,exynos5410-mipi-dsi";
545 reg = <0x14500000 0x10000>;
546 interrupts = <0 82 0>;
547 phys = <&mipi_phy 1>;
549 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
550 clock-names = "bus_clk", "pll_clk";
551 #address-cells = <1>;
556 fimd: fimd@14400000 {
557 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
558 clock-names = "sclk_fimd", "fimd";
559 power-domains = <&disp_pd>;
563 compatible = "samsung,exynos-adc-v2";
564 reg = <0x12D10000 0x100>;
565 interrupts = <0 106 0>;
566 clocks = <&clock CLK_TSADC>;
568 #io-channel-cells = <1>;
570 samsung,syscon-phandle = <&pmu_system_controller>;
574 i2c_0: i2c@12C60000 {
575 compatible = "samsung,s3c2440-i2c";
576 reg = <0x12C60000 0x100>;
577 interrupts = <0 56 0>;
578 #address-cells = <1>;
580 clocks = <&clock CLK_I2C0>;
582 pinctrl-names = "default";
583 pinctrl-0 = <&i2c0_bus>;
584 samsung,sysreg-phandle = <&sysreg_system_controller>;
588 i2c_1: i2c@12C70000 {
589 compatible = "samsung,s3c2440-i2c";
590 reg = <0x12C70000 0x100>;
591 interrupts = <0 57 0>;
592 #address-cells = <1>;
594 clocks = <&clock CLK_I2C1>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&i2c1_bus>;
598 samsung,sysreg-phandle = <&sysreg_system_controller>;
602 i2c_2: i2c@12C80000 {
603 compatible = "samsung,s3c2440-i2c";
604 reg = <0x12C80000 0x100>;
605 interrupts = <0 58 0>;
606 #address-cells = <1>;
608 clocks = <&clock CLK_I2C2>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&i2c2_bus>;
612 samsung,sysreg-phandle = <&sysreg_system_controller>;
616 i2c_3: i2c@12C90000 {
617 compatible = "samsung,s3c2440-i2c";
618 reg = <0x12C90000 0x100>;
619 interrupts = <0 59 0>;
620 #address-cells = <1>;
622 clocks = <&clock CLK_I2C3>;
624 pinctrl-names = "default";
625 pinctrl-0 = <&i2c3_bus>;
626 samsung,sysreg-phandle = <&sysreg_system_controller>;
630 hsi2c_4: i2c@12CA0000 {
631 compatible = "samsung,exynos5-hsi2c";
632 reg = <0x12CA0000 0x1000>;
633 interrupts = <0 60 0>;
634 #address-cells = <1>;
636 pinctrl-names = "default";
637 pinctrl-0 = <&i2c4_hs_bus>;
638 clocks = <&clock CLK_USI0>;
639 clock-names = "hsi2c";
643 hsi2c_5: i2c@12CB0000 {
644 compatible = "samsung,exynos5-hsi2c";
645 reg = <0x12CB0000 0x1000>;
646 interrupts = <0 61 0>;
647 #address-cells = <1>;
649 pinctrl-names = "default";
650 pinctrl-0 = <&i2c5_hs_bus>;
651 clocks = <&clock CLK_USI1>;
652 clock-names = "hsi2c";
656 hsi2c_6: i2c@12CC0000 {
657 compatible = "samsung,exynos5-hsi2c";
658 reg = <0x12CC0000 0x1000>;
659 interrupts = <0 62 0>;
660 #address-cells = <1>;
662 pinctrl-names = "default";
663 pinctrl-0 = <&i2c6_hs_bus>;
664 clocks = <&clock CLK_USI2>;
665 clock-names = "hsi2c";
669 hsi2c_7: i2c@12CD0000 {
670 compatible = "samsung,exynos5-hsi2c";
671 reg = <0x12CD0000 0x1000>;
672 interrupts = <0 63 0>;
673 #address-cells = <1>;
675 pinctrl-names = "default";
676 pinctrl-0 = <&i2c7_hs_bus>;
677 clocks = <&clock CLK_USI3>;
678 clock-names = "hsi2c";
682 hsi2c_8: i2c@12E00000 {
683 compatible = "samsung,exynos5-hsi2c";
684 reg = <0x12E00000 0x1000>;
685 interrupts = <0 87 0>;
686 #address-cells = <1>;
688 pinctrl-names = "default";
689 pinctrl-0 = <&i2c8_hs_bus>;
690 clocks = <&clock CLK_USI4>;
691 clock-names = "hsi2c";
695 hsi2c_9: i2c@12E10000 {
696 compatible = "samsung,exynos5-hsi2c";
697 reg = <0x12E10000 0x1000>;
698 interrupts = <0 88 0>;
699 #address-cells = <1>;
701 pinctrl-names = "default";
702 pinctrl-0 = <&i2c9_hs_bus>;
703 clocks = <&clock CLK_USI5>;
704 clock-names = "hsi2c";
708 hsi2c_10: i2c@12E20000 {
709 compatible = "samsung,exynos5-hsi2c";
710 reg = <0x12E20000 0x1000>;
711 interrupts = <0 203 0>;
712 #address-cells = <1>;
714 pinctrl-names = "default";
715 pinctrl-0 = <&i2c10_hs_bus>;
716 clocks = <&clock CLK_USI6>;
717 clock-names = "hsi2c";
721 hdmi: hdmi@14530000 {
722 compatible = "samsung,exynos5420-hdmi";
723 reg = <0x14530000 0x70000>;
724 interrupts = <0 95 0>;
725 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
726 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
727 <&clock CLK_MOUT_HDMI>;
728 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
729 "sclk_hdmiphy", "mout_hdmi";
731 samsung,syscon-phandle = <&pmu_system_controller>;
733 power-domains = <&disp_pd>;
736 hdmiphy: hdmiphy@145D0000 {
737 reg = <0x145D0000 0x20>;
740 mixer: mixer@14450000 {
741 compatible = "samsung,exynos5420-mixer";
742 reg = <0x14450000 0x10000>;
743 interrupts = <0 94 0>;
744 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
745 <&clock CLK_SCLK_HDMI>;
746 clock-names = "mixer", "hdmi", "sclk_hdmi";
747 power-domains = <&disp_pd>;
750 gsc_0: video-scaler@13e00000 {
751 compatible = "samsung,exynos5-gsc";
752 reg = <0x13e00000 0x1000>;
753 interrupts = <0 85 0>;
754 clocks = <&clock CLK_GSCL0>;
755 clock-names = "gscl";
756 power-domains = <&gsc_pd>;
759 gsc_1: video-scaler@13e10000 {
760 compatible = "samsung,exynos5-gsc";
761 reg = <0x13e10000 0x1000>;
762 interrupts = <0 86 0>;
763 clocks = <&clock CLK_GSCL1>;
764 clock-names = "gscl";
765 power-domains = <&gsc_pd>;
768 pmu_system_controller: system-controller@10040000 {
769 compatible = "samsung,exynos5420-pmu", "syscon";
770 reg = <0x10040000 0x5000>;
771 clock-names = "clkout16";
772 clocks = <&clock CLK_FIN_PLL>;
774 interrupt-controller;
775 #interrupt-cells = <3>;
776 interrupt-parent = <&gic>;
779 sysreg_system_controller: syscon@10050000 {
780 compatible = "samsung,exynos5-sysreg", "syscon";
781 reg = <0x10050000 0x5000>;
784 tmu_cpu0: tmu@10060000 {
785 compatible = "samsung,exynos5420-tmu";
786 reg = <0x10060000 0x100>;
787 interrupts = <0 65 0>;
788 clocks = <&clock CLK_TMU>;
789 clock-names = "tmu_apbif";
790 #include "exynos4412-tmu-sensor-conf.dtsi"
793 tmu_cpu1: tmu@10064000 {
794 compatible = "samsung,exynos5420-tmu";
795 reg = <0x10064000 0x100>;
796 interrupts = <0 183 0>;
797 clocks = <&clock CLK_TMU>;
798 clock-names = "tmu_apbif";
799 #include "exynos4412-tmu-sensor-conf.dtsi"
802 tmu_cpu2: tmu@10068000 {
803 compatible = "samsung,exynos5420-tmu-ext-triminfo";
804 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
805 interrupts = <0 184 0>;
806 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
807 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
808 #include "exynos4412-tmu-sensor-conf.dtsi"
811 tmu_cpu3: tmu@1006c000 {
812 compatible = "samsung,exynos5420-tmu-ext-triminfo";
813 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
814 interrupts = <0 185 0>;
815 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
816 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
817 #include "exynos4412-tmu-sensor-conf.dtsi"
820 tmu_gpu: tmu@100a0000 {
821 compatible = "samsung,exynos5420-tmu-ext-triminfo";
822 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
823 interrupts = <0 215 0>;
824 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
825 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
826 #include "exynos4412-tmu-sensor-conf.dtsi"
830 cpu0_thermal: cpu0-thermal {
831 thermal-sensors = <&tmu_cpu0>;
832 #include "exynos5420-trip-points.dtsi"
834 cpu1_thermal: cpu1-thermal {
835 thermal-sensors = <&tmu_cpu1>;
836 #include "exynos5420-trip-points.dtsi"
838 cpu2_thermal: cpu2-thermal {
839 thermal-sensors = <&tmu_cpu2>;
840 #include "exynos5420-trip-points.dtsi"
842 cpu3_thermal: cpu3-thermal {
843 thermal-sensors = <&tmu_cpu3>;
844 #include "exynos5420-trip-points.dtsi"
846 gpu_thermal: gpu-thermal {
847 thermal-sensors = <&tmu_gpu>;
848 #include "exynos5420-trip-points.dtsi"
852 watchdog: watchdog@101D0000 {
853 compatible = "samsung,exynos5420-wdt";
854 reg = <0x101D0000 0x100>;
855 interrupts = <0 42 0>;
856 clocks = <&clock CLK_WDT>;
857 clock-names = "watchdog";
858 samsung,syscon-phandle = <&pmu_system_controller>;
862 compatible = "samsung,exynos4210-secss";
863 reg = <0x10830000 0x10000>;
864 interrupts = <0 112 0>;
865 clocks = <&clock CLK_SSS>;
866 clock-names = "secss";
869 usbdrd3_0: usb@12000000 {
870 compatible = "samsung,exynos5250-dwusb3";
871 clocks = <&clock CLK_USBD300>;
872 clock-names = "usbdrd30";
873 #address-cells = <1>;
877 usbdrd_dwc3_0: dwc3 {
878 compatible = "snps,dwc3";
879 reg = <0x12000000 0x10000>;
880 interrupts = <0 72 0>;
881 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
882 phy-names = "usb2-phy", "usb3-phy";
886 usbdrd_phy0: phy@12100000 {
887 compatible = "samsung,exynos5420-usbdrd-phy";
888 reg = <0x12100000 0x100>;
889 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
890 clock-names = "phy", "ref";
891 samsung,pmu-syscon = <&pmu_system_controller>;
895 usbdrd3_1: usb@12400000 {
896 compatible = "samsung,exynos5250-dwusb3";
897 clocks = <&clock CLK_USBD301>;
898 clock-names = "usbdrd30";
899 #address-cells = <1>;
903 usbdrd_dwc3_1: dwc3 {
904 compatible = "snps,dwc3";
905 reg = <0x12400000 0x10000>;
906 interrupts = <0 73 0>;
907 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
908 phy-names = "usb2-phy", "usb3-phy";
912 usbdrd_phy1: phy@12500000 {
913 compatible = "samsung,exynos5420-usbdrd-phy";
914 reg = <0x12500000 0x100>;
915 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
916 clock-names = "phy", "ref";
917 samsung,pmu-syscon = <&pmu_system_controller>;
921 usbhost2: usb@12110000 {
922 compatible = "samsung,exynos4210-ehci";
923 reg = <0x12110000 0x100>;
924 interrupts = <0 71 0>;
926 clocks = <&clock CLK_USBH20>;
927 clock-names = "usbhost";
928 #address-cells = <1>;
932 phys = <&usb2_phy 1>;
936 usbhost1: usb@12120000 {
937 compatible = "samsung,exynos4210-ohci";
938 reg = <0x12120000 0x100>;
939 interrupts = <0 71 0>;
941 clocks = <&clock CLK_USBH20>;
942 clock-names = "usbhost";
943 #address-cells = <1>;
947 phys = <&usb2_phy 1>;
951 usb2_phy: phy@12130000 {
952 compatible = "samsung,exynos5250-usb2-phy";
953 reg = <0x12130000 0x100>;
954 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
955 clock-names = "phy", "ref";
957 samsung,sysreg-phandle = <&sysreg_system_controller>;
958 samsung,pmureg-phandle = <&pmu_system_controller>;