2 * SAMSUNG EXYNOS5420 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <dt-bindings/clock/exynos5420.h>
17 #include "exynos5.dtsi"
18 #include "exynos5420-pinctrl.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
23 compatible = "samsung,exynos5420", "samsung,exynos5";
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2;
32 pinctrl3 = &pinctrl_3;
33 pinctrl4 = &pinctrl_4;
50 usbdrdphy0 = &usbdrd_phy0;
51 usbdrdphy1 = &usbdrd_phy1;
60 compatible = "arm,cortex-a15";
62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>;
68 compatible = "arm,cortex-a15";
70 clock-frequency = <1800000000>;
71 cci-control-port = <&cci_control1>;
76 compatible = "arm,cortex-a15";
78 clock-frequency = <1800000000>;
79 cci-control-port = <&cci_control1>;
84 compatible = "arm,cortex-a15";
86 clock-frequency = <1800000000>;
87 cci-control-port = <&cci_control1>;
92 compatible = "arm,cortex-a7";
94 clock-frequency = <1000000000>;
95 cci-control-port = <&cci_control0>;
100 compatible = "arm,cortex-a7";
102 clock-frequency = <1000000000>;
103 cci-control-port = <&cci_control0>;
108 compatible = "arm,cortex-a7";
110 clock-frequency = <1000000000>;
111 cci-control-port = <&cci_control0>;
116 compatible = "arm,cortex-a7";
118 clock-frequency = <1000000000>;
119 cci-control-port = <&cci_control0>;
124 compatible = "arm,cci-400";
125 #address-cells = <1>;
127 reg = <0x10d20000 0x1000>;
128 ranges = <0x0 0x10d20000 0x6000>;
130 cci_control0: slave-if@4000 {
131 compatible = "arm,cci-400-ctrl-if";
132 interface-type = "ace";
133 reg = <0x4000 0x1000>;
135 cci_control1: slave-if@5000 {
136 compatible = "arm,cci-400-ctrl-if";
137 interface-type = "ace";
138 reg = <0x5000 0x1000>;
143 compatible = "mmio-sram";
144 reg = <0x02020000 0x54000>;
145 #address-cells = <1>;
147 ranges = <0 0x02020000 0x54000>;
150 compatible = "samsung,exynos4210-sysram";
155 compatible = "samsung,exynos4210-sysram-ns";
156 reg = <0x53000 0x1000>;
160 clock: clock-controller@10010000 {
161 compatible = "samsung,exynos5420-clock";
162 reg = <0x10010000 0x30000>;
166 clock_audss: audss-clock-controller@3810000 {
167 compatible = "samsung,exynos5420-audss-clock";
168 reg = <0x03810000 0x0C>;
170 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
171 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
172 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
175 mfc: codec@11000000 {
176 compatible = "samsung,mfc-v7";
177 reg = <0x11000000 0x10000>;
178 interrupts = <0 96 0>;
179 clocks = <&clock CLK_MFC>;
181 power-domains = <&mfc_pd>;
184 mmc_0: mmc@12200000 {
185 compatible = "samsung,exynos5420-dw-mshc-smu";
186 interrupts = <0 75 0>;
187 #address-cells = <1>;
189 reg = <0x12200000 0x2000>;
190 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
191 clock-names = "biu", "ciu";
196 mmc_1: mmc@12210000 {
197 compatible = "samsung,exynos5420-dw-mshc-smu";
198 interrupts = <0 76 0>;
199 #address-cells = <1>;
201 reg = <0x12210000 0x2000>;
202 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
203 clock-names = "biu", "ciu";
208 mmc_2: mmc@12220000 {
209 compatible = "samsung,exynos5420-dw-mshc";
210 interrupts = <0 77 0>;
211 #address-cells = <1>;
213 reg = <0x12220000 0x1000>;
214 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
215 clock-names = "biu", "ciu";
221 compatible = "samsung,exynos4210-mct";
222 reg = <0x101C0000 0x800>;
223 interrupt-controller;
224 #interrupt-cells = <1>;
225 interrupt-parent = <&mct_map>;
226 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
227 <8>, <9>, <10>, <11>;
228 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
229 clock-names = "fin_pll", "mct";
232 #interrupt-cells = <1>;
233 #address-cells = <0>;
235 interrupt-map = <0 &combiner 23 3>,
250 gsc_pd: power-domain@10044000 {
251 compatible = "samsung,exynos4210-pd";
252 reg = <0x10044000 0x20>;
253 #power-domain-cells = <0>;
254 clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
255 clock-names = "asb0", "asb1";
258 isp_pd: power-domain@10044020 {
259 compatible = "samsung,exynos4210-pd";
260 reg = <0x10044020 0x20>;
261 #power-domain-cells = <0>;
264 mfc_pd: power-domain@10044060 {
265 compatible = "samsung,exynos4210-pd";
266 reg = <0x10044060 0x20>;
267 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
268 <&clock CLK_MOUT_USER_ACLK333>;
269 clock-names = "oscclk", "pclk0", "clk0";
270 #power-domain-cells = <0>;
273 msc_pd: power-domain@10044120 {
274 compatible = "samsung,exynos4210-pd";
275 reg = <0x10044120 0x20>;
276 #power-domain-cells = <0>;
279 disp_pd: power-domain@100440C0 {
280 compatible = "samsung,exynos4210-pd";
281 reg = <0x100440C0 0x20>;
282 #power-domain-cells = <0>;
283 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>,
284 <&clock CLK_MOUT_USER_ACLK200_DISP1>,
285 <&clock CLK_MOUT_SW_ACLK300>,
286 <&clock CLK_MOUT_USER_ACLK300_DISP1>,
287 <&clock CLK_MOUT_SW_ACLK400>,
288 <&clock CLK_MOUT_USER_ACLK400_DISP1>,
289 <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
290 clock-names = "oscclk", "pclk0", "clk0",
291 "pclk1", "clk1", "pclk2", "clk2",
295 pinctrl_0: pinctrl@13400000 {
296 compatible = "samsung,exynos5420-pinctrl";
297 reg = <0x13400000 0x1000>;
298 interrupts = <0 45 0>;
300 wakeup-interrupt-controller {
301 compatible = "samsung,exynos4210-wakeup-eint";
302 interrupt-parent = <&gic>;
303 interrupts = <0 32 0>;
307 pinctrl_1: pinctrl@13410000 {
308 compatible = "samsung,exynos5420-pinctrl";
309 reg = <0x13410000 0x1000>;
310 interrupts = <0 78 0>;
313 pinctrl_2: pinctrl@14000000 {
314 compatible = "samsung,exynos5420-pinctrl";
315 reg = <0x14000000 0x1000>;
316 interrupts = <0 46 0>;
319 pinctrl_3: pinctrl@14010000 {
320 compatible = "samsung,exynos5420-pinctrl";
321 reg = <0x14010000 0x1000>;
322 interrupts = <0 50 0>;
325 pinctrl_4: pinctrl@03860000 {
326 compatible = "samsung,exynos5420-pinctrl";
327 reg = <0x03860000 0x1000>;
328 interrupts = <0 47 0>;
332 clocks = <&clock CLK_RTC>;
334 interrupt-parent = <&pmu_system_controller>;
339 #address-cells = <1>;
341 compatible = "arm,amba-bus";
342 interrupt-parent = <&gic>;
345 adma: adma@03880000 {
346 compatible = "arm,pl330", "arm,primecell";
347 reg = <0x03880000 0x1000>;
348 interrupts = <0 110 0>;
349 clocks = <&clock_audss EXYNOS_ADMA>;
350 clock-names = "apb_pclk";
353 #dma-requests = <16>;
356 pdma0: pdma@121A0000 {
357 compatible = "arm,pl330", "arm,primecell";
358 reg = <0x121A0000 0x1000>;
359 interrupts = <0 34 0>;
360 clocks = <&clock CLK_PDMA0>;
361 clock-names = "apb_pclk";
364 #dma-requests = <32>;
367 pdma1: pdma@121B0000 {
368 compatible = "arm,pl330", "arm,primecell";
369 reg = <0x121B0000 0x1000>;
370 interrupts = <0 35 0>;
371 clocks = <&clock CLK_PDMA1>;
372 clock-names = "apb_pclk";
375 #dma-requests = <32>;
378 mdma0: mdma@10800000 {
379 compatible = "arm,pl330", "arm,primecell";
380 reg = <0x10800000 0x1000>;
381 interrupts = <0 33 0>;
382 clocks = <&clock CLK_MDMA0>;
383 clock-names = "apb_pclk";
389 mdma1: mdma@11C10000 {
390 compatible = "arm,pl330", "arm,primecell";
391 reg = <0x11C10000 0x1000>;
392 interrupts = <0 124 0>;
393 clocks = <&clock CLK_MDMA1>;
394 clock-names = "apb_pclk";
399 * MDMA1 can support both secure and non-secure
400 * AXI transactions. When this is enabled in the kernel
401 * for boards that run in secure mode, we are getting
402 * imprecise external aborts causing the kernel to oops.
409 compatible = "samsung,exynos5420-i2s";
410 reg = <0x03830000 0x100>;
414 dma-names = "tx", "rx", "tx-sec";
415 clocks = <&clock_audss EXYNOS_I2S_BUS>,
416 <&clock_audss EXYNOS_I2S_BUS>,
417 <&clock_audss EXYNOS_SCLK_I2S>;
418 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
419 samsung,idma-addr = <0x03000000>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&i2s0_bus>;
426 compatible = "samsung,exynos5420-i2s";
427 reg = <0x12D60000 0x100>;
430 dma-names = "tx", "rx";
431 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
432 clock-names = "iis", "i2s_opclk0";
433 pinctrl-names = "default";
434 pinctrl-0 = <&i2s1_bus>;
439 compatible = "samsung,exynos5420-i2s";
440 reg = <0x12D70000 0x100>;
443 dma-names = "tx", "rx";
444 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
445 clock-names = "iis", "i2s_opclk0";
446 pinctrl-names = "default";
447 pinctrl-0 = <&i2s2_bus>;
451 spi_0: spi@12d20000 {
452 compatible = "samsung,exynos4210-spi";
453 reg = <0x12d20000 0x100>;
454 interrupts = <0 68 0>;
457 dma-names = "tx", "rx";
458 #address-cells = <1>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&spi0_bus>;
462 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
463 clock-names = "spi", "spi_busclk0";
467 spi_1: spi@12d30000 {
468 compatible = "samsung,exynos4210-spi";
469 reg = <0x12d30000 0x100>;
470 interrupts = <0 69 0>;
473 dma-names = "tx", "rx";
474 #address-cells = <1>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&spi1_bus>;
478 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
479 clock-names = "spi", "spi_busclk0";
483 spi_2: spi@12d40000 {
484 compatible = "samsung,exynos4210-spi";
485 reg = <0x12d40000 0x100>;
486 interrupts = <0 70 0>;
489 dma-names = "tx", "rx";
490 #address-cells = <1>;
492 pinctrl-names = "default";
493 pinctrl-0 = <&spi2_bus>;
494 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
495 clock-names = "spi", "spi_busclk0";
499 uart_0: serial@12C00000 {
500 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
501 clock-names = "uart", "clk_uart_baud0";
504 uart_1: serial@12C10000 {
505 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
506 clock-names = "uart", "clk_uart_baud0";
509 uart_2: serial@12C20000 {
510 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
511 clock-names = "uart", "clk_uart_baud0";
514 uart_3: serial@12C30000 {
515 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
516 clock-names = "uart", "clk_uart_baud0";
520 compatible = "samsung,exynos4210-pwm";
521 reg = <0x12dd0000 0x100>;
522 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
524 clocks = <&clock CLK_PWM>;
525 clock-names = "timers";
528 dp_phy: video-phy@10040728 {
529 compatible = "samsung,exynos5420-dp-video-phy";
530 samsung,pmu-syscon = <&pmu_system_controller>;
534 dp: dp-controller@145B0000 {
535 clocks = <&clock CLK_DP1>;
541 mipi_phy: video-phy@10040714 {
542 compatible = "samsung,s5pv210-mipi-video-phy";
543 reg = <0x10040714 12>;
548 compatible = "samsung,exynos5410-mipi-dsi";
549 reg = <0x14500000 0x10000>;
550 interrupts = <0 82 0>;
551 phys = <&mipi_phy 1>;
553 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
554 clock-names = "bus_clk", "pll_clk";
555 #address-cells = <1>;
560 fimd: fimd@14400000 {
561 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
562 clock-names = "sclk_fimd", "fimd";
563 power-domains = <&disp_pd>;
567 compatible = "samsung,exynos-adc-v2";
568 reg = <0x12D10000 0x100>;
569 interrupts = <0 106 0>;
570 clocks = <&clock CLK_TSADC>;
572 #io-channel-cells = <1>;
574 samsung,syscon-phandle = <&pmu_system_controller>;
578 i2c_0: i2c@12C60000 {
579 compatible = "samsung,s3c2440-i2c";
580 reg = <0x12C60000 0x100>;
581 interrupts = <0 56 0>;
582 #address-cells = <1>;
584 clocks = <&clock CLK_I2C0>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&i2c0_bus>;
588 samsung,sysreg-phandle = <&sysreg_system_controller>;
592 i2c_1: i2c@12C70000 {
593 compatible = "samsung,s3c2440-i2c";
594 reg = <0x12C70000 0x100>;
595 interrupts = <0 57 0>;
596 #address-cells = <1>;
598 clocks = <&clock CLK_I2C1>;
600 pinctrl-names = "default";
601 pinctrl-0 = <&i2c1_bus>;
602 samsung,sysreg-phandle = <&sysreg_system_controller>;
606 i2c_2: i2c@12C80000 {
607 compatible = "samsung,s3c2440-i2c";
608 reg = <0x12C80000 0x100>;
609 interrupts = <0 58 0>;
610 #address-cells = <1>;
612 clocks = <&clock CLK_I2C2>;
614 pinctrl-names = "default";
615 pinctrl-0 = <&i2c2_bus>;
616 samsung,sysreg-phandle = <&sysreg_system_controller>;
620 i2c_3: i2c@12C90000 {
621 compatible = "samsung,s3c2440-i2c";
622 reg = <0x12C90000 0x100>;
623 interrupts = <0 59 0>;
624 #address-cells = <1>;
626 clocks = <&clock CLK_I2C3>;
628 pinctrl-names = "default";
629 pinctrl-0 = <&i2c3_bus>;
630 samsung,sysreg-phandle = <&sysreg_system_controller>;
634 hsi2c_4: i2c@12CA0000 {
635 compatible = "samsung,exynos5-hsi2c";
636 reg = <0x12CA0000 0x1000>;
637 interrupts = <0 60 0>;
638 #address-cells = <1>;
640 pinctrl-names = "default";
641 pinctrl-0 = <&i2c4_hs_bus>;
642 clocks = <&clock CLK_USI0>;
643 clock-names = "hsi2c";
647 hsi2c_5: i2c@12CB0000 {
648 compatible = "samsung,exynos5-hsi2c";
649 reg = <0x12CB0000 0x1000>;
650 interrupts = <0 61 0>;
651 #address-cells = <1>;
653 pinctrl-names = "default";
654 pinctrl-0 = <&i2c5_hs_bus>;
655 clocks = <&clock CLK_USI1>;
656 clock-names = "hsi2c";
660 hsi2c_6: i2c@12CC0000 {
661 compatible = "samsung,exynos5-hsi2c";
662 reg = <0x12CC0000 0x1000>;
663 interrupts = <0 62 0>;
664 #address-cells = <1>;
666 pinctrl-names = "default";
667 pinctrl-0 = <&i2c6_hs_bus>;
668 clocks = <&clock CLK_USI2>;
669 clock-names = "hsi2c";
673 hsi2c_7: i2c@12CD0000 {
674 compatible = "samsung,exynos5-hsi2c";
675 reg = <0x12CD0000 0x1000>;
676 interrupts = <0 63 0>;
677 #address-cells = <1>;
679 pinctrl-names = "default";
680 pinctrl-0 = <&i2c7_hs_bus>;
681 clocks = <&clock CLK_USI3>;
682 clock-names = "hsi2c";
686 hsi2c_8: i2c@12E00000 {
687 compatible = "samsung,exynos5-hsi2c";
688 reg = <0x12E00000 0x1000>;
689 interrupts = <0 87 0>;
690 #address-cells = <1>;
692 pinctrl-names = "default";
693 pinctrl-0 = <&i2c8_hs_bus>;
694 clocks = <&clock CLK_USI4>;
695 clock-names = "hsi2c";
699 hsi2c_9: i2c@12E10000 {
700 compatible = "samsung,exynos5-hsi2c";
701 reg = <0x12E10000 0x1000>;
702 interrupts = <0 88 0>;
703 #address-cells = <1>;
705 pinctrl-names = "default";
706 pinctrl-0 = <&i2c9_hs_bus>;
707 clocks = <&clock CLK_USI5>;
708 clock-names = "hsi2c";
712 hsi2c_10: i2c@12E20000 {
713 compatible = "samsung,exynos5-hsi2c";
714 reg = <0x12E20000 0x1000>;
715 interrupts = <0 203 0>;
716 #address-cells = <1>;
718 pinctrl-names = "default";
719 pinctrl-0 = <&i2c10_hs_bus>;
720 clocks = <&clock CLK_USI6>;
721 clock-names = "hsi2c";
725 hdmi: hdmi@14530000 {
726 compatible = "samsung,exynos5420-hdmi";
727 reg = <0x14530000 0x70000>;
728 interrupts = <0 95 0>;
729 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
730 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
731 <&clock CLK_MOUT_HDMI>;
732 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
733 "sclk_hdmiphy", "mout_hdmi";
735 samsung,syscon-phandle = <&pmu_system_controller>;
737 power-domains = <&disp_pd>;
740 hdmiphy: hdmiphy@145D0000 {
741 reg = <0x145D0000 0x20>;
744 mixer: mixer@14450000 {
745 compatible = "samsung,exynos5420-mixer";
746 reg = <0x14450000 0x10000>;
747 interrupts = <0 94 0>;
748 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
749 <&clock CLK_SCLK_HDMI>;
750 clock-names = "mixer", "hdmi", "sclk_hdmi";
751 power-domains = <&disp_pd>;
754 gsc_0: video-scaler@13e00000 {
755 compatible = "samsung,exynos5-gsc";
756 reg = <0x13e00000 0x1000>;
757 interrupts = <0 85 0>;
758 clocks = <&clock CLK_GSCL0>;
759 clock-names = "gscl";
760 power-domains = <&gsc_pd>;
763 gsc_1: video-scaler@13e10000 {
764 compatible = "samsung,exynos5-gsc";
765 reg = <0x13e10000 0x1000>;
766 interrupts = <0 86 0>;
767 clocks = <&clock CLK_GSCL1>;
768 clock-names = "gscl";
769 power-domains = <&gsc_pd>;
772 pmu_system_controller: system-controller@10040000 {
773 compatible = "samsung,exynos5420-pmu", "syscon";
774 reg = <0x10040000 0x5000>;
775 clock-names = "clkout16";
776 clocks = <&clock CLK_FIN_PLL>;
778 interrupt-controller;
779 #interrupt-cells = <3>;
780 interrupt-parent = <&gic>;
783 sysreg_system_controller: syscon@10050000 {
784 compatible = "samsung,exynos5-sysreg", "syscon";
785 reg = <0x10050000 0x5000>;
788 tmu_cpu0: tmu@10060000 {
789 compatible = "samsung,exynos5420-tmu";
790 reg = <0x10060000 0x100>;
791 interrupts = <0 65 0>;
792 clocks = <&clock CLK_TMU>;
793 clock-names = "tmu_apbif";
794 #include "exynos4412-tmu-sensor-conf.dtsi"
797 tmu_cpu1: tmu@10064000 {
798 compatible = "samsung,exynos5420-tmu";
799 reg = <0x10064000 0x100>;
800 interrupts = <0 183 0>;
801 clocks = <&clock CLK_TMU>;
802 clock-names = "tmu_apbif";
803 #include "exynos4412-tmu-sensor-conf.dtsi"
806 tmu_cpu2: tmu@10068000 {
807 compatible = "samsung,exynos5420-tmu-ext-triminfo";
808 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
809 interrupts = <0 184 0>;
810 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
811 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
812 #include "exynos4412-tmu-sensor-conf.dtsi"
815 tmu_cpu3: tmu@1006c000 {
816 compatible = "samsung,exynos5420-tmu-ext-triminfo";
817 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
818 interrupts = <0 185 0>;
819 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
820 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
821 #include "exynos4412-tmu-sensor-conf.dtsi"
824 tmu_gpu: tmu@100a0000 {
825 compatible = "samsung,exynos5420-tmu-ext-triminfo";
826 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
827 interrupts = <0 215 0>;
828 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
829 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
830 #include "exynos4412-tmu-sensor-conf.dtsi"
834 cpu0_thermal: cpu0-thermal {
835 thermal-sensors = <&tmu_cpu0>;
836 #include "exynos5420-trip-points.dtsi"
838 cpu1_thermal: cpu1-thermal {
839 thermal-sensors = <&tmu_cpu1>;
840 #include "exynos5420-trip-points.dtsi"
842 cpu2_thermal: cpu2-thermal {
843 thermal-sensors = <&tmu_cpu2>;
844 #include "exynos5420-trip-points.dtsi"
846 cpu3_thermal: cpu3-thermal {
847 thermal-sensors = <&tmu_cpu3>;
848 #include "exynos5420-trip-points.dtsi"
850 gpu_thermal: gpu-thermal {
851 thermal-sensors = <&tmu_gpu>;
852 #include "exynos5420-trip-points.dtsi"
856 watchdog: watchdog@101D0000 {
857 compatible = "samsung,exynos5420-wdt";
858 reg = <0x101D0000 0x100>;
859 interrupts = <0 42 0>;
860 clocks = <&clock CLK_WDT>;
861 clock-names = "watchdog";
862 samsung,syscon-phandle = <&pmu_system_controller>;
866 compatible = "samsung,exynos4210-secss";
867 reg = <0x10830000 0x10000>;
868 interrupts = <0 112 0>;
869 clocks = <&clock CLK_SSS>;
870 clock-names = "secss";
873 usbdrd3_0: usb@12000000 {
874 compatible = "samsung,exynos5250-dwusb3";
875 clocks = <&clock CLK_USBD300>;
876 clock-names = "usbdrd30";
877 #address-cells = <1>;
881 usbdrd_dwc3_0: dwc3 {
882 compatible = "snps,dwc3";
883 reg = <0x12000000 0x10000>;
884 interrupts = <0 72 0>;
885 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
886 phy-names = "usb2-phy", "usb3-phy";
890 usbdrd_phy0: phy@12100000 {
891 compatible = "samsung,exynos5420-usbdrd-phy";
892 reg = <0x12100000 0x100>;
893 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
894 clock-names = "phy", "ref";
895 samsung,pmu-syscon = <&pmu_system_controller>;
899 usbdrd3_1: usb@12400000 {
900 compatible = "samsung,exynos5250-dwusb3";
901 clocks = <&clock CLK_USBD301>;
902 clock-names = "usbdrd30";
903 #address-cells = <1>;
907 usbdrd_dwc3_1: dwc3 {
908 compatible = "snps,dwc3";
909 reg = <0x12400000 0x10000>;
910 interrupts = <0 73 0>;
911 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
912 phy-names = "usb2-phy", "usb3-phy";
916 usbdrd_phy1: phy@12500000 {
917 compatible = "samsung,exynos5420-usbdrd-phy";
918 reg = <0x12500000 0x100>;
919 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
920 clock-names = "phy", "ref";
921 samsung,pmu-syscon = <&pmu_system_controller>;
925 usbhost2: usb@12110000 {
926 compatible = "samsung,exynos4210-ehci";
927 reg = <0x12110000 0x100>;
928 interrupts = <0 71 0>;
930 clocks = <&clock CLK_USBH20>;
931 clock-names = "usbhost";
932 #address-cells = <1>;
936 phys = <&usb2_phy 1>;
940 usbhost1: usb@12120000 {
941 compatible = "samsung,exynos4210-ohci";
942 reg = <0x12120000 0x100>;
943 interrupts = <0 71 0>;
945 clocks = <&clock CLK_USBH20>;
946 clock-names = "usbhost";
947 #address-cells = <1>;
951 phys = <&usb2_phy 1>;
955 usb2_phy: phy@12130000 {
956 compatible = "samsung,exynos5250-usb2-phy";
957 reg = <0x12130000 0x100>;
958 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
959 clock-names = "phy", "ref";
961 samsung,sysreg-phandle = <&sysreg_system_controller>;
962 samsung,pmureg-phandle = <&pmu_system_controller>;