arch/arm/boot/dts/exynos5260.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5260 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include "skeleton.dtsi"
  13
  14 #include <dt-bindings/clock/exynos5260-clk.h>
  15
  16 / {
  17         compatible = "samsung,exynos5260", "samsung,exynos5";
  18         interrupt-parent = <&gic>;
  19
  20         aliases {
  21                 pinctrl0 = &pinctrl_0;
  22                 pinctrl1 = &pinctrl_1;
  23                 pinctrl2 = &pinctrl_2;
  24                 serial0 = &uart0;
  25                 serial1 = &uart1;
  26                 serial2 = &uart2;
  27                 serial3 = &uart3;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a15";
  37                         reg = <0x0>;
  38                         cci-control-port = <&cci_control1>;
  39                 };
  40
  41                 cpu@1 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x1>;
  45                         cci-control-port = <&cci_control1>;
  46                 };
  47
  48                 cpu@100 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a7";
  51                         reg = <0x100>;
  52                         cci-control-port = <&cci_control0>;
  53                 };
  54
  55                 cpu@101 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a7";
  58                         reg = <0x101>;
  59                         cci-control-port = <&cci_control0>;
  60                 };
  61
  62                 cpu@102 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a7";
  65                         reg = <0x102>;
  66                         cci-control-port = <&cci_control0>;
  67                 };
  68
  69                 cpu@103 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a7";
  72                         reg = <0x103>;
  73                         cci-control-port = <&cci_control0>;
  74                 };
  75         };
  76
  77         soc: soc {
  78                 compatible = "simple-bus";
  79                 #address-cells = <1>;
  80                 #size-cells = <1>;
  81                 ranges;
  82
  83                 clock_top: clock-controller@10010000 {
  84                         compatible = "samsung,exynos5260-clock-top";
  85                         reg = <0x10010000 0x10000>;
  86                         #clock-cells = <1>;
  87                 };
  88
  89                 clock_peri: clock-controller@10200000 {
  90                         compatible = "samsung,exynos5260-clock-peri";
  91                         reg = <0x10200000 0x10000>;
  92                         #clock-cells = <1>;
  93                 };
  94
  95                 clock_egl: clock-controller@10600000 {
  96                         compatible = "samsung,exynos5260-clock-egl";
  97                         reg = <0x10600000 0x10000>;
  98                         #clock-cells = <1>;
  99                 };
 100
 101                 clock_kfc: clock-controller@10700000 {
 102                         compatible = "samsung,exynos5260-clock-kfc";
 103                         reg = <0x10700000 0x10000>;
 104                         #clock-cells = <1>;
 105                 };
 106
 107                 clock_g2d: clock-controller@10A00000 {
 108                         compatible = "samsung,exynos5260-clock-g2d";
 109                         reg = <0x10A00000 0x10000>;
 110                         #clock-cells = <1>;
 111                 };
 112
 113                 clock_mif: clock-controller@10CE0000 {
 114                         compatible = "samsung,exynos5260-clock-mif";
 115                         reg = <0x10CE0000 0x10000>;
 116                         #clock-cells = <1>;
 117                 };
 118
 119                 clock_mfc: clock-controller@11090000 {
 120                         compatible = "samsung,exynos5260-clock-mfc";
 121                         reg = <0x11090000 0x10000>;
 122                         #clock-cells = <1>;
 123                 };
 124
 125                 clock_g3d: clock-controller@11830000 {
 126                         compatible = "samsung,exynos5260-clock-g3d";
 127                         reg = <0x11830000 0x10000>;
 128                         #clock-cells = <1>;
 129                 };
 130
 131                 clock_fsys: clock-controller@122E0000 {
 132                         compatible = "samsung,exynos5260-clock-fsys";
 133                         reg = <0x122E0000 0x10000>;
 134                         #clock-cells = <1>;
 135                 };
 136
 137                 clock_aud: clock-controller@128C0000 {
 138                         compatible = "samsung,exynos5260-clock-aud";
 139                         reg = <0x128C0000 0x10000>;
 140                         #clock-cells = <1>;
 141                 };
 142
 143                 clock_isp: clock-controller@133C0000 {
 144                         compatible = "samsung,exynos5260-clock-isp";
 145                         reg = <0x133C0000 0x10000>;
 146                         #clock-cells = <1>;
 147                 };
 148
 149                 clock_gscl: clock-controller@13F00000 {
 150                         compatible = "samsung,exynos5260-clock-gscl";
 151                         reg = <0x13F00000 0x10000>;
 152                         #clock-cells = <1>;
 153                 };
 154
 155                 clock_disp: clock-controller@14550000 {
 156                         compatible = "samsung,exynos5260-clock-disp";
 157                         reg = <0x14550000 0x10000>;
 158                         #clock-cells = <1>;
 159                 };
 160
 161                 gic: interrupt-controller@10481000 {
 162                         compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 163                         #interrupt-cells = <3>;
 164                         #address-cells = <0>;
 165                         #size-cells = <0>;
 166                         interrupt-controller;
 167                         reg = <0x10481000 0x1000>,
 168                                 <0x10482000 0x1000>,
 169                                 <0x10484000 0x2000>,
 170                                 <0x10486000 0x2000>;
 171                         interrupts = <1 9 0xf04>;
 172                 };
 173
 174                 chipid: chipid@10000000 {
 175                         compatible = "samsung,exynos4210-chipid";
 176                         reg = <0x10000000 0x100>;
 177                 };
 178
 179                 mct: mct@100B0000 {
 180                         compatible = "samsung,exynos4210-mct";
 181                         reg = <0x100B0000 0x1000>;
 182                         clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
 183                         clock-names = "fin_pll", "mct";
 184                         interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
 185                                         <0 107 0>, <0 122 0>, <0 123 0>,
 186                                         <0 124 0>, <0 125 0>, <0 126 0>,
 187                                         <0 127 0>, <0 128 0>, <0 129 0>;
 188                 };
 189
 190                 cci: cci@10F00000 {
 191                         compatible = "arm,cci-400";
 192                         #address-cells = <1>;
 193                         #size-cells = <1>;
 194                         reg = <0x10F00000 0x1000>;
 195                         ranges = <0x0 0x10F00000 0x6000>;
 196
 197                         cci_control0: slave-if@4000 {
 198                                 compatible = "arm,cci-400-ctrl-if";
 199                                 interface-type = "ace";
 200                                 reg = <0x4000 0x1000>;
 201                         };
 202
 203                         cci_control1: slave-if@5000 {
 204                                 compatible = "arm,cci-400-ctrl-if";
 205                                 interface-type = "ace";
 206                                 reg = <0x5000 0x1000>;
 207                         };
 208                 };
 209
 210                 pinctrl_0: pinctrl@11600000 {
 211                         compatible = "samsung,exynos5260-pinctrl";
 212                         reg = <0x11600000 0x1000>;
 213                         interrupts = <0 79 0>;
 214
 215                         wakeup-interrupt-controller {
 216                                 compatible = "samsung,exynos4210-wakeup-eint";
 217                                 interrupt-parent = <&gic>;
 218                                 interrupts = <0 32 0>;
 219                         };
 220                 };
 221
 222                 pinctrl_1: pinctrl@12290000 {
 223                         compatible = "samsung,exynos5260-pinctrl";
 224                         reg = <0x12290000 0x1000>;
 225                         interrupts = <0 157 0>;
 226                 };
 227
 228                 pinctrl_2: pinctrl@128B0000 {
 229                         compatible = "samsung,exynos5260-pinctrl";
 230                         reg = <0x128B0000 0x1000>;
 231                         interrupts = <0 243 0>;
 232                 };
 233
 234                 uart0: serial@12C00000 {
 235                         compatible = "samsung,exynos4210-uart";
 236                         reg = <0x12C00000 0x100>;
 237                         interrupts = <0 146 0>;
 238                         clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
 239                         clock-names = "uart", "clk_uart_baud0";
 240                         status = "disabled";
 241                 };
 242
 243                 uart1: serial@12C10000 {
 244                         compatible = "samsung,exynos4210-uart";
 245                         reg = <0x12C10000 0x100>;
 246                         interrupts = <0 147 0>;
 247                         clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
 248                         clock-names = "uart", "clk_uart_baud0";
 249                         status = "disabled";
 250                 };
 251
 252                 uart2: serial@12C20000 {
 253                         compatible = "samsung,exynos4210-uart";
 254                         reg = <0x12C20000 0x100>;
 255                         interrupts = <0 148 0>;
 256                         clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
 257                         clock-names = "uart", "clk_uart_baud0";
 258                         status = "disabled";
 259                 };
 260
 261                 uart3: serial@12860000 {
 262                         compatible = "samsung,exynos4210-uart";
 263                         reg = <0x12860000 0x100>;
 264                         interrupts = <0 145 0>;
 265                         clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
 266                         clock-names = "uart", "clk_uart_baud0";
 267                         status = "disabled";
 268                 };
 269
 270                 mmc_0: mmc@12140000 {
 271                         compatible = "samsung,exynos5250-dw-mshc";
 272                         reg = <0x12140000 0x2000>;
 273                         interrupts = <0 156 0>;
 274                         #address-cells = <1>;
 275                         #size-cells = <0>;
 276                         clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
 277                         clock-names = "biu", "ciu";
 278                         fifo-depth = <64>;
 279                         status = "disabled";
 280                 };
 281
 282                 mmc_1: mmc@12150000 {
 283                         compatible = "samsung,exynos5250-dw-mshc";
 284                         reg = <0x12150000 0x2000>;
 285                         interrupts = <0 158 0>;
 286                         #address-cells = <1>;
 287                         #size-cells = <0>;
 288                         clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
 289                         clock-names = "biu", "ciu";
 290                         fifo-depth = <64>;
 291                         status = "disabled";
 292                 };
 293
 294                 mmc_2: mmc@12160000 {
 295                         compatible = "samsung,exynos5250-dw-mshc";
 296                         reg = <0x12160000 0x2000>;
 297                         interrupts = <0 159 0>;
 298                         #address-cells = <1>;
 299                         #size-cells = <0>;
 300                         clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
 301                         clock-names = "biu", "ciu";
 302                         fifo-depth = <64>;
 303                         status = "disabled";
 304                 };
 305         };
 306 };
 307
 308 #include "exynos5260-pinctrl.dtsi"