arch/arm/boot/dts/exynos5250.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5250 SoC device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
   8  * EXYNOS5250 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
  13  * additional nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include <dt-bindings/clock/exynos5250.h>
  21 #include "exynos5.dtsi"
  22 #include "exynos4-cpu-thermal.dtsi"
  23 #include <dt-bindings/clock/exynos-audss-clk.h>
  24
  25 / {
  26         compatible = "samsung,exynos5250", "samsung,exynos5";
  27
  28         aliases {
  29                 spi0 = &spi_0;
  30                 spi1 = &spi_1;
  31                 spi2 = &spi_2;
  32                 gsc0 = &gsc_0;
  33                 gsc1 = &gsc_1;
  34                 gsc2 = &gsc_2;
  35                 gsc3 = &gsc_3;
  36                 mshc0 = &mmc_0;
  37                 mshc1 = &mmc_1;
  38                 mshc2 = &mmc_2;
  39                 mshc3 = &mmc_3;
  40                 i2c0 = &i2c_0;
  41                 i2c1 = &i2c_1;
  42                 i2c2 = &i2c_2;
  43                 i2c3 = &i2c_3;
  44                 i2c4 = &i2c_4;
  45                 i2c5 = &i2c_5;
  46                 i2c6 = &i2c_6;
  47                 i2c7 = &i2c_7;
  48                 i2c8 = &i2c_8;
  49                 i2c9 = &i2c_9;
  50                 pinctrl0 = &pinctrl_0;
  51                 pinctrl1 = &pinctrl_1;
  52                 pinctrl2 = &pinctrl_2;
  53                 pinctrl3 = &pinctrl_3;
  54         };
  55
  56         cpus {
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 cpu0: cpu@0 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a15";
  63                         reg = <0>;
  64                         clock-frequency = <1700000000>;
  65                         cooling-min-level = <15>;
  66                         cooling-max-level = <9>;
  67                         #cooling-cells = <2>; /* min followed by max */
  68                 };
  69                 cpu@1 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a15";
  72                         reg = <1>;
  73                         clock-frequency = <1700000000>;
  74                 };
  75         };
  76
  77         sysram@02020000 {
  78                 compatible = "mmio-sram";
  79                 reg = <0x02020000 0x30000>;
  80                 #address-cells = <1>;
  81                 #size-cells = <1>;
  82                 ranges = <0 0x02020000 0x30000>;
  83
  84                 smp-sysram@0 {
  85                         compatible = "samsung,exynos4210-sysram";
  86                         reg = <0x0 0x1000>;
  87                 };
  88
  89                 smp-sysram@2f000 {
  90                         compatible = "samsung,exynos4210-sysram-ns";
  91                         reg = <0x2f000 0x1000>;
  92                 };
  93         };
  94
  95         pd_gsc: gsc-power-domain@10044000 {
  96                 compatible = "samsung,exynos4210-pd";
  97                 reg = <0x10044000 0x20>;
  98                 #power-domain-cells = <0>;
  99         };
 100
 101         pd_mfc: mfc-power-domain@10044040 {
 102                 compatible = "samsung,exynos4210-pd";
 103                 reg = <0x10044040 0x20>;
 104                 #power-domain-cells = <0>;
 105         };
 106
 107         pd_disp1: disp1-power-domain@100440A0 {
 108                 compatible = "samsung,exynos4210-pd";
 109                 reg = <0x100440A0 0x20>;
 110                 #power-domain-cells = <0>;
 111         };
 112
 113         clock: clock-controller@10010000 {
 114                 compatible = "samsung,exynos5250-clock";
 115                 reg = <0x10010000 0x30000>;
 116                 #clock-cells = <1>;
 117         };
 118
 119         clock_audss: audss-clock-controller@3810000 {
 120                 compatible = "samsung,exynos5250-audss-clock";
 121                 reg = <0x03810000 0x0C>;
 122                 #clock-cells = <1>;
 123                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
 124                          <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
 125                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 126         };
 127
 128         timer {
 129                 compatible = "arm,armv7-timer";
 130                 interrupts = <1 13 0xf08>,
 131                              <1 14 0xf08>,
 132                              <1 11 0xf08>,
 133                              <1 10 0xf08>;
 134                 /* Unfortunately we need this since some versions of U-Boot
 135                  * on Exynos don't set the CNTFRQ register, so we need the
 136                  * value from DT.
 137                  */
 138                 clock-frequency = <24000000>;
 139         };
 140
 141         mct@101C0000 {
 142                 compatible = "samsung,exynos4210-mct";
 143                 reg = <0x101C0000 0x800>;
 144                 interrupt-controller;
 145                 #interrupt-cells = <2>;
 146                 interrupt-parent = <&mct_map>;
 147                 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
 148                              <4 0>, <5 0>;
 149                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 150                 clock-names = "fin_pll", "mct";
 151
 152                 mct_map: mct-map {
 153                         #interrupt-cells = <2>;
 154                         #address-cells = <0>;
 155                         #size-cells = <0>;
 156                         interrupt-map = <0x0 0 &combiner 23 3>,
 157                                         <0x1 0 &combiner 23 4>,
 158                                         <0x2 0 &combiner 25 2>,
 159                                         <0x3 0 &combiner 25 3>,
 160                                         <0x4 0 &gic 0 120 0>,
 161                                         <0x5 0 &gic 0 121 0>;
 162                 };
 163         };
 164
 165         pmu {
 166                 compatible = "arm,cortex-a15-pmu";
 167                 interrupt-parent = <&combiner>;
 168                 interrupts = <1 2>, <22 4>;
 169         };
 170
 171         pinctrl_0: pinctrl@11400000 {
 172                 compatible = "samsung,exynos5250-pinctrl";
 173                 reg = <0x11400000 0x1000>;
 174                 interrupts = <0 46 0>;
 175
 176                 wakup_eint: wakeup-interrupt-controller {
 177                         compatible = "samsung,exynos4210-wakeup-eint";
 178                         interrupt-parent = <&gic>;
 179                         interrupts = <0 32 0>;
 180                 };
 181         };
 182
 183         pinctrl_1: pinctrl@13400000 {
 184                 compatible = "samsung,exynos5250-pinctrl";
 185                 reg = <0x13400000 0x1000>;
 186                 interrupts = <0 45 0>;
 187         };
 188
 189         pinctrl_2: pinctrl@10d10000 {
 190                 compatible = "samsung,exynos5250-pinctrl";
 191                 reg = <0x10d10000 0x1000>;
 192                 interrupts = <0 50 0>;
 193         };
 194
 195         pinctrl_3: pinctrl@03860000 {
 196                 compatible = "samsung,exynos5250-pinctrl";
 197                 reg = <0x03860000 0x1000>;
 198                 interrupts = <0 47 0>;
 199         };
 200
 201         pmu_system_controller: system-controller@10040000 {
 202                 compatible = "samsung,exynos5250-pmu", "syscon";
 203                 reg = <0x10040000 0x5000>;
 204                 clock-names = "clkout16";
 205                 clocks = <&clock CLK_FIN_PLL>;
 206                 #clock-cells = <1>;
 207                 interrupt-controller;
 208                 #interrupt-cells = <3>;
 209                 interrupt-parent = <&gic>;
 210         };
 211
 212         sysreg_system_controller: syscon@10050000 {
 213                 compatible = "samsung,exynos5-sysreg", "syscon";
 214                 reg = <0x10050000 0x5000>;
 215         };
 216
 217         watchdog@101D0000 {
 218                 compatible = "samsung,exynos5250-wdt";
 219                 reg = <0x101D0000 0x100>;
 220                 interrupts = <0 42 0>;
 221                 clocks = <&clock CLK_WDT>;
 222                 clock-names = "watchdog";
 223                 samsung,syscon-phandle = <&pmu_system_controller>;
 224         };
 225
 226         g2d@10850000 {
 227                 compatible = "samsung,exynos5250-g2d";
 228                 reg = <0x10850000 0x1000>;
 229                 interrupts = <0 91 0>;
 230                 clocks = <&clock CLK_G2D>;
 231                 clock-names = "fimg2d";
 232                 iommus = <&sysmmu_g2d>;
 233         };
 234
 235         mfc: codec@11000000 {
 236                 compatible = "samsung,mfc-v6";
 237                 reg = <0x11000000 0x10000>;
 238                 interrupts = <0 96 0>;
 239                 power-domains = <&pd_mfc>;
 240                 clocks = <&clock CLK_MFC>;
 241                 clock-names = "mfc";
 242                 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 243                 iommu-names = "left", "right";
 244         };
 245
 246         tmu: tmu@10060000 {
 247                 compatible = "samsung,exynos5250-tmu";
 248                 reg = <0x10060000 0x100>;
 249                 interrupts = <0 65 0>;
 250                 clocks = <&clock CLK_TMU>;
 251                 clock-names = "tmu_apbif";
 252                 #include "exynos4412-tmu-sensor-conf.dtsi"
 253         };
 254
 255         thermal-zones {
 256                 cpu_thermal: cpu-thermal {
 257                         polling-delay-passive = <0>;
 258                         polling-delay = <0>;
 259                         thermal-sensors = <&tmu 0>;
 260
 261                         cooling-maps {
 262                                 map0 {
 263                                      /* Corresponds to 800MHz at freq_table */
 264                                      cooling-device = <&cpu0 9 9>;
 265                                 };
 266                                 map1 {
 267                                      /* Corresponds to 200MHz at freq_table */
 268                                      cooling-device = <&cpu0 15 15>;
 269                                };
 270                        };
 271                 };
 272         };
 273
 274         sata: sata@122F0000 {
 275                 compatible = "snps,dwc-ahci";
 276                 samsung,sata-freq = <66>;
 277                 reg = <0x122F0000 0x1ff>;
 278                 interrupts = <0 115 0>;
 279                 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
 280                 clock-names = "sata", "sclk_sata";
 281                 phys = <&sata_phy>;
 282                 phy-names = "sata-phy";
 283                 status = "disabled";
 284         };
 285
 286         sata_phy: sata-phy@12170000 {
 287                 compatible = "samsung,exynos5250-sata-phy";
 288                 reg = <0x12170000 0x1ff>;
 289                 clocks = <&clock CLK_SATA_PHYCTRL>;
 290                 clock-names = "sata_phyctrl";
 291                 #phy-cells = <0>;
 292                 samsung,syscon-phandle = <&pmu_system_controller>;
 293                 status = "disabled";
 294         };
 295
 296         i2c_0: i2c@12C60000 {
 297                 compatible = "samsung,s3c2440-i2c";
 298                 reg = <0x12C60000 0x100>;
 299                 interrupts = <0 56 0>;
 300                 #address-cells = <1>;
 301                 #size-cells = <0>;
 302                 clocks = <&clock CLK_I2C0>;
 303                 clock-names = "i2c";
 304                 pinctrl-names = "default";
 305                 pinctrl-0 = <&i2c0_bus>;
 306                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 307                 status = "disabled";
 308         };
 309
 310         i2c_1: i2c@12C70000 {
 311                 compatible = "samsung,s3c2440-i2c";
 312                 reg = <0x12C70000 0x100>;
 313                 interrupts = <0 57 0>;
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316                 clocks = <&clock CLK_I2C1>;
 317                 clock-names = "i2c";
 318                 pinctrl-names = "default";
 319                 pinctrl-0 = <&i2c1_bus>;
 320                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 321                 status = "disabled";
 322         };
 323
 324         i2c_2: i2c@12C80000 {
 325                 compatible = "samsung,s3c2440-i2c";
 326                 reg = <0x12C80000 0x100>;
 327                 interrupts = <0 58 0>;
 328                 #address-cells = <1>;
 329                 #size-cells = <0>;
 330                 clocks = <&clock CLK_I2C2>;
 331                 clock-names = "i2c";
 332                 pinctrl-names = "default";
 333                 pinctrl-0 = <&i2c2_bus>;
 334                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 335                 status = "disabled";
 336         };
 337
 338         i2c_3: i2c@12C90000 {
 339                 compatible = "samsung,s3c2440-i2c";
 340                 reg = <0x12C90000 0x100>;
 341                 interrupts = <0 59 0>;
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344                 clocks = <&clock CLK_I2C3>;
 345                 clock-names = "i2c";
 346                 pinctrl-names = "default";
 347                 pinctrl-0 = <&i2c3_bus>;
 348                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 349                 status = "disabled";
 350         };
 351
 352         i2c_4: i2c@12CA0000 {
 353                 compatible = "samsung,s3c2440-i2c";
 354                 reg = <0x12CA0000 0x100>;
 355                 interrupts = <0 60 0>;
 356                 #address-cells = <1>;
 357                 #size-cells = <0>;
 358                 clocks = <&clock CLK_I2C4>;
 359                 clock-names = "i2c";
 360                 pinctrl-names = "default";
 361                 pinctrl-0 = <&i2c4_bus>;
 362                 status = "disabled";
 363         };
 364
 365         i2c_5: i2c@12CB0000 {
 366                 compatible = "samsung,s3c2440-i2c";
 367                 reg = <0x12CB0000 0x100>;
 368                 interrupts = <0 61 0>;
 369                 #address-cells = <1>;
 370                 #size-cells = <0>;
 371                 clocks = <&clock CLK_I2C5>;
 372                 clock-names = "i2c";
 373                 pinctrl-names = "default";
 374                 pinctrl-0 = <&i2c5_bus>;
 375                 status = "disabled";
 376         };
 377
 378         i2c_6: i2c@12CC0000 {
 379                 compatible = "samsung,s3c2440-i2c";
 380                 reg = <0x12CC0000 0x100>;
 381                 interrupts = <0 62 0>;
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 clocks = <&clock CLK_I2C6>;
 385                 clock-names = "i2c";
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&i2c6_bus>;
 388                 status = "disabled";
 389         };
 390
 391         i2c_7: i2c@12CD0000 {
 392                 compatible = "samsung,s3c2440-i2c";
 393                 reg = <0x12CD0000 0x100>;
 394                 interrupts = <0 63 0>;
 395                 #address-cells = <1>;
 396                 #size-cells = <0>;
 397                 clocks = <&clock CLK_I2C7>;
 398                 clock-names = "i2c";
 399                 pinctrl-names = "default";
 400                 pinctrl-0 = <&i2c7_bus>;
 401                 status = "disabled";
 402         };
 403
 404         i2c_8: i2c@12CE0000 {
 405                 compatible = "samsung,s3c2440-hdmiphy-i2c";
 406                 reg = <0x12CE0000 0x1000>;
 407                 interrupts = <0 64 0>;
 408                 #address-cells = <1>;
 409                 #size-cells = <0>;
 410                 clocks = <&clock CLK_I2C_HDMI>;
 411                 clock-names = "i2c";
 412                 status = "disabled";
 413         };
 414
 415         i2c_9: i2c@121D0000 {
 416                 compatible = "samsung,exynos5-sata-phy-i2c";
 417                 reg = <0x121D0000 0x100>;
 418                 #address-cells = <1>;
 419                 #size-cells = <0>;
 420                 clocks = <&clock CLK_SATA_PHYI2C>;
 421                 clock-names = "i2c";
 422                 status = "disabled";
 423         };
 424
 425         spi_0: spi@12d20000 {
 426                 compatible = "samsung,exynos4210-spi";
 427                 status = "disabled";
 428                 reg = <0x12d20000 0x100>;
 429                 interrupts = <0 66 0>;
 430                 dmas = <&pdma0 5
 431                         &pdma0 4>;
 432                 dma-names = "tx", "rx";
 433                 #address-cells = <1>;
 434                 #size-cells = <0>;
 435                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 436                 clock-names = "spi", "spi_busclk0";
 437                 pinctrl-names = "default";
 438                 pinctrl-0 = <&spi0_bus>;
 439         };
 440
 441         spi_1: spi@12d30000 {
 442                 compatible = "samsung,exynos4210-spi";
 443                 status = "disabled";
 444                 reg = <0x12d30000 0x100>;
 445                 interrupts = <0 67 0>;
 446                 dmas = <&pdma1 5
 447                         &pdma1 4>;
 448                 dma-names = "tx", "rx";
 449                 #address-cells = <1>;
 450                 #size-cells = <0>;
 451                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 452                 clock-names = "spi", "spi_busclk0";
 453                 pinctrl-names = "default";
 454                 pinctrl-0 = <&spi1_bus>;
 455         };
 456
 457         spi_2: spi@12d40000 {
 458                 compatible = "samsung,exynos4210-spi";
 459                 status = "disabled";
 460                 reg = <0x12d40000 0x100>;
 461                 interrupts = <0 68 0>;
 462                 dmas = <&pdma0 7
 463                         &pdma0 6>;
 464                 dma-names = "tx", "rx";
 465                 #address-cells = <1>;
 466                 #size-cells = <0>;
 467                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 468                 clock-names = "spi", "spi_busclk0";
 469                 pinctrl-names = "default";
 470                 pinctrl-0 = <&spi2_bus>;
 471         };
 472
 473         mmc_0: mmc@12200000 {
 474                 compatible = "samsung,exynos5250-dw-mshc";
 475                 interrupts = <0 75 0>;
 476                 #address-cells = <1>;
 477                 #size-cells = <0>;
 478                 reg = <0x12200000 0x1000>;
 479                 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 480                 clock-names = "biu", "ciu";
 481                 fifo-depth = <0x80>;
 482                 status = "disabled";
 483         };
 484
 485         mmc_1: mmc@12210000 {
 486                 compatible = "samsung,exynos5250-dw-mshc";
 487                 interrupts = <0 76 0>;
 488                 #address-cells = <1>;
 489                 #size-cells = <0>;
 490                 reg = <0x12210000 0x1000>;
 491                 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 492                 clock-names = "biu", "ciu";
 493                 fifo-depth = <0x80>;
 494                 status = "disabled";
 495         };
 496
 497         mmc_2: mmc@12220000 {
 498                 compatible = "samsung,exynos5250-dw-mshc";
 499                 interrupts = <0 77 0>;
 500                 #address-cells = <1>;
 501                 #size-cells = <0>;
 502                 reg = <0x12220000 0x1000>;
 503                 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 504                 clock-names = "biu", "ciu";
 505                 fifo-depth = <0x80>;
 506                 status = "disabled";
 507         };
 508
 509         mmc_3: mmc@12230000 {
 510                 compatible = "samsung,exynos5250-dw-mshc";
 511                 reg = <0x12230000 0x1000>;
 512                 interrupts = <0 78 0>;
 513                 #address-cells = <1>;
 514                 #size-cells = <0>;
 515                 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 516                 clock-names = "biu", "ciu";
 517                 fifo-depth = <0x80>;
 518                 status = "disabled";
 519         };
 520
 521         i2s0: i2s@03830000 {
 522                 compatible = "samsung,s5pv210-i2s";
 523                 status = "disabled";
 524                 reg = <0x03830000 0x100>;
 525                 dmas = <&pdma0 10
 526                         &pdma0 9
 527                         &pdma0 8>;
 528                 dma-names = "tx", "rx", "tx-sec";
 529                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 530                         <&clock_audss EXYNOS_I2S_BUS>,
 531                         <&clock_audss EXYNOS_SCLK_I2S>;
 532                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 533                 samsung,idma-addr = <0x03000000>;
 534                 pinctrl-names = "default";
 535                 pinctrl-0 = <&i2s0_bus>;
 536         };
 537
 538         i2s1: i2s@12D60000 {
 539                 compatible = "samsung,s3c6410-i2s";
 540                 status = "disabled";
 541                 reg = <0x12D60000 0x100>;
 542                 dmas = <&pdma1 12
 543                         &pdma1 11>;
 544                 dma-names = "tx", "rx";
 545                 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
 546                 clock-names = "iis", "i2s_opclk0";
 547                 pinctrl-names = "default";
 548                 pinctrl-0 = <&i2s1_bus>;
 549         };
 550
 551         i2s2: i2s@12D70000 {
 552                 compatible = "samsung,s3c6410-i2s";
 553                 status = "disabled";
 554                 reg = <0x12D70000 0x100>;
 555                 dmas = <&pdma0 12
 556                         &pdma0 11>;
 557                 dma-names = "tx", "rx";
 558                 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
 559                 clock-names = "iis", "i2s_opclk0";
 560                 pinctrl-names = "default";
 561                 pinctrl-0 = <&i2s2_bus>;
 562         };
 563
 564         usb@12000000 {
 565                 compatible = "samsung,exynos5250-dwusb3";
 566                 clocks = <&clock CLK_USB3>;
 567                 clock-names = "usbdrd30";
 568                 #address-cells = <1>;
 569                 #size-cells = <1>;
 570                 ranges;
 571
 572                 usbdrd_dwc3: dwc3 {
 573                         compatible = "synopsys,dwc3";
 574                         reg = <0x12000000 0x10000>;
 575                         interrupts = <0 72 0>;
 576                         phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
 577                         phy-names = "usb2-phy", "usb3-phy";
 578                 };
 579         };
 580
 581         usbdrd_phy: phy@12100000 {
 582                 compatible = "samsung,exynos5250-usbdrd-phy";
 583                 reg = <0x12100000 0x100>;
 584                 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
 585                 clock-names = "phy", "ref";
 586                 samsung,pmu-syscon = <&pmu_system_controller>;
 587                 #phy-cells = <1>;
 588         };
 589
 590         ehci: usb@12110000 {
 591                 compatible = "samsung,exynos4210-ehci";
 592                 reg = <0x12110000 0x100>;
 593                 interrupts = <0 71 0>;
 594
 595                 clocks = <&clock CLK_USB2>;
 596                 clock-names = "usbhost";
 597                 #address-cells = <1>;
 598                 #size-cells = <0>;
 599                 port@0 {
 600                         reg = <0>;
 601                         phys = <&usb2_phy_gen 1>;
 602                 };
 603         };
 604
 605         ohci: usb@12120000 {
 606                 compatible = "samsung,exynos4210-ohci";
 607                 reg = <0x12120000 0x100>;
 608                 interrupts = <0 71 0>;
 609
 610                 clocks = <&clock CLK_USB2>;
 611                 clock-names = "usbhost";
 612                 #address-cells = <1>;
 613                 #size-cells = <0>;
 614                 port@0 {
 615                         reg = <0>;
 616                         phys = <&usb2_phy_gen 1>;
 617                 };
 618         };
 619
 620         usb2_phy_gen: phy@12130000 {
 621                 compatible = "samsung,exynos5250-usb2-phy";
 622                 reg = <0x12130000 0x100>;
 623                 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
 624                 clock-names = "phy", "ref";
 625                 #phy-cells = <1>;
 626                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 627                 samsung,pmureg-phandle = <&pmu_system_controller>;
 628         };
 629
 630         pwm: pwm@12dd0000 {
 631                 compatible = "samsung,exynos4210-pwm";
 632                 reg = <0x12dd0000 0x100>;
 633                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 634                 #pwm-cells = <3>;
 635                 clocks = <&clock CLK_PWM>;
 636                 clock-names = "timers";
 637         };
 638
 639         amba {
 640                 #address-cells = <1>;
 641                 #size-cells = <1>;
 642                 compatible = "arm,amba-bus";
 643                 interrupt-parent = <&gic>;
 644                 ranges;
 645
 646                 pdma0: pdma@121A0000 {
 647                         compatible = "arm,pl330", "arm,primecell";
 648                         reg = <0x121A0000 0x1000>;
 649                         interrupts = <0 34 0>;
 650                         clocks = <&clock CLK_PDMA0>;
 651                         clock-names = "apb_pclk";
 652                         #dma-cells = <1>;
 653                         #dma-channels = <8>;
 654                         #dma-requests = <32>;
 655                 };
 656
 657                 pdma1: pdma@121B0000 {
 658                         compatible = "arm,pl330", "arm,primecell";
 659                         reg = <0x121B0000 0x1000>;
 660                         interrupts = <0 35 0>;
 661                         clocks = <&clock CLK_PDMA1>;
 662                         clock-names = "apb_pclk";
 663                         #dma-cells = <1>;
 664                         #dma-channels = <8>;
 665                         #dma-requests = <32>;
 666                 };
 667
 668                 mdma0: mdma@10800000 {
 669                         compatible = "arm,pl330", "arm,primecell";
 670                         reg = <0x10800000 0x1000>;
 671                         interrupts = <0 33 0>;
 672                         clocks = <&clock CLK_MDMA0>;
 673                         clock-names = "apb_pclk";
 674                         #dma-cells = <1>;
 675                         #dma-channels = <8>;
 676                         #dma-requests = <1>;
 677                 };
 678
 679                 mdma1: mdma@11C10000 {
 680                         compatible = "arm,pl330", "arm,primecell";
 681                         reg = <0x11C10000 0x1000>;
 682                         interrupts = <0 124 0>;
 683                         clocks = <&clock CLK_MDMA1>;
 684                         clock-names = "apb_pclk";
 685                         #dma-cells = <1>;
 686                         #dma-channels = <8>;
 687                         #dma-requests = <1>;
 688                 };
 689         };
 690
 691         gsc_0:  gsc@13e00000 {
 692                 compatible = "samsung,exynos5-gsc";
 693                 reg = <0x13e00000 0x1000>;
 694                 interrupts = <0 85 0>;
 695                 power-domains = <&pd_gsc>;
 696                 clocks = <&clock CLK_GSCL0>;
 697                 clock-names = "gscl";
 698                 iommu = <&sysmmu_gsc0>;
 699         };
 700
 701         gsc_1:  gsc@13e10000 {
 702                 compatible = "samsung,exynos5-gsc";
 703                 reg = <0x13e10000 0x1000>;
 704                 interrupts = <0 86 0>;
 705                 power-domains = <&pd_gsc>;
 706                 clocks = <&clock CLK_GSCL1>;
 707                 clock-names = "gscl";
 708                 iommu = <&sysmmu_gsc1>;
 709         };
 710
 711         gsc_2:  gsc@13e20000 {
 712                 compatible = "samsung,exynos5-gsc";
 713                 reg = <0x13e20000 0x1000>;
 714                 interrupts = <0 87 0>;
 715                 power-domains = <&pd_gsc>;
 716                 clocks = <&clock CLK_GSCL2>;
 717                 clock-names = "gscl";
 718                 iommu = <&sysmmu_gsc2>;
 719         };
 720
 721         gsc_3:  gsc@13e30000 {
 722                 compatible = "samsung,exynos5-gsc";
 723                 reg = <0x13e30000 0x1000>;
 724                 interrupts = <0 88 0>;
 725                 power-domains = <&pd_gsc>;
 726                 clocks = <&clock CLK_GSCL3>;
 727                 clock-names = "gscl";
 728                 iommu = <&sysmmu_gsc3>;
 729         };
 730
 731         hdmi: hdmi {
 732                 compatible = "samsung,exynos4212-hdmi";
 733                 reg = <0x14530000 0x70000>;
 734                 power-domains = <&pd_disp1>;
 735                 interrupts = <0 95 0>;
 736                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 737                          <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 738                          <&clock CLK_MOUT_HDMI>;
 739                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 740                                 "sclk_hdmiphy", "mout_hdmi";
 741                 samsung,syscon-phandle = <&pmu_system_controller>;
 742         };
 743
 744         mixer {
 745                 compatible = "samsung,exynos5250-mixer";
 746                 reg = <0x14450000 0x10000>;
 747                 power-domains = <&pd_disp1>;
 748                 interrupts = <0 94 0>;
 749                 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 750                          <&clock CLK_SCLK_HDMI>;
 751                 clock-names = "mixer", "hdmi", "sclk_hdmi";
 752                 iommus = <&sysmmu_tv>;
 753         };
 754
 755         dp_phy: video-phy@10040720 {
 756                 compatible = "samsung,exynos5250-dp-video-phy";
 757                 samsung,pmu-syscon = <&pmu_system_controller>;
 758                 #phy-cells = <0>;
 759         };
 760
 761         adc: adc@12D10000 {
 762                 compatible = "samsung,exynos-adc-v1";
 763                 reg = <0x12D10000 0x100>;
 764                 interrupts = <0 106 0>;
 765                 clocks = <&clock CLK_ADC>;
 766                 clock-names = "adc";
 767                 #io-channel-cells = <1>;
 768                 io-channel-ranges;
 769                 samsung,syscon-phandle = <&pmu_system_controller>;
 770                 status = "disabled";
 771         };
 772
 773         sss@10830000 {
 774                 compatible = "samsung,exynos4210-secss";
 775                 reg = <0x10830000 0x10000>;
 776                 interrupts = <0 112 0>;
 777                 clocks = <&clock CLK_SSS>;
 778                 clock-names = "secss";
 779         };
 780
 781         sysmmu_g2d: sysmmu@10A60000 {
 782                 compatible = "samsung,exynos-sysmmu";
 783                 reg = <0x10A60000 0x1000>;
 784                 interrupt-parent = <&combiner>;
 785                 interrupts = <24 5>;
 786                 clock-names = "sysmmu", "master";
 787                 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
 788                 #iommu-cells = <0>;
 789         };
 790
 791         sysmmu_mfc_r: sysmmu@11200000 {
 792                 compatible = "samsung,exynos-sysmmu";
 793                 reg = <0x11200000 0x1000>;
 794                 interrupt-parent = <&combiner>;
 795                 interrupts = <6 2>;
 796                 power-domains = <&pd_mfc>;
 797                 clock-names = "sysmmu", "master";
 798                 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
 799                 #iommu-cells = <0>;
 800         };
 801
 802         sysmmu_mfc_l: sysmmu@11210000 {
 803                 compatible = "samsung,exynos-sysmmu";
 804                 reg = <0x11210000 0x1000>;
 805                 interrupt-parent = <&combiner>;
 806                 interrupts = <8 5>;
 807                 power-domains = <&pd_mfc>;
 808                 clock-names = "sysmmu", "master";
 809                 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
 810                 #iommu-cells = <0>;
 811         };
 812
 813         sysmmu_rotator: sysmmu@11D40000 {
 814                 compatible = "samsung,exynos-sysmmu";
 815                 reg = <0x11D40000 0x1000>;
 816                 interrupt-parent = <&combiner>;
 817                 interrupts = <4 0>;
 818                 clock-names = "sysmmu", "master";
 819                 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
 820                 #iommu-cells = <0>;
 821         };
 822
 823         sysmmu_jpeg: sysmmu@11F20000 {
 824                 compatible = "samsung,exynos-sysmmu";
 825                 reg = <0x11F20000 0x1000>;
 826                 interrupt-parent = <&combiner>;
 827                 interrupts = <4 2>;
 828                 power-domains = <&pd_gsc>;
 829                 clock-names = "sysmmu", "master";
 830                 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
 831                 #iommu-cells = <0>;
 832         };
 833
 834         sysmmu_fimc_isp: sysmmu@13260000 {
 835                 compatible = "samsung,exynos-sysmmu";
 836                 reg = <0x13260000 0x1000>;
 837                 interrupt-parent = <&combiner>;
 838                 interrupts = <10 6>;
 839                 clock-names = "sysmmu";
 840                 clocks = <&clock CLK_SMMU_FIMC_ISP>;
 841                 #iommu-cells = <0>;
 842         };
 843
 844         sysmmu_fimc_drc: sysmmu@13270000 {
 845                 compatible = "samsung,exynos-sysmmu";
 846                 reg = <0x13270000 0x1000>;
 847                 interrupt-parent = <&combiner>;
 848                 interrupts = <11 6>;
 849                 clock-names = "sysmmu";
 850                 clocks = <&clock CLK_SMMU_FIMC_DRC>;
 851                 #iommu-cells = <0>;
 852         };
 853
 854         sysmmu_fimc_fd: sysmmu@132A0000 {
 855                 compatible = "samsung,exynos-sysmmu";
 856                 reg = <0x132A0000 0x1000>;
 857                 interrupt-parent = <&combiner>;
 858                 interrupts = <5 0>;
 859                 clock-names = "sysmmu";
 860                 clocks = <&clock CLK_SMMU_FIMC_FD>;
 861                 #iommu-cells = <0>;
 862         };
 863
 864         sysmmu_fimc_scc: sysmmu@13280000 {
 865                 compatible = "samsung,exynos-sysmmu";
 866                 reg = <0x13280000 0x1000>;
 867                 interrupt-parent = <&combiner>;
 868                 interrupts = <5 2>;
 869                 clock-names = "sysmmu";
 870                 clocks = <&clock CLK_SMMU_FIMC_SCC>;
 871                 #iommu-cells = <0>;
 872         };
 873
 874         sysmmu_fimc_scp: sysmmu@13290000 {
 875                 compatible = "samsung,exynos-sysmmu";
 876                 reg = <0x13290000 0x1000>;
 877                 interrupt-parent = <&combiner>;
 878                 interrupts = <3 6>;
 879                 clock-names = "sysmmu";
 880                 clocks = <&clock CLK_SMMU_FIMC_SCP>;
 881                 #iommu-cells = <0>;
 882         };
 883
 884         sysmmu_fimc_mcuctl: sysmmu@132B0000 {
 885                 compatible = "samsung,exynos-sysmmu";
 886                 reg = <0x132B0000 0x1000>;
 887                 interrupt-parent = <&combiner>;
 888                 interrupts = <5 4>;
 889                 clock-names = "sysmmu";
 890                 clocks = <&clock CLK_SMMU_FIMC_MCU>;
 891                 #iommu-cells = <0>;
 892         };
 893
 894         sysmmu_fimc_odc: sysmmu@132C0000 {
 895                 compatible = "samsung,exynos-sysmmu";
 896                 reg = <0x132C0000 0x1000>;
 897                 interrupt-parent = <&combiner>;
 898                 interrupts = <11 0>;
 899                 clock-names = "sysmmu";
 900                 clocks = <&clock CLK_SMMU_FIMC_ODC>;
 901                 #iommu-cells = <0>;
 902         };
 903
 904         sysmmu_fimc_dis0: sysmmu@132D0000 {
 905                 compatible = "samsung,exynos-sysmmu";
 906                 reg = <0x132D0000 0x1000>;
 907                 interrupt-parent = <&combiner>;
 908                 interrupts = <10 4>;
 909                 clock-names = "sysmmu";
 910                 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
 911                 #iommu-cells = <0>;
 912         };
 913
 914         sysmmu_fimc_dis1: sysmmu@132E0000{
 915                 compatible = "samsung,exynos-sysmmu";
 916                 reg = <0x132E0000 0x1000>;
 917                 interrupt-parent = <&combiner>;
 918                 interrupts = <9 4>;
 919                 clock-names = "sysmmu";
 920                 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
 921                 #iommu-cells = <0>;
 922         };
 923
 924         sysmmu_fimc_3dnr: sysmmu@132F0000 {
 925                 compatible = "samsung,exynos-sysmmu";
 926                 reg = <0x132F0000 0x1000>;
 927                 interrupt-parent = <&combiner>;
 928                 interrupts = <5 6>;
 929                 clock-names = "sysmmu";
 930                 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
 931                 #iommu-cells = <0>;
 932         };
 933
 934         sysmmu_fimc_lite0: sysmmu@13C40000 {
 935                 compatible = "samsung,exynos-sysmmu";
 936                 reg = <0x13C40000 0x1000>;
 937                 interrupt-parent = <&combiner>;
 938                 interrupts = <3 4>;
 939                 power-domains = <&pd_gsc>;
 940                 clock-names = "sysmmu", "master";
 941                 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
 942                 #iommu-cells = <0>;
 943         };
 944
 945         sysmmu_fimc_lite1: sysmmu@13C50000 {
 946                 compatible = "samsung,exynos-sysmmu";
 947                 reg = <0x13C50000 0x1000>;
 948                 interrupt-parent = <&combiner>;
 949                 interrupts = <24 1>;
 950                 power-domains = <&pd_gsc>;
 951                 clock-names = "sysmmu", "master";
 952                 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
 953                 #iommu-cells = <0>;
 954         };
 955
 956         sysmmu_gsc0: sysmmu@13E80000 {
 957                 compatible = "samsung,exynos-sysmmu";
 958                 reg = <0x13E80000 0x1000>;
 959                 interrupt-parent = <&combiner>;
 960                 interrupts = <2 0>;
 961                 power-domains = <&pd_gsc>;
 962                 clock-names = "sysmmu", "master";
 963                 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
 964                 #iommu-cells = <0>;
 965         };
 966
 967         sysmmu_gsc1: sysmmu@13E90000 {
 968                 compatible = "samsung,exynos-sysmmu";
 969                 reg = <0x13E90000 0x1000>;
 970                 interrupt-parent = <&combiner>;
 971                 interrupts = <2 2>;
 972                 power-domains = <&pd_gsc>;
 973                 clock-names = "sysmmu", "master";
 974                 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
 975                 #iommu-cells = <0>;
 976         };
 977
 978         sysmmu_gsc2: sysmmu@13EA0000 {
 979                 compatible = "samsung,exynos-sysmmu";
 980                 reg = <0x13EA0000 0x1000>;
 981                 interrupt-parent = <&combiner>;
 982                 interrupts = <2 4>;
 983                 power-domains = <&pd_gsc>;
 984                 clock-names = "sysmmu", "master";
 985                 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
 986                 #iommu-cells = <0>;
 987         };
 988
 989         sysmmu_gsc3: sysmmu@13EB0000 {
 990                 compatible = "samsung,exynos-sysmmu";
 991                 reg = <0x13EB0000 0x1000>;
 992                 interrupt-parent = <&combiner>;
 993                 interrupts = <2 6>;
 994                 power-domains = <&pd_gsc>;
 995                 clock-names = "sysmmu", "master";
 996                 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
 997                 #iommu-cells = <0>;
 998         };
 999
1000         sysmmu_fimd1: sysmmu@14640000 {
1001                 compatible = "samsung,exynos-sysmmu";
1002                 reg = <0x14640000 0x1000>;
1003                 interrupt-parent = <&combiner>;
1004                 interrupts = <3 2>;
1005                 power-domains = <&pd_disp1>;
1006                 clock-names = "sysmmu", "master";
1007                 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1008                 #iommu-cells = <0>;
1009         };
1010
1011         sysmmu_tv: sysmmu@14650000 {
1012                 compatible = "samsung,exynos-sysmmu";
1013                 reg = <0x14650000 0x1000>;
1014                 interrupt-parent = <&combiner>;
1015                 interrupts = <7 4>;
1016                 power-domains = <&pd_disp1>;
1017                 clock-names = "sysmmu", "master";
1018                 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1019                 #iommu-cells = <0>;
1020         };
1021 };
1022
1023 &dp {
1024         power-domains = <&pd_disp1>;
1025         clocks = <&clock CLK_DP>;
1026         clock-names = "dp";
1027         phys = <&dp_phy>;
1028         phy-names = "dp";
1029 };
1030
1031 &fimd {
1032         power-domains = <&pd_disp1>;
1033         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1034         clock-names = "sclk_fimd", "fimd";
1035         iommus = <&sysmmu_fimd1>;
1036 };
1037
1038 &rtc {
1039         clocks = <&clock CLK_RTC>;
1040         clock-names = "rtc";
1041         interrupt-parent = <&pmu_system_controller>;
1042         status = "disabled";
1043 };
1044
1045 &serial_0 {
1046         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1047         clock-names = "uart", "clk_uart_baud0";
1048 };
1049
1050 &serial_1 {
1051         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1052         clock-names = "uart", "clk_uart_baud0";
1053 };
1054
1055 &serial_2 {
1056         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1057         clock-names = "uart", "clk_uart_baud0";
1058 };
1059
1060 &serial_3 {
1061         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1062         clock-names = "uart", "clk_uart_baud0";
1063 };
1064
1065 #include "exynos5250-pinctrl.dtsi"