2 * SAMSUNG EXYNOS5250 SoC device tree source
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <dt-bindings/clock/exynos5250.h>
21 #include "exynos5.dtsi"
22 #include "exynos5250-pinctrl.dtsi"
24 #include <dt-bindings/clock/exynos-audss-clk.h>
27 compatible = "samsung,exynos5250", "samsung,exynos5";
51 pinctrl0 = &pinctrl_0;
52 pinctrl1 = &pinctrl_1;
53 pinctrl2 = &pinctrl_2;
54 pinctrl3 = &pinctrl_3;
63 compatible = "arm,cortex-a15";
65 clock-frequency = <1700000000>;
69 compatible = "arm,cortex-a15";
71 clock-frequency = <1700000000>;
76 compatible = "mmio-sram";
77 reg = <0x02020000 0x30000>;
80 ranges = <0 0x02020000 0x30000>;
83 compatible = "samsung,exynos4210-sysram";
88 compatible = "samsung,exynos4210-sysram-ns";
89 reg = <0x2f000 0x1000>;
93 pd_gsc: gsc-power-domain@10044000 {
94 compatible = "samsung,exynos4210-pd";
95 reg = <0x10044000 0x20>;
96 #power-domain-cells = <0>;
99 pd_mfc: mfc-power-domain@10044040 {
100 compatible = "samsung,exynos4210-pd";
101 reg = <0x10044040 0x20>;
102 #power-domain-cells = <0>;
105 clock: clock-controller@10010000 {
106 compatible = "samsung,exynos5250-clock";
107 reg = <0x10010000 0x30000>;
111 clock_audss: audss-clock-controller@3810000 {
112 compatible = "samsung,exynos5250-audss-clock";
113 reg = <0x03810000 0x0C>;
115 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
116 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
117 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
121 compatible = "arm,armv7-timer";
122 interrupts = <1 13 0xf08>,
126 /* Unfortunately we need this since some versions of U-Boot
127 * on Exynos don't set the CNTFRQ register, so we need the
130 clock-frequency = <24000000>;
134 compatible = "samsung,exynos4210-mct";
135 reg = <0x101C0000 0x800>;
136 interrupt-controller;
137 #interrups-cells = <2>;
138 interrupt-parent = <&mct_map>;
139 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
141 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
142 clock-names = "fin_pll", "mct";
145 #interrupt-cells = <2>;
146 #address-cells = <0>;
148 interrupt-map = <0x0 0 &combiner 23 3>,
149 <0x1 0 &combiner 23 4>,
150 <0x2 0 &combiner 25 2>,
151 <0x3 0 &combiner 25 3>,
152 <0x4 0 &gic 0 120 0>,
153 <0x5 0 &gic 0 121 0>;
158 compatible = "arm,cortex-a15-pmu";
159 interrupt-parent = <&combiner>;
160 interrupts = <1 2>, <22 4>;
163 pinctrl_0: pinctrl@11400000 {
164 compatible = "samsung,exynos5250-pinctrl";
165 reg = <0x11400000 0x1000>;
166 interrupts = <0 46 0>;
168 wakup_eint: wakeup-interrupt-controller {
169 compatible = "samsung,exynos4210-wakeup-eint";
170 interrupt-parent = <&gic>;
171 interrupts = <0 32 0>;
175 pinctrl_1: pinctrl@13400000 {
176 compatible = "samsung,exynos5250-pinctrl";
177 reg = <0x13400000 0x1000>;
178 interrupts = <0 45 0>;
181 pinctrl_2: pinctrl@10d10000 {
182 compatible = "samsung,exynos5250-pinctrl";
183 reg = <0x10d10000 0x1000>;
184 interrupts = <0 50 0>;
187 pinctrl_3: pinctrl@03860000 {
188 compatible = "samsung,exynos5250-pinctrl";
189 reg = <0x03860000 0x1000>;
190 interrupts = <0 47 0>;
193 pmu_system_controller: system-controller@10040000 {
194 compatible = "samsung,exynos5250-pmu", "syscon";
195 reg = <0x10040000 0x5000>;
196 clock-names = "clkout16";
197 clocks = <&clock CLK_FIN_PLL>;
201 sysreg_system_controller: syscon@10050000 {
202 compatible = "samsung,exynos5-sysreg", "syscon";
203 reg = <0x10050000 0x5000>;
207 compatible = "samsung,exynos5250-wdt";
208 reg = <0x101D0000 0x100>;
209 interrupts = <0 42 0>;
210 clocks = <&clock CLK_WDT>;
211 clock-names = "watchdog";
212 samsung,syscon-phandle = <&pmu_system_controller>;
216 compatible = "samsung,exynos5250-g2d";
217 reg = <0x10850000 0x1000>;
218 interrupts = <0 91 0>;
219 clocks = <&clock CLK_G2D>;
220 clock-names = "fimg2d";
223 mfc: codec@11000000 {
224 compatible = "samsung,mfc-v6";
225 reg = <0x11000000 0x10000>;
226 interrupts = <0 96 0>;
227 power-domains = <&pd_mfc>;
228 clocks = <&clock CLK_MFC>;
233 clocks = <&clock CLK_RTC>;
239 compatible = "samsung,exynos5250-tmu";
240 reg = <0x10060000 0x100>;
241 interrupts = <0 65 0>;
242 clocks = <&clock CLK_TMU>;
243 clock-names = "tmu_apbif";
247 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
248 clock-names = "uart", "clk_uart_baud0";
252 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
253 clock-names = "uart", "clk_uart_baud0";
257 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
258 clock-names = "uart", "clk_uart_baud0";
262 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
263 clock-names = "uart", "clk_uart_baud0";
266 sata: sata@122F0000 {
267 compatible = "snps,dwc-ahci";
268 samsung,sata-freq = <66>;
269 reg = <0x122F0000 0x1ff>;
270 interrupts = <0 115 0>;
271 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
272 clock-names = "sata", "sclk_sata";
274 phy-names = "sata-phy";
278 sata_phy: sata-phy@12170000 {
279 compatible = "samsung,exynos5250-sata-phy";
280 reg = <0x12170000 0x1ff>;
281 clocks = <&clock CLK_SATA_PHYCTRL>;
282 clock-names = "sata_phyctrl";
284 samsung,syscon-phandle = <&pmu_system_controller>;
288 i2c_0: i2c@12C60000 {
289 compatible = "samsung,s3c2440-i2c";
290 reg = <0x12C60000 0x100>;
291 interrupts = <0 56 0>;
292 #address-cells = <1>;
294 clocks = <&clock CLK_I2C0>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&i2c0_bus>;
298 samsung,sysreg-phandle = <&sysreg_system_controller>;
302 i2c_1: i2c@12C70000 {
303 compatible = "samsung,s3c2440-i2c";
304 reg = <0x12C70000 0x100>;
305 interrupts = <0 57 0>;
306 #address-cells = <1>;
308 clocks = <&clock CLK_I2C1>;
310 pinctrl-names = "default";
311 pinctrl-0 = <&i2c1_bus>;
312 samsung,sysreg-phandle = <&sysreg_system_controller>;
316 i2c_2: i2c@12C80000 {
317 compatible = "samsung,s3c2440-i2c";
318 reg = <0x12C80000 0x100>;
319 interrupts = <0 58 0>;
320 #address-cells = <1>;
322 clocks = <&clock CLK_I2C2>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&i2c2_bus>;
326 samsung,sysreg-phandle = <&sysreg_system_controller>;
330 i2c_3: i2c@12C90000 {
331 compatible = "samsung,s3c2440-i2c";
332 reg = <0x12C90000 0x100>;
333 interrupts = <0 59 0>;
334 #address-cells = <1>;
336 clocks = <&clock CLK_I2C3>;
338 pinctrl-names = "default";
339 pinctrl-0 = <&i2c3_bus>;
340 samsung,sysreg-phandle = <&sysreg_system_controller>;
344 i2c_4: i2c@12CA0000 {
345 compatible = "samsung,s3c2440-i2c";
346 reg = <0x12CA0000 0x100>;
347 interrupts = <0 60 0>;
348 #address-cells = <1>;
350 clocks = <&clock CLK_I2C4>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&i2c4_bus>;
357 i2c_5: i2c@12CB0000 {
358 compatible = "samsung,s3c2440-i2c";
359 reg = <0x12CB0000 0x100>;
360 interrupts = <0 61 0>;
361 #address-cells = <1>;
363 clocks = <&clock CLK_I2C5>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&i2c5_bus>;
370 i2c_6: i2c@12CC0000 {
371 compatible = "samsung,s3c2440-i2c";
372 reg = <0x12CC0000 0x100>;
373 interrupts = <0 62 0>;
374 #address-cells = <1>;
376 clocks = <&clock CLK_I2C6>;
378 pinctrl-names = "default";
379 pinctrl-0 = <&i2c6_bus>;
383 i2c_7: i2c@12CD0000 {
384 compatible = "samsung,s3c2440-i2c";
385 reg = <0x12CD0000 0x100>;
386 interrupts = <0 63 0>;
387 #address-cells = <1>;
389 clocks = <&clock CLK_I2C7>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&i2c7_bus>;
396 i2c_8: i2c@12CE0000 {
397 compatible = "samsung,s3c2440-hdmiphy-i2c";
398 reg = <0x12CE0000 0x1000>;
399 interrupts = <0 64 0>;
400 #address-cells = <1>;
402 clocks = <&clock CLK_I2C_HDMI>;
407 i2c_9: i2c@121D0000 {
408 compatible = "samsung,exynos5-sata-phy-i2c";
409 reg = <0x121D0000 0x100>;
410 #address-cells = <1>;
412 clocks = <&clock CLK_SATA_PHYI2C>;
417 spi_0: spi@12d20000 {
418 compatible = "samsung,exynos4210-spi";
420 reg = <0x12d20000 0x100>;
421 interrupts = <0 66 0>;
424 dma-names = "tx", "rx";
425 #address-cells = <1>;
427 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
428 clock-names = "spi", "spi_busclk0";
429 pinctrl-names = "default";
430 pinctrl-0 = <&spi0_bus>;
433 spi_1: spi@12d30000 {
434 compatible = "samsung,exynos4210-spi";
436 reg = <0x12d30000 0x100>;
437 interrupts = <0 67 0>;
440 dma-names = "tx", "rx";
441 #address-cells = <1>;
443 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
444 clock-names = "spi", "spi_busclk0";
445 pinctrl-names = "default";
446 pinctrl-0 = <&spi1_bus>;
449 spi_2: spi@12d40000 {
450 compatible = "samsung,exynos4210-spi";
452 reg = <0x12d40000 0x100>;
453 interrupts = <0 68 0>;
456 dma-names = "tx", "rx";
457 #address-cells = <1>;
459 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
460 clock-names = "spi", "spi_busclk0";
461 pinctrl-names = "default";
462 pinctrl-0 = <&spi2_bus>;
465 mmc_0: mmc@12200000 {
466 compatible = "samsung,exynos5250-dw-mshc";
467 interrupts = <0 75 0>;
468 #address-cells = <1>;
470 reg = <0x12200000 0x1000>;
471 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
472 clock-names = "biu", "ciu";
477 mmc_1: mmc@12210000 {
478 compatible = "samsung,exynos5250-dw-mshc";
479 interrupts = <0 76 0>;
480 #address-cells = <1>;
482 reg = <0x12210000 0x1000>;
483 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
484 clock-names = "biu", "ciu";
489 mmc_2: mmc@12220000 {
490 compatible = "samsung,exynos5250-dw-mshc";
491 interrupts = <0 77 0>;
492 #address-cells = <1>;
494 reg = <0x12220000 0x1000>;
495 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
496 clock-names = "biu", "ciu";
501 mmc_3: mmc@12230000 {
502 compatible = "samsung,exynos5250-dw-mshc";
503 reg = <0x12230000 0x1000>;
504 interrupts = <0 78 0>;
505 #address-cells = <1>;
507 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
508 clock-names = "biu", "ciu";
514 compatible = "samsung,s5pv210-i2s";
516 reg = <0x03830000 0x100>;
520 dma-names = "tx", "rx", "tx-sec";
521 clocks = <&clock_audss EXYNOS_I2S_BUS>,
522 <&clock_audss EXYNOS_I2S_BUS>,
523 <&clock_audss EXYNOS_SCLK_I2S>;
524 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
525 samsung,idma-addr = <0x03000000>;
526 pinctrl-names = "default";
527 pinctrl-0 = <&i2s0_bus>;
531 compatible = "samsung,s3c6410-i2s";
533 reg = <0x12D60000 0x100>;
536 dma-names = "tx", "rx";
537 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
538 clock-names = "iis", "i2s_opclk0";
539 pinctrl-names = "default";
540 pinctrl-0 = <&i2s1_bus>;
544 compatible = "samsung,s3c6410-i2s";
546 reg = <0x12D70000 0x100>;
549 dma-names = "tx", "rx";
550 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
551 clock-names = "iis", "i2s_opclk0";
552 pinctrl-names = "default";
553 pinctrl-0 = <&i2s2_bus>;
557 compatible = "samsung,exynos5250-dwusb3";
558 clocks = <&clock CLK_USB3>;
559 clock-names = "usbdrd30";
560 #address-cells = <1>;
565 compatible = "synopsys,dwc3";
566 reg = <0x12000000 0x10000>;
567 interrupts = <0 72 0>;
568 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
569 phy-names = "usb2-phy", "usb3-phy";
573 usbdrd_phy: phy@12100000 {
574 compatible = "samsung,exynos5250-usbdrd-phy";
575 reg = <0x12100000 0x100>;
576 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
577 clock-names = "phy", "ref";
578 samsung,pmu-syscon = <&pmu_system_controller>;
583 compatible = "samsung,exynos4210-ehci";
584 reg = <0x12110000 0x100>;
585 interrupts = <0 71 0>;
587 clocks = <&clock CLK_USB2>;
588 clock-names = "usbhost";
589 #address-cells = <1>;
593 phys = <&usb2_phy_gen 1>;
598 compatible = "samsung,exynos4210-ohci";
599 reg = <0x12120000 0x100>;
600 interrupts = <0 71 0>;
602 clocks = <&clock CLK_USB2>;
603 clock-names = "usbhost";
604 #address-cells = <1>;
608 phys = <&usb2_phy_gen 1>;
612 usb2_phy_gen: phy@12130000 {
613 compatible = "samsung,exynos5250-usb2-phy";
614 reg = <0x12130000 0x100>;
615 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
616 clock-names = "phy", "ref";
618 samsung,sysreg-phandle = <&sysreg_system_controller>;
619 samsung,pmureg-phandle = <&pmu_system_controller>;
623 compatible = "samsung,exynos4210-pwm";
624 reg = <0x12dd0000 0x100>;
625 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
627 clocks = <&clock CLK_PWM>;
628 clock-names = "timers";
632 #address-cells = <1>;
634 compatible = "arm,amba-bus";
635 interrupt-parent = <&gic>;
638 pdma0: pdma@121A0000 {
639 compatible = "arm,pl330", "arm,primecell";
640 reg = <0x121A0000 0x1000>;
641 interrupts = <0 34 0>;
642 clocks = <&clock CLK_PDMA0>;
643 clock-names = "apb_pclk";
646 #dma-requests = <32>;
649 pdma1: pdma@121B0000 {
650 compatible = "arm,pl330", "arm,primecell";
651 reg = <0x121B0000 0x1000>;
652 interrupts = <0 35 0>;
653 clocks = <&clock CLK_PDMA1>;
654 clock-names = "apb_pclk";
657 #dma-requests = <32>;
660 mdma0: mdma@10800000 {
661 compatible = "arm,pl330", "arm,primecell";
662 reg = <0x10800000 0x1000>;
663 interrupts = <0 33 0>;
664 clocks = <&clock CLK_MDMA0>;
665 clock-names = "apb_pclk";
671 mdma1: mdma@11C10000 {
672 compatible = "arm,pl330", "arm,primecell";
673 reg = <0x11C10000 0x1000>;
674 interrupts = <0 124 0>;
675 clocks = <&clock CLK_MDMA1>;
676 clock-names = "apb_pclk";
683 gsc_0: gsc@13e00000 {
684 compatible = "samsung,exynos5-gsc";
685 reg = <0x13e00000 0x1000>;
686 interrupts = <0 85 0>;
687 power-domains = <&pd_gsc>;
688 clocks = <&clock CLK_GSCL0>;
689 clock-names = "gscl";
692 gsc_1: gsc@13e10000 {
693 compatible = "samsung,exynos5-gsc";
694 reg = <0x13e10000 0x1000>;
695 interrupts = <0 86 0>;
696 power-domains = <&pd_gsc>;
697 clocks = <&clock CLK_GSCL1>;
698 clock-names = "gscl";
701 gsc_2: gsc@13e20000 {
702 compatible = "samsung,exynos5-gsc";
703 reg = <0x13e20000 0x1000>;
704 interrupts = <0 87 0>;
705 power-domains = <&pd_gsc>;
706 clocks = <&clock CLK_GSCL2>;
707 clock-names = "gscl";
710 gsc_3: gsc@13e30000 {
711 compatible = "samsung,exynos5-gsc";
712 reg = <0x13e30000 0x1000>;
713 interrupts = <0 88 0>;
714 power-domains = <&pd_gsc>;
715 clocks = <&clock CLK_GSCL3>;
716 clock-names = "gscl";
720 compatible = "samsung,exynos4212-hdmi";
721 reg = <0x14530000 0x70000>;
722 interrupts = <0 95 0>;
723 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
724 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
725 <&clock CLK_MOUT_HDMI>;
726 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
727 "sclk_hdmiphy", "mout_hdmi";
728 samsung,syscon-phandle = <&pmu_system_controller>;
732 compatible = "samsung,exynos5250-mixer";
733 reg = <0x14450000 0x10000>;
734 interrupts = <0 94 0>;
735 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
736 clock-names = "mixer", "sclk_hdmi";
739 dp_phy: video-phy@10040720 {
740 compatible = "samsung,exynos5250-dp-video-phy";
741 samsung,pmu-syscon = <&pmu_system_controller>;
745 dp: dp-controller@145B0000 {
746 clocks = <&clock CLK_DP>;
752 fimd: fimd@14400000 {
753 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
754 clock-names = "sclk_fimd", "fimd";
758 compatible = "samsung,exynos-adc-v1";
759 reg = <0x12D10000 0x100>;
760 interrupts = <0 106 0>;
761 clocks = <&clock CLK_ADC>;
763 #io-channel-cells = <1>;
765 samsung,syscon-phandle = <&pmu_system_controller>;
770 compatible = "samsung,exynos4210-secss";
771 reg = <0x10830000 0x10000>;
772 interrupts = <0 112 0>;
773 clocks = <&clock CLK_SSS>;
774 clock-names = "secss";