arch/arm/boot/dts/exynos5250.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5250 SoC device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
   8  * EXYNOS5250 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
  13  * additional nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include <dt-bindings/clock/exynos5250.h>
  21 #include "exynos5.dtsi"
  22 #include "exynos5250-pinctrl.dtsi"
  23
  24 #include <dt-bindings/clock/exynos-audss-clk.h>
  25
  26 / {
  27         compatible = "samsung,exynos5250", "samsung,exynos5";
  28
  29         aliases {
  30                 spi0 = &spi_0;
  31                 spi1 = &spi_1;
  32                 spi2 = &spi_2;
  33                 gsc0 = &gsc_0;
  34                 gsc1 = &gsc_1;
  35                 gsc2 = &gsc_2;
  36                 gsc3 = &gsc_3;
  37                 mshc0 = &mmc_0;
  38                 mshc1 = &mmc_1;
  39                 mshc2 = &mmc_2;
  40                 mshc3 = &mmc_3;
  41                 i2c0 = &i2c_0;
  42                 i2c1 = &i2c_1;
  43                 i2c2 = &i2c_2;
  44                 i2c3 = &i2c_3;
  45                 i2c4 = &i2c_4;
  46                 i2c5 = &i2c_5;
  47                 i2c6 = &i2c_6;
  48                 i2c7 = &i2c_7;
  49                 i2c8 = &i2c_8;
  50                 i2c9 = &i2c_9;
  51                 pinctrl0 = &pinctrl_0;
  52                 pinctrl1 = &pinctrl_1;
  53                 pinctrl2 = &pinctrl_2;
  54                 pinctrl3 = &pinctrl_3;
  55         };
  56
  57         cpus {
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60
  61                 cpu@0 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a15";
  64                         reg = <0>;
  65                         clock-frequency = <1700000000>;
  66                 };
  67                 cpu@1 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a15";
  70                         reg = <1>;
  71                         clock-frequency = <1700000000>;
  72                 };
  73         };
  74
  75         sysram@02020000 {
  76                 compatible = "mmio-sram";
  77                 reg = <0x02020000 0x30000>;
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80                 ranges = <0 0x02020000 0x30000>;
  81
  82                 smp-sysram@0 {
  83                         compatible = "samsung,exynos4210-sysram";
  84                         reg = <0x0 0x1000>;
  85                 };
  86
  87                 smp-sysram@2f000 {
  88                         compatible = "samsung,exynos4210-sysram-ns";
  89                         reg = <0x2f000 0x1000>;
  90                 };
  91         };
  92
  93         pd_gsc: gsc-power-domain@10044000 {
  94                 compatible = "samsung,exynos4210-pd";
  95                 reg = <0x10044000 0x20>;
  96         };
  97
  98         pd_mfc: mfc-power-domain@10044040 {
  99                 compatible = "samsung,exynos4210-pd";
 100                 reg = <0x10044040 0x20>;
 101         };
 102
 103         clock: clock-controller@10010000 {
 104                 compatible = "samsung,exynos5250-clock";
 105                 reg = <0x10010000 0x30000>;
 106                 #clock-cells = <1>;
 107         };
 108
 109         clock_audss: audss-clock-controller@3810000 {
 110                 compatible = "samsung,exynos5250-audss-clock";
 111                 reg = <0x03810000 0x0C>;
 112                 #clock-cells = <1>;
 113                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
 114                          <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
 115                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 116         };
 117
 118         timer {
 119                 compatible = "arm,armv7-timer";
 120                 interrupts = <1 13 0xf08>,
 121                              <1 14 0xf08>,
 122                              <1 11 0xf08>,
 123                              <1 10 0xf08>;
 124                 /* Unfortunately we need this since some versions of U-Boot
 125                  * on Exynos don't set the CNTFRQ register, so we need the
 126                  * value from DT.
 127                  */
 128                 clock-frequency = <24000000>;
 129         };
 130
 131         mct@101C0000 {
 132                 compatible = "samsung,exynos4210-mct";
 133                 reg = <0x101C0000 0x800>;
 134                 interrupt-controller;
 135                 #interrups-cells = <2>;
 136                 interrupt-parent = <&mct_map>;
 137                 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
 138                              <4 0>, <5 0>;
 139                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 140                 clock-names = "fin_pll", "mct";
 141
 142                 mct_map: mct-map {
 143                         #interrupt-cells = <2>;
 144                         #address-cells = <0>;
 145                         #size-cells = <0>;
 146                         interrupt-map = <0x0 0 &combiner 23 3>,
 147                                         <0x1 0 &combiner 23 4>,
 148                                         <0x2 0 &combiner 25 2>,
 149                                         <0x3 0 &combiner 25 3>,
 150                                         <0x4 0 &gic 0 120 0>,
 151                                         <0x5 0 &gic 0 121 0>;
 152                 };
 153         };
 154
 155         pmu {
 156                 compatible = "arm,cortex-a15-pmu";
 157                 interrupt-parent = <&combiner>;
 158                 interrupts = <1 2>, <22 4>;
 159         };
 160
 161         pinctrl_0: pinctrl@11400000 {
 162                 compatible = "samsung,exynos5250-pinctrl";
 163                 reg = <0x11400000 0x1000>;
 164                 interrupts = <0 46 0>;
 165
 166                 wakup_eint: wakeup-interrupt-controller {
 167                         compatible = "samsung,exynos4210-wakeup-eint";
 168                         interrupt-parent = <&gic>;
 169                         interrupts = <0 32 0>;
 170                 };
 171         };
 172
 173         pinctrl_1: pinctrl@13400000 {
 174                 compatible = "samsung,exynos5250-pinctrl";
 175                 reg = <0x13400000 0x1000>;
 176                 interrupts = <0 45 0>;
 177         };
 178
 179         pinctrl_2: pinctrl@10d10000 {
 180                 compatible = "samsung,exynos5250-pinctrl";
 181                 reg = <0x10d10000 0x1000>;
 182                 interrupts = <0 50 0>;
 183         };
 184
 185         pinctrl_3: pinctrl@03860000 {
 186                 compatible = "samsung,exynos5250-pinctrl";
 187                 reg = <0x03860000 0x1000>;
 188                 interrupts = <0 47 0>;
 189         };
 190
 191         pmu_system_controller: system-controller@10040000 {
 192                 compatible = "samsung,exynos5250-pmu", "syscon";
 193                 reg = <0x10040000 0x5000>;
 194         };
 195
 196         watchdog@101D0000 {
 197                 compatible = "samsung,exynos5250-wdt";
 198                 reg = <0x101D0000 0x100>;
 199                 interrupts = <0 42 0>;
 200                 clocks = <&clock CLK_WDT>;
 201                 clock-names = "watchdog";
 202                 samsung,syscon-phandle = <&pmu_system_controller>;
 203         };
 204
 205         g2d@10850000 {
 206                 compatible = "samsung,exynos5250-g2d";
 207                 reg = <0x10850000 0x1000>;
 208                 interrupts = <0 91 0>;
 209                 clocks = <&clock CLK_G2D>;
 210                 clock-names = "fimg2d";
 211         };
 212
 213         codec@11000000 {
 214                 compatible = "samsung,mfc-v6";
 215                 reg = <0x11000000 0x10000>;
 216                 interrupts = <0 96 0>;
 217                 samsung,power-domain = <&pd_mfc>;
 218                 clocks = <&clock CLK_MFC>;
 219                 clock-names = "mfc";
 220         };
 221
 222         rtc@101E0000 {
 223                 clocks = <&clock CLK_RTC>;
 224                 clock-names = "rtc";
 225                 status = "disabled";
 226         };
 227
 228         tmu@10060000 {
 229                 compatible = "samsung,exynos5250-tmu";
 230                 reg = <0x10060000 0x100>;
 231                 interrupts = <0 65 0>;
 232                 clocks = <&clock CLK_TMU>;
 233                 clock-names = "tmu_apbif";
 234         };
 235
 236         serial@12C00000 {
 237                 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 238                 clock-names = "uart", "clk_uart_baud0";
 239         };
 240
 241         serial@12C10000 {
 242                 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 243                 clock-names = "uart", "clk_uart_baud0";
 244         };
 245
 246         serial@12C20000 {
 247                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 248                 clock-names = "uart", "clk_uart_baud0";
 249         };
 250
 251         serial@12C30000 {
 252                 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 253                 clock-names = "uart", "clk_uart_baud0";
 254         };
 255
 256         sata@122F0000 {
 257                 compatible = "snps,dwc-ahci";
 258                 samsung,sata-freq = <66>;
 259                 reg = <0x122F0000 0x1ff>;
 260                 interrupts = <0 115 0>;
 261                 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
 262                 clock-names = "sata", "sclk_sata";
 263                 phys = <&sata_phy>;
 264                 phy-names = "sata-phy";
 265                 status = "disabled";
 266         };
 267
 268         sata_phy: sata-phy@12170000 {
 269                 compatible = "samsung,exynos5250-sata-phy";
 270                 reg = <0x12170000 0x1ff>;
 271                 clocks = <&clock 287>;
 272                 clock-names = "sata_phyctrl";
 273                 #phy-cells = <0>;
 274                 samsung,syscon-phandle = <&pmu_system_controller>;
 275                 status = "disabled";
 276         };
 277
 278         i2c_0: i2c@12C60000 {
 279                 compatible = "samsung,s3c2440-i2c";
 280                 reg = <0x12C60000 0x100>;
 281                 interrupts = <0 56 0>;
 282                 #address-cells = <1>;
 283                 #size-cells = <0>;
 284                 clocks = <&clock CLK_I2C0>;
 285                 clock-names = "i2c";
 286                 pinctrl-names = "default";
 287                 pinctrl-0 = <&i2c0_bus>;
 288                 status = "disabled";
 289         };
 290
 291         i2c_1: i2c@12C70000 {
 292                 compatible = "samsung,s3c2440-i2c";
 293                 reg = <0x12C70000 0x100>;
 294                 interrupts = <0 57 0>;
 295                 #address-cells = <1>;
 296                 #size-cells = <0>;
 297                 clocks = <&clock CLK_I2C1>;
 298                 clock-names = "i2c";
 299                 pinctrl-names = "default";
 300                 pinctrl-0 = <&i2c1_bus>;
 301                 status = "disabled";
 302         };
 303
 304         i2c_2: i2c@12C80000 {
 305                 compatible = "samsung,s3c2440-i2c";
 306                 reg = <0x12C80000 0x100>;
 307                 interrupts = <0 58 0>;
 308                 #address-cells = <1>;
 309                 #size-cells = <0>;
 310                 clocks = <&clock CLK_I2C2>;
 311                 clock-names = "i2c";
 312                 pinctrl-names = "default";
 313                 pinctrl-0 = <&i2c2_bus>;
 314                 status = "disabled";
 315         };
 316
 317         i2c_3: i2c@12C90000 {
 318                 compatible = "samsung,s3c2440-i2c";
 319                 reg = <0x12C90000 0x100>;
 320                 interrupts = <0 59 0>;
 321                 #address-cells = <1>;
 322                 #size-cells = <0>;
 323                 clocks = <&clock CLK_I2C3>;
 324                 clock-names = "i2c";
 325                 pinctrl-names = "default";
 326                 pinctrl-0 = <&i2c3_bus>;
 327                 status = "disabled";
 328         };
 329
 330         i2c_4: i2c@12CA0000 {
 331                 compatible = "samsung,s3c2440-i2c";
 332                 reg = <0x12CA0000 0x100>;
 333                 interrupts = <0 60 0>;
 334                 #address-cells = <1>;
 335                 #size-cells = <0>;
 336                 clocks = <&clock CLK_I2C4>;
 337                 clock-names = "i2c";
 338                 pinctrl-names = "default";
 339                 pinctrl-0 = <&i2c4_bus>;
 340                 status = "disabled";
 341         };
 342
 343         i2c_5: i2c@12CB0000 {
 344                 compatible = "samsung,s3c2440-i2c";
 345                 reg = <0x12CB0000 0x100>;
 346                 interrupts = <0 61 0>;
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 clocks = <&clock CLK_I2C5>;
 350                 clock-names = "i2c";
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&i2c5_bus>;
 353                 status = "disabled";
 354         };
 355
 356         i2c_6: i2c@12CC0000 {
 357                 compatible = "samsung,s3c2440-i2c";
 358                 reg = <0x12CC0000 0x100>;
 359                 interrupts = <0 62 0>;
 360                 #address-cells = <1>;
 361                 #size-cells = <0>;
 362                 clocks = <&clock CLK_I2C6>;
 363                 clock-names = "i2c";
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&i2c6_bus>;
 366                 status = "disabled";
 367         };
 368
 369         i2c_7: i2c@12CD0000 {
 370                 compatible = "samsung,s3c2440-i2c";
 371                 reg = <0x12CD0000 0x100>;
 372                 interrupts = <0 63 0>;
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375                 clocks = <&clock CLK_I2C7>;
 376                 clock-names = "i2c";
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&i2c7_bus>;
 379                 status = "disabled";
 380         };
 381
 382         i2c_8: i2c@12CE0000 {
 383                 compatible = "samsung,s3c2440-hdmiphy-i2c";
 384                 reg = <0x12CE0000 0x1000>;
 385                 interrupts = <0 64 0>;
 386                 #address-cells = <1>;
 387                 #size-cells = <0>;
 388                 clocks = <&clock CLK_I2C_HDMI>;
 389                 clock-names = "i2c";
 390                 status = "disabled";
 391         };
 392
 393         i2c_9: i2c@121D0000 {
 394                 compatible = "samsung,exynos5-sata-phy-i2c";
 395                 reg = <0x121D0000 0x100>;
 396                 #address-cells = <1>;
 397                 #size-cells = <0>;
 398                 clocks = <&clock CLK_SATA_PHYI2C>;
 399                 clock-names = "i2c";
 400                 status = "disabled";
 401         };
 402
 403         spi_0: spi@12d20000 {
 404                 compatible = "samsung,exynos4210-spi";
 405                 status = "disabled";
 406                 reg = <0x12d20000 0x100>;
 407                 interrupts = <0 66 0>;
 408                 dmas = <&pdma0 5
 409                         &pdma0 4>;
 410                 dma-names = "tx", "rx";
 411                 #address-cells = <1>;
 412                 #size-cells = <0>;
 413                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 414                 clock-names = "spi", "spi_busclk0";
 415                 pinctrl-names = "default";
 416                 pinctrl-0 = <&spi0_bus>;
 417         };
 418
 419         spi_1: spi@12d30000 {
 420                 compatible = "samsung,exynos4210-spi";
 421                 status = "disabled";
 422                 reg = <0x12d30000 0x100>;
 423                 interrupts = <0 67 0>;
 424                 dmas = <&pdma1 5
 425                         &pdma1 4>;
 426                 dma-names = "tx", "rx";
 427                 #address-cells = <1>;
 428                 #size-cells = <0>;
 429                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 430                 clock-names = "spi", "spi_busclk0";
 431                 pinctrl-names = "default";
 432                 pinctrl-0 = <&spi1_bus>;
 433         };
 434
 435         spi_2: spi@12d40000 {
 436                 compatible = "samsung,exynos4210-spi";
 437                 status = "disabled";
 438                 reg = <0x12d40000 0x100>;
 439                 interrupts = <0 68 0>;
 440                 dmas = <&pdma0 7
 441                         &pdma0 6>;
 442                 dma-names = "tx", "rx";
 443                 #address-cells = <1>;
 444                 #size-cells = <0>;
 445                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 446                 clock-names = "spi", "spi_busclk0";
 447                 pinctrl-names = "default";
 448                 pinctrl-0 = <&spi2_bus>;
 449         };
 450
 451         mmc_0: mmc@12200000 {
 452                 compatible = "samsung,exynos5250-dw-mshc";
 453                 interrupts = <0 75 0>;
 454                 #address-cells = <1>;
 455                 #size-cells = <0>;
 456                 reg = <0x12200000 0x1000>;
 457                 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 458                 clock-names = "biu", "ciu";
 459                 fifo-depth = <0x80>;
 460                 status = "disabled";
 461         };
 462
 463         mmc_1: mmc@12210000 {
 464                 compatible = "samsung,exynos5250-dw-mshc";
 465                 interrupts = <0 76 0>;
 466                 #address-cells = <1>;
 467                 #size-cells = <0>;
 468                 reg = <0x12210000 0x1000>;
 469                 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 470                 clock-names = "biu", "ciu";
 471                 fifo-depth = <0x80>;
 472                 status = "disabled";
 473         };
 474
 475         mmc_2: mmc@12220000 {
 476                 compatible = "samsung,exynos5250-dw-mshc";
 477                 interrupts = <0 77 0>;
 478                 #address-cells = <1>;
 479                 #size-cells = <0>;
 480                 reg = <0x12220000 0x1000>;
 481                 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 482                 clock-names = "biu", "ciu";
 483                 fifo-depth = <0x80>;
 484                 status = "disabled";
 485         };
 486
 487         mmc_3: mmc@12230000 {
 488                 compatible = "samsung,exynos5250-dw-mshc";
 489                 reg = <0x12230000 0x1000>;
 490                 interrupts = <0 78 0>;
 491                 #address-cells = <1>;
 492                 #size-cells = <0>;
 493                 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 494                 clock-names = "biu", "ciu";
 495                 fifo-depth = <0x80>;
 496                 status = "disabled";
 497         };
 498
 499         i2s0: i2s@03830000 {
 500                 compatible = "samsung,s5pv210-i2s";
 501                 status = "disabled";
 502                 reg = <0x03830000 0x100>;
 503                 dmas = <&pdma0 10
 504                         &pdma0 9
 505                         &pdma0 8>;
 506                 dma-names = "tx", "rx", "tx-sec";
 507                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 508                         <&clock_audss EXYNOS_I2S_BUS>,
 509                         <&clock_audss EXYNOS_SCLK_I2S>;
 510                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 511                 samsung,idma-addr = <0x03000000>;
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&i2s0_bus>;
 514         };
 515
 516         i2s1: i2s@12D60000 {
 517                 compatible = "samsung,s3c6410-i2s";
 518                 status = "disabled";
 519                 reg = <0x12D60000 0x100>;
 520                 dmas = <&pdma1 12
 521                         &pdma1 11>;
 522                 dma-names = "tx", "rx";
 523                 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
 524                 clock-names = "iis", "i2s_opclk0";
 525                 pinctrl-names = "default";
 526                 pinctrl-0 = <&i2s1_bus>;
 527         };
 528
 529         i2s2: i2s@12D70000 {
 530                 compatible = "samsung,s3c6410-i2s";
 531                 status = "disabled";
 532                 reg = <0x12D70000 0x100>;
 533                 dmas = <&pdma0 12
 534                         &pdma0 11>;
 535                 dma-names = "tx", "rx";
 536                 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
 537                 clock-names = "iis", "i2s_opclk0";
 538                 pinctrl-names = "default";
 539                 pinctrl-0 = <&i2s2_bus>;
 540         };
 541
 542         usb@12000000 {
 543                 compatible = "samsung,exynos5250-dwusb3";
 544                 clocks = <&clock CLK_USB3>;
 545                 clock-names = "usbdrd30";
 546                 #address-cells = <1>;
 547                 #size-cells = <1>;
 548                 ranges;
 549
 550                 dwc3 {
 551                         compatible = "synopsys,dwc3";
 552                         reg = <0x12000000 0x10000>;
 553                         interrupts = <0 72 0>;
 554                         phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
 555                         phy-names = "usb2-phy", "usb3-phy";
 556                 };
 557         };
 558
 559         usbdrd_phy: phy@12100000 {
 560                 compatible = "samsung,exynos5250-usbdrd-phy";
 561                 reg = <0x12100000 0x100>;
 562                 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
 563                 clock-names = "phy", "ref";
 564                 samsung,pmu-syscon = <&pmu_system_controller>;
 565                 #phy-cells = <1>;
 566         };
 567
 568         usb@12110000 {
 569                 compatible = "samsung,exynos4210-ehci";
 570                 reg = <0x12110000 0x100>;
 571                 interrupts = <0 71 0>;
 572
 573                 clocks = <&clock CLK_USB2>;
 574                 clock-names = "usbhost";
 575         };
 576
 577         usb@12120000 {
 578                 compatible = "samsung,exynos4210-ohci";
 579                 reg = <0x12120000 0x100>;
 580                 interrupts = <0 71 0>;
 581
 582                 clocks = <&clock CLK_USB2>;
 583                 clock-names = "usbhost";
 584         };
 585
 586         usb2_phy: usbphy@12130000 {
 587                 compatible = "samsung,exynos5250-usb2phy";
 588                 reg = <0x12130000 0x100>;
 589                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>;
 590                 clock-names = "ext_xtal", "usbhost";
 591                 #address-cells = <1>;
 592                 #size-cells = <1>;
 593                 ranges;
 594
 595                 usbphy-sys {
 596                         reg = <0x10040704 0x8>,
 597                               <0x10050230 0x4>;
 598                 };
 599         };
 600
 601         pwm: pwm@12dd0000 {
 602                 compatible = "samsung,exynos4210-pwm";
 603                 reg = <0x12dd0000 0x100>;
 604                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 605                 #pwm-cells = <3>;
 606                 clocks = <&clock CLK_PWM>;
 607                 clock-names = "timers";
 608         };
 609
 610         amba {
 611                 #address-cells = <1>;
 612                 #size-cells = <1>;
 613                 compatible = "arm,amba-bus";
 614                 interrupt-parent = <&gic>;
 615                 ranges;
 616
 617                 pdma0: pdma@121A0000 {
 618                         compatible = "arm,pl330", "arm,primecell";
 619                         reg = <0x121A0000 0x1000>;
 620                         interrupts = <0 34 0>;
 621                         clocks = <&clock CLK_PDMA0>;
 622                         clock-names = "apb_pclk";
 623                         #dma-cells = <1>;
 624                         #dma-channels = <8>;
 625                         #dma-requests = <32>;
 626                 };
 627
 628                 pdma1: pdma@121B0000 {
 629                         compatible = "arm,pl330", "arm,primecell";
 630                         reg = <0x121B0000 0x1000>;
 631                         interrupts = <0 35 0>;
 632                         clocks = <&clock CLK_PDMA1>;
 633                         clock-names = "apb_pclk";
 634                         #dma-cells = <1>;
 635                         #dma-channels = <8>;
 636                         #dma-requests = <32>;
 637                 };
 638
 639                 mdma0: mdma@10800000 {
 640                         compatible = "arm,pl330", "arm,primecell";
 641                         reg = <0x10800000 0x1000>;
 642                         interrupts = <0 33 0>;
 643                         clocks = <&clock CLK_MDMA0>;
 644                         clock-names = "apb_pclk";
 645                         #dma-cells = <1>;
 646                         #dma-channels = <8>;
 647                         #dma-requests = <1>;
 648                 };
 649
 650                 mdma1: mdma@11C10000 {
 651                         compatible = "arm,pl330", "arm,primecell";
 652                         reg = <0x11C10000 0x1000>;
 653                         interrupts = <0 124 0>;
 654                         clocks = <&clock CLK_MDMA1>;
 655                         clock-names = "apb_pclk";
 656                         #dma-cells = <1>;
 657                         #dma-channels = <8>;
 658                         #dma-requests = <1>;
 659                 };
 660         };
 661
 662         gsc_0:  gsc@13e00000 {
 663                 compatible = "samsung,exynos5-gsc";
 664                 reg = <0x13e00000 0x1000>;
 665                 interrupts = <0 85 0>;
 666                 samsung,power-domain = <&pd_gsc>;
 667                 clocks = <&clock CLK_GSCL0>;
 668                 clock-names = "gscl";
 669         };
 670
 671         gsc_1:  gsc@13e10000 {
 672                 compatible = "samsung,exynos5-gsc";
 673                 reg = <0x13e10000 0x1000>;
 674                 interrupts = <0 86 0>;
 675                 samsung,power-domain = <&pd_gsc>;
 676                 clocks = <&clock CLK_GSCL1>;
 677                 clock-names = "gscl";
 678         };
 679
 680         gsc_2:  gsc@13e20000 {
 681                 compatible = "samsung,exynos5-gsc";
 682                 reg = <0x13e20000 0x1000>;
 683                 interrupts = <0 87 0>;
 684                 samsung,power-domain = <&pd_gsc>;
 685                 clocks = <&clock CLK_GSCL2>;
 686                 clock-names = "gscl";
 687         };
 688
 689         gsc_3:  gsc@13e30000 {
 690                 compatible = "samsung,exynos5-gsc";
 691                 reg = <0x13e30000 0x1000>;
 692                 interrupts = <0 88 0>;
 693                 samsung,power-domain = <&pd_gsc>;
 694                 clocks = <&clock CLK_GSCL3>;
 695                 clock-names = "gscl";
 696         };
 697
 698         hdmi {
 699                 compatible = "samsung,exynos4212-hdmi";
 700                 reg = <0x14530000 0x70000>;
 701                 interrupts = <0 95 0>;
 702                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 703                          <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 704                          <&clock CLK_MOUT_HDMI>;
 705                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 706                                 "sclk_hdmiphy", "mout_hdmi";
 707         };
 708
 709         mixer {
 710                 compatible = "samsung,exynos5250-mixer";
 711                 reg = <0x14450000 0x10000>;
 712                 interrupts = <0 94 0>;
 713                 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
 714                 clock-names = "mixer", "sclk_hdmi";
 715         };
 716
 717         dp_phy: video-phy@10040720 {
 718                 compatible = "samsung,exynos5250-dp-video-phy";
 719                 reg = <0x10040720 4>;
 720                 #phy-cells = <0>;
 721         };
 722
 723         dp-controller@145B0000 {
 724                 clocks = <&clock CLK_DP>;
 725                 clock-names = "dp";
 726                 phys = <&dp_phy>;
 727                 phy-names = "dp";
 728         };
 729
 730         fimd@14400000 {
 731                 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
 732                 clock-names = "sclk_fimd", "fimd";
 733         };
 734
 735         adc: adc@12D10000 {
 736                 compatible = "samsung,exynos-adc-v1";
 737                 reg = <0x12D10000 0x100>, <0x10040718 0x4>;
 738                 interrupts = <0 106 0>;
 739                 clocks = <&clock CLK_ADC>;
 740                 clock-names = "adc";
 741                 #io-channel-cells = <1>;
 742                 io-channel-ranges;
 743                 status = "disabled";
 744         };
 745
 746         sss@10830000 {
 747                 compatible = "samsung,exynos4210-secss";
 748                 reg = <0x10830000 0x10000>;
 749                 interrupts = <0 112 0>;
 750                 clocks = <&clock 348>;
 751                 clock-names = "secss";
 752         };
 753 };