arch/arm/boot/dts/exynos4x12.dtsi

   1 /*
   2  * Samsung's Exynos4x12 SoCs device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include "exynos4.dtsi"
  21 #include "exynos4x12-pinctrl.dtsi"
  22
  23 / {
  24         aliases {
  25                 pinctrl0 = &pinctrl_0;
  26                 pinctrl1 = &pinctrl_1;
  27                 pinctrl2 = &pinctrl_2;
  28                 pinctrl3 = &pinctrl_3;
  29                 fimc-lite0 = &fimc_lite_0;
  30                 fimc-lite1 = &fimc_lite_1;
  31                 mshc0 = &mshc_0;
  32         };
  33
  34         pd_isp: isp-power-domain@10023CA0 {
  35                 compatible = "samsung,exynos4210-pd";
  36                 reg = <0x10023CA0 0x20>;
  37         };
  38
  39         clock: clock-controller@10030000 {
  40                 compatible = "samsung,exynos4412-clock";
  41                 reg = <0x10030000 0x20000>;
  42                 #clock-cells = <1>;
  43         };
  44
  45         mct@10050000 {
  46                 compatible = "samsung,exynos4412-mct";
  47                 reg = <0x10050000 0x800>;
  48                 interrupt-parent = <&mct_map>;
  49                 interrupts = <0>, <1>, <2>, <3>, <4>;
  50                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
  51                 clock-names = "fin_pll", "mct";
  52
  53                 mct_map: mct-map {
  54                         #interrupt-cells = <1>;
  55                         #address-cells = <0>;
  56                         #size-cells = <0>;
  57                         interrupt-map = <0 &gic 0 57 0>,
  58                                         <1 &combiner 12 5>,
  59                                         <2 &combiner 12 6>,
  60                                         <3 &combiner 12 7>,
  61                                         <4 &gic 1 12 0>;
  62                 };
  63         };
  64
  65         pinctrl_0: pinctrl@11400000 {
  66                 compatible = "samsung,exynos4x12-pinctrl";
  67                 reg = <0x11400000 0x1000>;
  68                 interrupts = <0 47 0>;
  69         };
  70
  71         pinctrl_1: pinctrl@11000000 {
  72                 compatible = "samsung,exynos4x12-pinctrl";
  73                 reg = <0x11000000 0x1000>;
  74                 interrupts = <0 46 0>;
  75
  76                 wakup_eint: wakeup-interrupt-controller {
  77                         compatible = "samsung,exynos4210-wakeup-eint";
  78                         interrupt-parent = <&gic>;
  79                         interrupts = <0 32 0>;
  80                 };
  81         };
  82
  83         pinctrl_2: pinctrl@03860000 {
  84                 compatible = "samsung,exynos4x12-pinctrl";
  85                 reg = <0x03860000 0x1000>;
  86                 interrupt-parent = <&combiner>;
  87                 interrupts = <10 0>;
  88         };
  89
  90         pinctrl_3: pinctrl@106E0000 {
  91                 compatible = "samsung,exynos4x12-pinctrl";
  92                 reg = <0x106E0000 0x1000>;
  93                 interrupts = <0 72 0>;
  94         };
  95
  96         g2d@10800000 {
  97                 compatible = "samsung,exynos4212-g2d";
  98                 reg = <0x10800000 0x1000>;
  99                 interrupts = <0 89 0>;
 100                 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
 101                 clock-names = "sclk_fimg2d", "fimg2d";
 102                 status = "disabled";
 103         };
 104
 105         camera {
 106                 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
 107                          <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
 108                 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
 109
 110                 fimc_0: fimc@11800000 {
 111                         compatible = "samsung,exynos4212-fimc";
 112                         samsung,pix-limits = <4224 8192 1920 4224>;
 113                         samsung,mainscaler-ext;
 114                         samsung,isp-wb;
 115                         samsung,cam-if;
 116                 };
 117
 118                 fimc_1: fimc@11810000 {
 119                         compatible = "samsung,exynos4212-fimc";
 120                         samsung,pix-limits = <4224 8192 1920 4224>;
 121                         samsung,mainscaler-ext;
 122                         samsung,isp-wb;
 123                         samsung,cam-if;
 124                 };
 125
 126                 fimc_2: fimc@11820000 {
 127                         compatible = "samsung,exynos4212-fimc";
 128                         samsung,pix-limits = <4224 8192 1920 4224>;
 129                         samsung,mainscaler-ext;
 130                         samsung,isp-wb;
 131                         samsung,lcd-wb;
 132                         samsung,cam-if;
 133                 };
 134
 135                 fimc_3: fimc@11830000 {
 136                         compatible = "samsung,exynos4212-fimc";
 137                         samsung,pix-limits = <1920 8192 1366 1920>;
 138                         samsung,rotators = <0>;
 139                         samsung,mainscaler-ext;
 140                         samsung,isp-wb;
 141                         samsung,lcd-wb;
 142                 };
 143
 144                 fimc_lite_0: fimc-lite@12390000 {
 145                         compatible = "samsung,exynos4212-fimc-lite";
 146                         reg = <0x12390000 0x1000>;
 147                         interrupts = <0 105 0>;
 148                         samsung,power-domain = <&pd_isp>;
 149                         clocks = <&clock CLK_FIMC_LITE0>;
 150                         clock-names = "flite";
 151                         status = "disabled";
 152                 };
 153
 154                 fimc_lite_1: fimc-lite@123A0000 {
 155                         compatible = "samsung,exynos4212-fimc-lite";
 156                         reg = <0x123A0000 0x1000>;
 157                         interrupts = <0 106 0>;
 158                         samsung,power-domain = <&pd_isp>;
 159                         clocks = <&clock CLK_FIMC_LITE1>;
 160                         clock-names = "flite";
 161                         status = "disabled";
 162                 };
 163
 164                 fimc_is: fimc-is@12000000 {
 165                         compatible = "samsung,exynos4212-fimc-is", "simple-bus";
 166                         reg = <0x12000000 0x260000>;
 167                         interrupts = <0 90 0>, <0 95 0>;
 168                         samsung,power-domain = <&pd_isp>;
 169                         clocks = <&clock CLK_FIMC_LITE0>,
 170                                  <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
 171                                  <&clock CLK_PPMUISPMX>,
 172                                  <&clock CLK_MOUT_MPLL_USER_T>,
 173                                  <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
 174                                  <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
 175                                  <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
 176                                  <&clock CLK_DIV_MCUISP0>,
 177                                  <&clock CLK_DIV_MCUISP1>,
 178                                  <&clock CLK_SCLK_UART_ISP>,
 179                                  <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
 180                                  <&clock CLK_ACLK400_MCUISP>,
 181                                  <&clock CLK_DIV_ACLK400_MCUISP>;
 182                         clock-names = "lite0", "lite1", "ppmuispx",
 183                                       "ppmuispmx", "mpll", "isp",
 184                                       "drc", "fd", "mcuisp",
 185                                       "ispdiv0", "ispdiv1", "mcuispdiv0",
 186                                       "mcuispdiv1", "uart", "aclk200",
 187                                       "div_aclk200", "aclk400mcuisp",
 188                                       "div_aclk400mcuisp";
 189                         #address-cells = <1>;
 190                         #size-cells = <1>;
 191                         ranges;
 192                         status = "disabled";
 193
 194                         pmu {
 195                                 reg = <0x10020000 0x3000>;
 196                         };
 197
 198                         i2c1_isp: i2c-isp@12140000 {
 199                                 compatible = "samsung,exynos4212-i2c-isp";
 200                                 reg = <0x12140000 0x100>;
 201                                 clocks = <&clock CLK_I2C1_ISP>;
 202                                 clock-names = "i2c_isp";
 203                                 #address-cells = <1>;
 204                                 #size-cells = <0>;
 205                         };
 206                 };
 207         };
 208
 209         mshc_0: mmc@12550000 {
 210                 compatible = "samsung,exynos4412-dw-mshc";
 211                 reg = <0x12550000 0x1000>;
 212                 interrupts = <0 77 0>;
 213                 #address-cells = <1>;
 214                 #size-cells = <0>;
 215                 fifo-depth = <0x80>;
 216                 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
 217                 clock-names = "biu", "ciu";
 218                 status = "disabled";
 219         };
 220 };