arch/arm/boot/dts/exynos4x12.dtsi

   1 /*
   2  * Samsung's Exynos4x12 SoCs device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include "exynos4.dtsi"
  21 #include "exynos4x12-pinctrl.dtsi"
  22
  23 / {
  24         aliases {
  25                 pinctrl0 = &pinctrl_0;
  26                 pinctrl1 = &pinctrl_1;
  27                 pinctrl2 = &pinctrl_2;
  28                 pinctrl3 = &pinctrl_3;
  29                 fimc-lite0 = &fimc_lite_0;
  30                 fimc-lite1 = &fimc_lite_1;
  31                 mshc0 = &mshc_0;
  32         };
  33
  34         pmu {
  35                 compatible = "arm,cortex-a9-pmu";
  36                 interrupt-parent = <&combiner>;
  37                 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
  38         };
  39
  40         pd_isp: isp-power-domain@10023CA0 {
  41                 compatible = "samsung,exynos4210-pd";
  42                 reg = <0x10023CA0 0x20>;
  43         };
  44
  45         clock: clock-controller@10030000 {
  46                 compatible = "samsung,exynos4412-clock";
  47                 reg = <0x10030000 0x20000>;
  48                 #clock-cells = <1>;
  49         };
  50
  51         mct@10050000 {
  52                 compatible = "samsung,exynos4412-mct";
  53                 reg = <0x10050000 0x800>;
  54                 interrupt-parent = <&mct_map>;
  55                 interrupts = <0>, <1>, <2>, <3>, <4>;
  56                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
  57                 clock-names = "fin_pll", "mct";
  58
  59                 mct_map: mct-map {
  60                         #interrupt-cells = <1>;
  61                         #address-cells = <0>;
  62                         #size-cells = <0>;
  63                         interrupt-map = <0 &gic 0 57 0>,
  64                                         <1 &combiner 12 5>,
  65                                         <2 &combiner 12 6>,
  66                                         <3 &combiner 12 7>,
  67                                         <4 &gic 1 12 0>;
  68                 };
  69         };
  70
  71         pinctrl_0: pinctrl@11400000 {
  72                 compatible = "samsung,exynos4x12-pinctrl";
  73                 reg = <0x11400000 0x1000>;
  74                 interrupts = <0 47 0>;
  75         };
  76
  77         pinctrl_1: pinctrl@11000000 {
  78                 compatible = "samsung,exynos4x12-pinctrl";
  79                 reg = <0x11000000 0x1000>;
  80                 interrupts = <0 46 0>;
  81
  82                 wakup_eint: wakeup-interrupt-controller {
  83                         compatible = "samsung,exynos4210-wakeup-eint";
  84                         interrupt-parent = <&gic>;
  85                         interrupts = <0 32 0>;
  86                 };
  87         };
  88
  89         adc: adc@126C0000 {
  90                 compatible = "samsung,exynos-adc-v1";
  91                 reg = <0x126C0000 0x100>, <0x10020718 0x4>;
  92                 interrupt-parent = <&combiner>;
  93                 interrupts = <10 3>;
  94                 clocks = <&clock CLK_TSADC>;
  95                 clock-names = "adc";
  96                 #io-channel-cells = <1>;
  97                 io-channel-ranges;
  98                 status = "disabled";
  99         };
 100
 101         pinctrl_2: pinctrl@03860000 {
 102                 compatible = "samsung,exynos4x12-pinctrl";
 103                 reg = <0x03860000 0x1000>;
 104                 interrupt-parent = <&combiner>;
 105                 interrupts = <10 0>;
 106         };
 107
 108         pinctrl_3: pinctrl@106E0000 {
 109                 compatible = "samsung,exynos4x12-pinctrl";
 110                 reg = <0x106E0000 0x1000>;
 111                 interrupts = <0 72 0>;
 112         };
 113
 114         g2d@10800000 {
 115                 compatible = "samsung,exynos4212-g2d";
 116                 reg = <0x10800000 0x1000>;
 117                 interrupts = <0 89 0>;
 118                 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
 119                 clock-names = "sclk_fimg2d", "fimg2d";
 120                 status = "disabled";
 121         };
 122
 123         camera {
 124                 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
 125                          <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
 126                 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
 127
 128                 fimc_0: fimc@11800000 {
 129                         compatible = "samsung,exynos4212-fimc";
 130                         samsung,pix-limits = <4224 8192 1920 4224>;
 131                         samsung,mainscaler-ext;
 132                         samsung,isp-wb;
 133                         samsung,cam-if;
 134                 };
 135
 136                 fimc_1: fimc@11810000 {
 137                         compatible = "samsung,exynos4212-fimc";
 138                         samsung,pix-limits = <4224 8192 1920 4224>;
 139                         samsung,mainscaler-ext;
 140                         samsung,isp-wb;
 141                         samsung,cam-if;
 142                 };
 143
 144                 fimc_2: fimc@11820000 {
 145                         compatible = "samsung,exynos4212-fimc";
 146                         samsung,pix-limits = <4224 8192 1920 4224>;
 147                         samsung,mainscaler-ext;
 148                         samsung,isp-wb;
 149                         samsung,lcd-wb;
 150                         samsung,cam-if;
 151                 };
 152
 153                 fimc_3: fimc@11830000 {
 154                         compatible = "samsung,exynos4212-fimc";
 155                         samsung,pix-limits = <1920 8192 1366 1920>;
 156                         samsung,rotators = <0>;
 157                         samsung,mainscaler-ext;
 158                         samsung,isp-wb;
 159                         samsung,lcd-wb;
 160                 };
 161
 162                 fimc_lite_0: fimc-lite@12390000 {
 163                         compatible = "samsung,exynos4212-fimc-lite";
 164                         reg = <0x12390000 0x1000>;
 165                         interrupts = <0 105 0>;
 166                         samsung,power-domain = <&pd_isp>;
 167                         clocks = <&clock CLK_FIMC_LITE0>;
 168                         clock-names = "flite";
 169                         status = "disabled";
 170                 };
 171
 172                 fimc_lite_1: fimc-lite@123A0000 {
 173                         compatible = "samsung,exynos4212-fimc-lite";
 174                         reg = <0x123A0000 0x1000>;
 175                         interrupts = <0 106 0>;
 176                         samsung,power-domain = <&pd_isp>;
 177                         clocks = <&clock CLK_FIMC_LITE1>;
 178                         clock-names = "flite";
 179                         status = "disabled";
 180                 };
 181
 182                 fimc_is: fimc-is@12000000 {
 183                         compatible = "samsung,exynos4212-fimc-is", "simple-bus";
 184                         reg = <0x12000000 0x260000>;
 185                         interrupts = <0 90 0>, <0 95 0>;
 186                         samsung,power-domain = <&pd_isp>;
 187                         clocks = <&clock CLK_FIMC_LITE0>,
 188                                  <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
 189                                  <&clock CLK_PPMUISPMX>,
 190                                  <&clock CLK_MOUT_MPLL_USER_T>,
 191                                  <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
 192                                  <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
 193                                  <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
 194                                  <&clock CLK_DIV_MCUISP0>,
 195                                  <&clock CLK_DIV_MCUISP1>,
 196                                  <&clock CLK_SCLK_UART_ISP>,
 197                                  <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
 198                                  <&clock CLK_ACLK400_MCUISP>,
 199                                  <&clock CLK_DIV_ACLK400_MCUISP>;
 200                         clock-names = "lite0", "lite1", "ppmuispx",
 201                                       "ppmuispmx", "mpll", "isp",
 202                                       "drc", "fd", "mcuisp",
 203                                       "ispdiv0", "ispdiv1", "mcuispdiv0",
 204                                       "mcuispdiv1", "uart", "aclk200",
 205                                       "div_aclk200", "aclk400mcuisp",
 206                                       "div_aclk400mcuisp";
 207                         #address-cells = <1>;
 208                         #size-cells = <1>;
 209                         ranges;
 210                         status = "disabled";
 211
 212                         pmu {
 213                                 reg = <0x10020000 0x3000>;
 214                         };
 215
 216                         i2c1_isp: i2c-isp@12140000 {
 217                                 compatible = "samsung,exynos4212-i2c-isp";
 218                                 reg = <0x12140000 0x100>;
 219                                 clocks = <&clock CLK_I2C1_ISP>;
 220                                 clock-names = "i2c_isp";
 221                                 #address-cells = <1>;
 222                                 #size-cells = <0>;
 223                         };
 224                 };
 225         };
 226
 227         mshc_0: mmc@12550000 {
 228                 compatible = "samsung,exynos4412-dw-mshc";
 229                 reg = <0x12550000 0x1000>;
 230                 interrupts = <0 77 0>;
 231                 #address-cells = <1>;
 232                 #size-cells = <0>;
 233                 fifo-depth = <0x80>;
 234                 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
 235                 clock-names = "biu", "ciu";
 236                 status = "disabled";
 237         };
 238 };