Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / exynos4x12.dtsi
1 /*
2  * Samsung's Exynos4x12 SoCs device tree source
3  *
4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5  *              http://www.samsung.com
6  *
7  * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
8  * based board files can include this file and provide values for board specfic
9  * bindings.
10  *
11  * Note: This file does not include device nodes for all the controllers in
12  * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
13  * nodes can be added to this file.
14  *
15  * This program is free software; you can redistribute it and/or modify
16  * it under the terms of the GNU General Public License version 2 as
17  * published by the Free Software Foundation.
18 */
19
20 #include "exynos4.dtsi"
21 #include "exynos4x12-pinctrl.dtsi"
22 #include "exynos4-cpu-thermal.dtsi"
23
24 / {
25         aliases {
26                 pinctrl0 = &pinctrl_0;
27                 pinctrl1 = &pinctrl_1;
28                 pinctrl2 = &pinctrl_2;
29                 pinctrl3 = &pinctrl_3;
30                 fimc-lite0 = &fimc_lite_0;
31                 fimc-lite1 = &fimc_lite_1;
32                 mshc0 = &mshc_0;
33         };
34
35         sysram@02020000 {
36                 compatible = "mmio-sram";
37                 reg = <0x02020000 0x40000>;
38                 #address-cells = <1>;
39                 #size-cells = <1>;
40                 ranges = <0 0x02020000 0x40000>;
41
42                 smp-sysram@0 {
43                         compatible = "samsung,exynos4210-sysram";
44                         reg = <0x0 0x1000>;
45                 };
46
47                 smp-sysram@2f000 {
48                         compatible = "samsung,exynos4210-sysram-ns";
49                         reg = <0x2f000 0x1000>;
50                 };
51         };
52
53         pd_isp: isp-power-domain@10023CA0 {
54                 compatible = "samsung,exynos4210-pd";
55                 reg = <0x10023CA0 0x20>;
56                 #power-domain-cells = <0>;
57         };
58
59         l2c: l2-cache-controller@10502000 {
60                 compatible = "arm,pl310-cache";
61                 reg = <0x10502000 0x1000>;
62                 cache-unified;
63                 cache-level = <2>;
64                 arm,tag-latency = <2 2 1>;
65                 arm,data-latency = <3 2 1>;
66                 arm,double-linefill = <1>;
67                 arm,double-linefill-incr = <0>;
68                 arm,double-linefill-wrap = <1>;
69                 arm,prefetch-drop = <1>;
70                 arm,prefetch-offset = <7>;
71         };
72
73         clock: clock-controller@10030000 {
74                 compatible = "samsung,exynos4412-clock";
75                 reg = <0x10030000 0x20000>;
76                 #clock-cells = <1>;
77         };
78
79         mct@10050000 {
80                 compatible = "samsung,exynos4412-mct";
81                 reg = <0x10050000 0x800>;
82                 interrupt-parent = <&mct_map>;
83                 interrupts = <0>, <1>, <2>, <3>, <4>;
84                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
85                 clock-names = "fin_pll", "mct";
86
87                 mct_map: mct-map {
88                         #interrupt-cells = <1>;
89                         #address-cells = <0>;
90                         #size-cells = <0>;
91                         interrupt-map = <0 &gic 0 57 0>,
92                                         <1 &combiner 12 5>,
93                                         <2 &combiner 12 6>,
94                                         <3 &combiner 12 7>,
95                                         <4 &gic 1 12 0>;
96                 };
97         };
98
99         adc: adc@126C0000 {
100                 compatible = "samsung,exynos-adc-v1";
101                 reg = <0x126C0000 0x100>;
102                 interrupt-parent = <&combiner>;
103                 interrupts = <10 3>;
104                 clocks = <&clock CLK_TSADC>;
105                 clock-names = "adc";
106                 #io-channel-cells = <1>;
107                 io-channel-ranges;
108                 samsung,syscon-phandle = <&pmu_system_controller>;
109                 status = "disabled";
110         };
111
112         g2d: g2d@10800000 {
113                 compatible = "samsung,exynos4212-g2d";
114                 reg = <0x10800000 0x1000>;
115                 interrupts = <0 89 0>;
116                 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
117                 clock-names = "sclk_fimg2d", "fimg2d";
118                 iommus = <&sysmmu_g2d>;
119                 status = "disabled";
120         };
121
122         camera {
123                 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
124                          <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
125                 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
126
127                 /* fimc_[0-3] are configured outside, under phandles */
128                 fimc_lite_0: fimc-lite@12390000 {
129                         compatible = "samsung,exynos4212-fimc-lite";
130                         reg = <0x12390000 0x1000>;
131                         interrupts = <0 105 0>;
132                         power-domains = <&pd_isp>;
133                         clocks = <&clock CLK_FIMC_LITE0>;
134                         clock-names = "flite";
135                         iommus = <&sysmmu_fimc_lite0>;
136                         status = "disabled";
137                 };
138
139                 fimc_lite_1: fimc-lite@123A0000 {
140                         compatible = "samsung,exynos4212-fimc-lite";
141                         reg = <0x123A0000 0x1000>;
142                         interrupts = <0 106 0>;
143                         power-domains = <&pd_isp>;
144                         clocks = <&clock CLK_FIMC_LITE1>;
145                         clock-names = "flite";
146                         iommus = <&sysmmu_fimc_lite1>;
147                         status = "disabled";
148                 };
149
150                 fimc_is: fimc-is@12000000 {
151                         compatible = "samsung,exynos4212-fimc-is", "simple-bus";
152                         reg = <0x12000000 0x260000>;
153                         interrupts = <0 90 0>, <0 95 0>;
154                         power-domains = <&pd_isp>;
155                         clocks = <&clock CLK_FIMC_LITE0>,
156                                  <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
157                                  <&clock CLK_PPMUISPMX>,
158                                  <&clock CLK_MOUT_MPLL_USER_T>,
159                                  <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
160                                  <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
161                                  <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
162                                  <&clock CLK_DIV_MCUISP0>,
163                                  <&clock CLK_DIV_MCUISP1>,
164                                  <&clock CLK_UART_ISP_SCLK>,
165                                  <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
166                                  <&clock CLK_ACLK400_MCUISP>,
167                                  <&clock CLK_DIV_ACLK400_MCUISP>;
168                         clock-names = "lite0", "lite1", "ppmuispx",
169                                       "ppmuispmx", "mpll", "isp",
170                                       "drc", "fd", "mcuisp",
171                                       "ispdiv0", "ispdiv1", "mcuispdiv0",
172                                       "mcuispdiv1", "uart", "aclk200",
173                                       "div_aclk200", "aclk400mcuisp",
174                                       "div_aclk400mcuisp";
175                         iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
176                                  <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
177                         iommu-names = "isp", "drc", "fd", "mcuctl";
178                         #address-cells = <1>;
179                         #size-cells = <1>;
180                         ranges;
181                         status = "disabled";
182
183                         pmu {
184                                 reg = <0x10020000 0x3000>;
185                         };
186
187                         i2c1_isp: i2c-isp@12140000 {
188                                 compatible = "samsung,exynos4212-i2c-isp";
189                                 reg = <0x12140000 0x100>;
190                                 clocks = <&clock CLK_I2C1_ISP>;
191                                 clock-names = "i2c_isp";
192                                 #address-cells = <1>;
193                                 #size-cells = <0>;
194                         };
195                 };
196         };
197
198         mshc_0: mmc@12550000 {
199                 compatible = "samsung,exynos4412-dw-mshc";
200                 reg = <0x12550000 0x1000>;
201                 interrupts = <0 77 0>;
202                 #address-cells = <1>;
203                 #size-cells = <0>;
204                 fifo-depth = <0x80>;
205                 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
206                 clock-names = "biu", "ciu";
207                 status = "disabled";
208         };
209
210         sysmmu_g2d: sysmmu@10A40000{
211                 compatible = "samsung,exynos-sysmmu";
212                 reg = <0x10A40000 0x1000>;
213                 interrupt-parent = <&combiner>;
214                 interrupts = <4 7>;
215                 clock-names = "sysmmu", "master";
216                 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
217                 #iommu-cells = <0>;
218         };
219
220         sysmmu_fimc_isp: sysmmu@12260000 {
221                 compatible = "samsung,exynos-sysmmu";
222                 reg = <0x12260000 0x1000>;
223                 interrupt-parent = <&combiner>;
224                 interrupts = <16 2>;
225                 power-domains = <&pd_isp>;
226                 clock-names = "sysmmu";
227                 clocks = <&clock CLK_SMMU_ISP>;
228                 #iommu-cells = <0>;
229         };
230
231         sysmmu_fimc_drc: sysmmu@12270000 {
232                 compatible = "samsung,exynos-sysmmu";
233                 reg = <0x12270000 0x1000>;
234                 interrupt-parent = <&combiner>;
235                 interrupts = <16 3>;
236                 power-domains = <&pd_isp>;
237                 clock-names = "sysmmu";
238                 clocks = <&clock CLK_SMMU_DRC>;
239                 #iommu-cells = <0>;
240         };
241
242         sysmmu_fimc_fd: sysmmu@122A0000 {
243                 compatible = "samsung,exynos-sysmmu";
244                 reg = <0x122A0000 0x1000>;
245                 interrupt-parent = <&combiner>;
246                 interrupts = <16 4>;
247                 power-domains = <&pd_isp>;
248                 clock-names = "sysmmu";
249                 clocks = <&clock CLK_SMMU_FD>;
250                 #iommu-cells = <0>;
251         };
252
253         sysmmu_fimc_mcuctl: sysmmu@122B0000 {
254                 compatible = "samsung,exynos-sysmmu";
255                 reg = <0x122B0000 0x1000>;
256                 interrupt-parent = <&combiner>;
257                 interrupts = <16 5>;
258                 power-domains = <&pd_isp>;
259                 clock-names = "sysmmu";
260                 clocks = <&clock CLK_SMMU_ISPCX>;
261                 #iommu-cells = <0>;
262         };
263
264         sysmmu_fimc_lite0: sysmmu@123B0000 {
265                 compatible = "samsung,exynos-sysmmu";
266                 reg = <0x123B0000 0x1000>;
267                 interrupt-parent = <&combiner>;
268                 interrupts = <16 0>;
269                 power-domains = <&pd_isp>;
270                 clock-names = "sysmmu", "master";
271                 clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>;
272                 #iommu-cells = <0>;
273         };
274
275         sysmmu_fimc_lite1: sysmmu@123C0000 {
276                 compatible = "samsung,exynos-sysmmu";
277                 reg = <0x123C0000 0x1000>;
278                 interrupt-parent = <&combiner>;
279                 interrupts = <16 1>;
280                 power-domains = <&pd_isp>;
281                 clock-names = "sysmmu", "master";
282                 clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
283                 #iommu-cells = <0>;
284         };
285 };
286
287 &combiner {
288         interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
289                      <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
290                      <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
291                      <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
292                      <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
293 };
294
295 &exynos_usbphy {
296         compatible = "samsung,exynos4x12-usb2-phy";
297         samsung,sysreg-phandle = <&sys_reg>;
298 };
299
300 &fimc_0 {
301         compatible = "samsung,exynos4212-fimc";
302         samsung,pix-limits = <4224 8192 1920 4224>;
303         samsung,mainscaler-ext;
304         samsung,isp-wb;
305         samsung,cam-if;
306 };
307
308 &fimc_1 {
309         compatible = "samsung,exynos4212-fimc";
310         samsung,pix-limits = <4224 8192 1920 4224>;
311         samsung,mainscaler-ext;
312         samsung,isp-wb;
313         samsung,cam-if;
314 };
315
316 &fimc_2 {
317         compatible = "samsung,exynos4212-fimc";
318         samsung,pix-limits = <4224 8192 1920 4224>;
319         samsung,mainscaler-ext;
320         samsung,isp-wb;
321         samsung,lcd-wb;
322         samsung,cam-if;
323 };
324
325 &fimc_3 {
326         compatible = "samsung,exynos4212-fimc";
327         samsung,pix-limits = <1920 8192 1366 1920>;
328         samsung,rotators = <0>;
329         samsung,mainscaler-ext;
330         samsung,isp-wb;
331         samsung,lcd-wb;
332 };
333
334 &hdmi {
335         compatible = "samsung,exynos4212-hdmi";
336 };
337
338 &jpeg_codec {
339         compatible = "samsung,exynos4212-jpeg";
340 };
341
342 &mixer {
343         compatible = "samsung,exynos4212-mixer";
344         clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
345         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
346                  <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
347 };
348
349 &pinctrl_0 {
350         compatible = "samsung,exynos4x12-pinctrl";
351         reg = <0x11400000 0x1000>;
352         interrupts = <0 47 0>;
353 };
354
355 &pinctrl_1 {
356         compatible = "samsung,exynos4x12-pinctrl";
357         reg = <0x11000000 0x1000>;
358         interrupts = <0 46 0>;
359
360         wakup_eint: wakeup-interrupt-controller {
361                 compatible = "samsung,exynos4210-wakeup-eint";
362                 interrupt-parent = <&gic>;
363                 interrupts = <0 32 0>;
364         };
365 };
366
367 &pinctrl_2 {
368         compatible = "samsung,exynos4x12-pinctrl";
369         reg = <0x03860000 0x1000>;
370         interrupt-parent = <&combiner>;
371         interrupts = <10 0>;
372 };
373
374 &pinctrl_3 {
375         compatible = "samsung,exynos4x12-pinctrl";
376         reg = <0x106E0000 0x1000>;
377         interrupts = <0 72 0>;
378 };
379
380 &pmu_system_controller {
381         compatible = "samsung,exynos4212-pmu", "syscon";
382         clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
383                         "clkout4", "clkout8", "clkout9";
384         clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
385                 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
386                 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
387         #clock-cells = <1>;
388 };
389
390 &tmu {
391         compatible = "samsung,exynos4412-tmu";
392         interrupt-parent = <&combiner>;
393         interrupts = <2 4>;
394         reg = <0x100C0000 0x100>;
395         clocks = <&clock 383>;
396         clock-names = "tmu_apbif";
397         status = "disabled";
398 };