Merge branch 'turbostat' of https://git.kernel.org/pub/scm/linux/kernel/git/lenb...
[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / exynos4415.dtsi
1 /*
2  * Samsung's Exynos4415 SoC device tree source
3  *
4  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5  *
6  * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415
7  * based board files can include this file and provide values for board
8  * specific bindings.
9  *
10  * Note: This file does not include device nodes for all the controllers in
11  * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional
12  * nodes can be added to this file.
13  *
14  * This program is free software; you can redistribute it and/or modify
15  * it under the terms of the GNU General Public License version 2 as
16  * published by the Free Software Foundation.
17  */
18
19 #include "skeleton.dtsi"
20 #include <dt-bindings/clock/exynos4415.h>
21 #include <dt-bindings/clock/exynos-audss-clk.h>
22
23 / {
24         compatible = "samsung,exynos4415";
25         interrupt-parent = <&gic>;
26
27         aliases {
28                 pinctrl0 = &pinctrl_0;
29                 pinctrl1 = &pinctrl_1;
30                 pinctrl2 = &pinctrl_2;
31                 mshc0 = &mshc_0;
32                 mshc1 = &mshc_1;
33                 mshc2 = &mshc_2;
34                 spi0 = &spi_0;
35                 spi1 = &spi_1;
36                 spi2 = &spi_2;
37                 i2c0 = &i2c_0;
38                 i2c1 = &i2c_1;
39                 i2c2 = &i2c_2;
40                 i2c3 = &i2c_3;
41                 i2c4 = &i2c_4;
42                 i2c5 = &i2c_5;
43                 i2c6 = &i2c_6;
44                 i2c7 = &i2c_7;
45         };
46
47         cpus {
48                 #address-cells = <1>;
49                 #size-cells = <0>;
50
51                 cpu0: cpu@a00 {
52                         device_type = "cpu";
53                         compatible = "arm,cortex-a9";
54                         reg = <0xa00>;
55                         clock-frequency = <1600000000>;
56                 };
57
58                 cpu1: cpu@a01 {
59                         device_type = "cpu";
60                         compatible = "arm,cortex-a9";
61                         reg = <0xa01>;
62                         clock-frequency = <1600000000>;
63                 };
64
65                 cpu2: cpu@a02 {
66                         device_type = "cpu";
67                         compatible = "arm,cortex-a9";
68                         reg = <0xa02>;
69                         clock-frequency = <1600000000>;
70                 };
71
72                 cpu3: cpu@a03 {
73                         device_type = "cpu";
74                         compatible = "arm,cortex-a9";
75                         reg = <0xa03>;
76                         clock-frequency = <1600000000>;
77                 };
78         };
79
80         soc: soc {
81                 compatible = "simple-bus";
82                 #address-cells = <1>;
83                 #size-cells = <1>;
84                 ranges;
85
86                 sysram@02020000 {
87                         compatible = "mmio-sram";
88                         reg = <0x02020000 0x50000>;
89                         #address-cells = <1>;
90                         #size-cells = <1>;
91                         ranges = <0 0x02020000 0x50000>;
92
93                         smp-sysram@0 {
94                                 compatible = "samsung,exynos4210-sysram";
95                                 reg = <0x0 0x1000>;
96                         };
97
98                         smp-sysram@4f000 {
99                                 compatible = "samsung,exynos4210-sysram-ns";
100                                 reg = <0x4f000 0x1000>;
101                         };
102                 };
103
104                 pinctrl_2: pinctrl@03860000 {
105                         compatible = "samsung,exynos4415-pinctrl";
106                         reg = <0x03860000 0x1000>;
107                         interrupts = <0 242 0>;
108                 };
109
110                 chipid@10000000 {
111                         compatible = "samsung,exynos4210-chipid";
112                         reg = <0x10000000 0x100>;
113                 };
114
115                 sysreg_system_controller: syscon@10010000 {
116                         compatible = "samsung,exynos4-sysreg", "syscon";
117                         reg = <0x10010000 0x400>;
118                 };
119
120                 pmu_system_controller: system-controller@10020000 {
121                         compatible = "samsung,exynos4415-pmu", "syscon";
122                         reg = <0x10020000 0x4000>;
123                 };
124
125                 mipi_phy: video-phy@10020710 {
126                         compatible = "samsung,s5pv210-mipi-video-phy";
127                         #phy-cells = <1>;
128                         syscon = <&pmu_system_controller>;
129                 };
130
131                 pd_cam: cam-power-domain@10024000 {
132                         compatible = "samsung,exynos4210-pd";
133                         reg = <0x10024000 0x20>;
134                         #power-domain-cells = <0>;
135                 };
136
137                 pd_tv: tv-power-domain@10024020 {
138                         compatible = "samsung,exynos4210-pd";
139                         reg = <0x10024020 0x20>;
140                         #power-domain-cells = <0>;
141                 };
142
143                 pd_mfc: mfc-power-domain@10024040 {
144                         compatible = "samsung,exynos4210-pd";
145                         reg = <0x10024040 0x20>;
146                         #power-domain-cells = <0>;
147                 };
148
149                 pd_g3d: g3d-power-domain@10024060 {
150                         compatible = "samsung,exynos4210-pd";
151                         reg = <0x10024060 0x20>;
152                         #power-domain-cells = <0>;
153                 };
154
155                 pd_lcd0: lcd0-power-domain@10024080 {
156                         compatible = "samsung,exynos4210-pd";
157                         reg = <0x10024080 0x20>;
158                         #power-domain-cells = <0>;
159                 };
160
161                 pd_isp0: isp0-power-domain@100240A0 {
162                         compatible = "samsung,exynos4210-pd";
163                         reg = <0x100240A0 0x20>;
164                         #power-domain-cells = <0>;
165                 };
166
167                 pd_isp1: isp1-power-domain@100240E0 {
168                         compatible = "samsung,exynos4210-pd";
169                         reg = <0x100240E0 0x20>;
170                         #power-domain-cells = <0>;
171                 };
172
173                 cmu: clock-controller@10030000 {
174                         compatible = "samsung,exynos4415-cmu";
175                         reg = <0x10030000 0x18000>;
176                         #clock-cells = <1>;
177                 };
178
179                 rtc: rtc@10070000 {
180                         compatible = "samsung,s3c6410-rtc";
181                         reg = <0x10070000 0x100>;
182                         interrupts = <0 73 0>, <0 74 0>;
183                         status = "disabled";
184                 };
185
186                 mct@10050000 {
187                         compatible = "samsung,exynos4210-mct";
188                         reg = <0x10050000 0x800>;
189                         interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
190                                      <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
191                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
192                         clock-names = "fin_pll", "mct";
193                 };
194
195                 gic: interrupt-controller@10481000 {
196                         compatible = "arm,cortex-a9-gic";
197                         #interrupt-cells = <3>;
198                         interrupt-controller;
199                         reg = <0x10481000 0x1000>,
200                               <0x10482000 0x1000>,
201                               <0x10484000 0x2000>,
202                               <0x10486000 0x2000>;
203                         interrupts = <1 9 0xf04>;
204                 };
205
206                 l2c: l2-cache-controller@10502000 {
207                         compatible = "arm,pl310-cache";
208                         reg = <0x10502000 0x1000>;
209                         cache-unified;
210                         cache-level = <2>;
211                         arm,tag-latency = <2 2 1>;
212                         arm,data-latency = <3 2 1>;
213                         arm,double-linefill = <1>;
214                         arm,double-linefill-incr = <0>;
215                         arm,double-linefill-wrap = <1>;
216                         arm,prefetch-drop = <1>;
217                         arm,prefetch-offset = <7>;
218                 };
219
220                 cmu_dmc: clock-controller@105C0000 {
221                         compatible = "samsung,exynos4415-cmu-dmc";
222                         reg = <0x105C0000 0x3000>;
223                         #clock-cells = <1>;
224                 };
225
226                 pinctrl_1: pinctrl@11000000 {
227                         compatible = "samsung,exynos4415-pinctrl";
228                         reg = <0x11000000 0x1000>;
229                         interrupts = <0 225 0>;
230
231                         wakeup-interrupt-controller {
232                                 compatible = "samsung,exynos4210-wakeup-eint";
233                                 interrupt-parent = <&gic>;
234                                 interrupts = <0 48 0>;
235                         };
236                 };
237
238                 pinctrl_0: pinctrl@11400000 {
239                         compatible = "samsung,exynos4415-pinctrl";
240                         reg = <0x11400000 0x1000>;
241                         interrupts = <0 240 0>;
242                 };
243
244                 fimd: fimd@11C00000 {
245                         compatible = "samsung,exynos4415-fimd";
246                         reg = <0x11C00000 0x30000>;
247                         interrupt-names = "fifo", "vsync", "lcd_sys";
248                         interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
249                         clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
250                         clock-names = "sclk_fimd", "fimd";
251                         samsung,power-domain = <&pd_lcd0>;
252                         iommus = <&sysmmu_fimd0>;
253                         samsung,sysreg = <&sysreg_system_controller>;
254                         status = "disabled";
255                 };
256
257                 dsi_0: dsi@11C80000 {
258                         compatible = "samsung,exynos4415-mipi-dsi";
259                         reg = <0x11C80000 0x10000>;
260                         interrupts = <0 83 0>;
261                         samsung,phy-type = <0>;
262                         samsung,power-domain = <&pd_lcd0>;
263                         phys = <&mipi_phy 1>;
264                         phy-names = "dsim";
265                         clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
266                         clock-names = "bus_clk", "pll_clk";
267                         #address-cells = <1>;
268                         #size-cells = <0>;
269                         status = "disabled";
270                 };
271
272                 sysmmu_fimd0: sysmmu@11E20000 {
273                         compatible = "samsung,exynos-sysmmu";
274                         reg = <0x11e20000 0x1000>;
275                         interrupts = <0 80 0>, <0 81 0>;
276                         clock-names = "sysmmu", "master";
277                         clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
278                         power-domains = <&pd_lcd0>;
279                         #iommu-cells = <0>;
280                 };
281
282                 hsotg: hsotg@12480000 {
283                         compatible = "samsung,s3c6400-hsotg";
284                         reg = <0x12480000 0x20000>;
285                         interrupts = <0 141 0>;
286                         clocks = <&cmu CLK_USBDEVICE>;
287                         clock-names = "otg";
288                         phys = <&exynos_usbphy 0>;
289                         phy-names = "usb2-phy";
290                         status = "disabled";
291                 };
292
293                 mshc_0: mshc@12510000 {
294                         compatible = "samsung,exynos5250-dw-mshc";
295                         reg = <0x12510000 0x1000>;
296                         interrupts = <0 142 0>;
297                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
298                         clock-names = "biu", "ciu";
299                         fifo-depth = <0x80>;
300                         #address-cells = <1>;
301                         #size-cells = <0>;
302                         status = "disabled";
303                 };
304
305                 mshc_1: mshc@12520000 {
306                         compatible = "samsung,exynos5250-dw-mshc";
307                         reg = <0x12520000 0x1000>;
308                         interrupts = <0 143 0>;
309                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
310                         clock-names = "biu", "ciu";
311                         fifo-depth = <0x80>;
312                         #address-cells = <1>;
313                         #size-cells = <0>;
314                         status = "disabled";
315                 };
316
317                 mshc_2: mshc@12530000 {
318                         compatible = "samsung,exynos5250-dw-mshc";
319                         reg = <0x12530000 0x1000>;
320                         interrupts = <0 144 0>;
321                         clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
322                         clock-names = "biu", "ciu";
323                         fifo-depth = <0x80>;
324                         #address-cells = <1>;
325                         #size-cells = <0>;
326                         status = "disabled";
327                 };
328
329                 ehci: ehci@12580000 {
330                         compatible = "samsung,exynos4210-ehci";
331                         reg = <0x12580000 0x100>;
332                         interrupts = <0 140 0>;
333                         clocks = <&cmu CLK_USBHOST>;
334                         clock-names = "usbhost";
335                         status = "disabled";
336                         #address-cells = <1>;
337                         #size-cells = <0>;
338                         port@0 {
339                                 reg = <0>;
340                                 phys = <&exynos_usbphy 1>;
341                                 status = "disabled";
342                         };
343                         port@1 {
344                                 reg = <1>;
345                                 phys = <&exynos_usbphy 2>;
346                                 status = "disabled";
347                         };
348                         port@2 {
349                                 reg = <2>;
350                                 phys = <&exynos_usbphy 3>;
351                                 status = "disabled";
352                         };
353                 };
354
355                 ohci: ohci@12590000 {
356                         compatible = "samsung,exynos4210-ohci";
357                         reg = <0x12590000 0x100>;
358                         interrupts = <0 140 0>;
359                         clocks = <&cmu CLK_USBHOST>;
360                         clock-names = "usbhost";
361                         status = "disabled";
362                         #address-cells = <1>;
363                         #size-cells = <0>;
364                         port@0 {
365                                 reg = <0>;
366                                 phys = <&exynos_usbphy 1>;
367                                 status = "disabled";
368                         };
369                 };
370
371                 exynos_usbphy: exynos-usbphy@125B0000 {
372                         compatible = "samsung,exynos4x12-usb2-phy";
373                         reg = <0x125B0000 0x100>;
374                         samsung,pmureg-phandle = <&pmu_system_controller>;
375                         samsung,sysreg-phandle = <&sysreg_system_controller>;
376                         clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>;
377                         clock-names = "phy", "ref";
378                         #phy-cells = <1>;
379                         status = "disabled";
380                 };
381
382                 amba {
383                         compatible = "arm,amba-bus";
384                         #address-cells = <1>;
385                         #size-cells = <1>;
386                         interrupt-parent = <&gic>;
387                         ranges;
388
389                         pdma0: pdma@12680000 {
390                                 compatible = "arm,pl330", "arm,primecell";
391                                 reg = <0x12680000 0x1000>;
392                                 interrupts = <0 138 0>;
393                                 clocks = <&cmu CLK_PDMA0>;
394                                 clock-names = "apb_pclk";
395                                 #dma-cells = <1>;
396                                 #dma-channels = <8>;
397                                 #dma-requests = <32>;
398                         };
399
400                         pdma1: pdma@12690000 {
401                                 compatible = "arm,pl330", "arm,primecell";
402                                 reg = <0x12690000 0x1000>;
403                                 interrupts = <0 139 0>;
404                                 clocks = <&cmu CLK_PDMA1>;
405                                 clock-names = "apb_pclk";
406                                 #dma-cells = <1>;
407                                 #dma-channels = <8>;
408                                 #dma-requests = <32>;
409                         };
410                 };
411
412                 adc: adc@126C0000 {
413                         compatible = "samsung,exynos3250-adc",
414                                      "samsung,exynos-adc-v2";
415                         reg = <0x126C0000 0x100>, <0x10020718 0x4>;
416                         interrupts = <0 137 0>;
417                         clock-names = "adc", "sclk";
418                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
419                         #io-channel-cells = <1>;
420                         io-channel-ranges;
421                         status = "disabled";
422                 };
423
424                 serial_0: serial@13800000 {
425                         compatible = "samsung,exynos4210-uart";
426                         reg = <0x13800000 0x100>;
427                         interrupts = <0 109 0>;
428                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
429                         clock-names = "uart", "clk_uart_baud0";
430                         status = "disabled";
431                 };
432
433                 serial_1: serial@13810000 {
434                         compatible = "samsung,exynos4210-uart";
435                         reg = <0x13810000 0x100>;
436                         interrupts = <0 110 0>;
437                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
438                         clock-names = "uart", "clk_uart_baud0";
439                         status = "disabled";
440                 };
441
442                 serial_2: serial@13820000 {
443                         compatible = "samsung,exynos4210-uart";
444                         reg = <0x13820000 0x100>;
445                         interrupts = <0 111 0>;
446                         clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
447                         clock-names = "uart", "clk_uart_baud0";
448                         status = "disabled";
449                 };
450
451                 serial_3: serial@13830000 {
452                         compatible = "samsung,exynos4210-uart";
453                         reg = <0x13830000 0x100>;
454                         interrupts = <0 112 0>;
455                         clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>;
456                         clock-names = "uart", "clk_uart_baud0";
457                         status = "disabled";
458                 };
459
460                 i2c_0: i2c@13860000 {
461                         #address-cells = <1>;
462                         #size-cells = <0>;
463                         compatible = "samsung,s3c2440-i2c";
464                         reg = <0x13860000 0x100>;
465                         interrupts = <0 113 0>;
466                         clocks = <&cmu CLK_I2C0>;
467                         clock-names = "i2c";
468                         pinctrl-names = "default";
469                         pinctrl-0 = <&i2c0_bus>;
470                         status = "disabled";
471                 };
472
473                 i2c_1: i2c@13870000 {
474                         #address-cells = <1>;
475                         #size-cells = <0>;
476                         compatible = "samsung,s3c2440-i2c";
477                         reg = <0x13870000 0x100>;
478                         interrupts = <0 114 0>;
479                         clocks = <&cmu CLK_I2C1>;
480                         clock-names = "i2c";
481                         pinctrl-names = "default";
482                         pinctrl-0 = <&i2c1_bus>;
483                         status = "disabled";
484                 };
485
486                 i2c_2: i2c@13880000 {
487                         #address-cells = <1>;
488                         #size-cells = <0>;
489                         compatible = "samsung,s3c2440-i2c";
490                         reg = <0x13880000 0x100>;
491                         interrupts = <0 115 0>;
492                         clocks = <&cmu CLK_I2C2>;
493                         clock-names = "i2c";
494                         pinctrl-names = "default";
495                         pinctrl-0 = <&i2c2_bus>;
496                         status = "disabled";
497                 };
498
499                 i2c_3: i2c@13890000 {
500                         #address-cells = <1>;
501                         #size-cells = <0>;
502                         compatible = "samsung,s3c2440-i2c";
503                         reg = <0x13890000 0x100>;
504                         interrupts = <0 116 0>;
505                         clocks = <&cmu CLK_I2C3>;
506                         clock-names = "i2c";
507                         pinctrl-names = "default";
508                         pinctrl-0 = <&i2c3_bus>;
509                         status = "disabled";
510                 };
511
512                 i2c_4: i2c@138A0000 {
513                         #address-cells = <1>;
514                         #size-cells = <0>;
515                         compatible = "samsung,s3c2440-i2c";
516                         reg = <0x138A0000 0x100>;
517                         interrupts = <0 117 0>;
518                         clocks = <&cmu CLK_I2C4>;
519                         clock-names = "i2c";
520                         pinctrl-names = "default";
521                         pinctrl-0 = <&i2c4_bus>;
522                         status = "disabled";
523                 };
524
525                 i2c_5: i2c@138B0000 {
526                         #address-cells = <1>;
527                         #size-cells = <0>;
528                         compatible = "samsung,s3c2440-i2c";
529                         reg = <0x138B0000 0x100>;
530                         interrupts = <0 118 0>;
531                         clocks = <&cmu CLK_I2C5>;
532                         clock-names = "i2c";
533                         pinctrl-names = "default";
534                         pinctrl-0 = <&i2c5_bus>;
535                         status = "disabled";
536                 };
537
538                 i2c_6: i2c@138C0000 {
539                         #address-cells = <1>;
540                         #size-cells = <0>;
541                         compatible = "samsung,s3c2440-i2c";
542                         reg = <0x138C0000 0x100>;
543                         interrupts = <0 119 0>;
544                         clocks = <&cmu CLK_I2C6>;
545                         clock-names = "i2c";
546                         pinctrl-names = "default";
547                         pinctrl-0 = <&i2c6_bus>;
548                         status = "disabled";
549                 };
550
551                 i2c_7: i2c@138D0000 {
552                         #address-cells = <1>;
553                         #size-cells = <0>;
554                         compatible = "samsung,s3c2440-i2c";
555                         reg = <0x138D0000 0x100>;
556                         interrupts = <0 120 0>;
557                         clocks = <&cmu CLK_I2C7>;
558                         clock-names = "i2c";
559                         pinctrl-names = "default";
560                         pinctrl-0 = <&i2c7_bus>;
561                         status = "disabled";
562                 };
563
564                 spi_0: spi@13920000 {
565                         compatible = "samsung,exynos4210-spi";
566                         reg = <0x13920000 0x100>;
567                         interrupts = <0 121 0>;
568                         dmas = <&pdma0 7>, <&pdma0 6>;
569                         dma-names = "tx", "rx";
570                         #address-cells = <1>;
571                         #size-cells = <0>;
572                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
573                         clock-names = "spi", "spi_busclk0";
574                         samsung,spi-src-clk = <0>;
575                         pinctrl-names = "default";
576                         pinctrl-0 = <&spi0_bus>;
577                         status = "disabled";
578                 };
579
580                 spi_1: spi@13930000 {
581                         compatible = "samsung,exynos4210-spi";
582                         reg = <0x13930000 0x100>;
583                         interrupts = <0 122 0>;
584                         dmas = <&pdma1 7>, <&pdma1 6>;
585                         dma-names = "tx", "rx";
586                         #address-cells = <1>;
587                         #size-cells = <0>;
588                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
589                         clock-names = "spi", "spi_busclk0";
590                         samsung,spi-src-clk = <0>;
591                         pinctrl-names = "default";
592                         pinctrl-0 = <&spi1_bus>;
593                         status = "disabled";
594                 };
595
596                 spi_2: spi@13940000 {
597                         compatible = "samsung,exynos4210-spi";
598                         reg = <0x13940000 0x100>;
599                         interrupts = <0 123 0>;
600                         dmas = <&pdma0 9>, <&pdma0 8>;
601                         dma-names = "tx", "rx";
602                         #address-cells = <1>;
603                         #size-cells = <0>;
604                         clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>;
605                         clock-names = "spi", "spi_busclk0";
606                         samsung,spi-src-clk = <0>;
607                         pinctrl-names = "default";
608                         pinctrl-0 = <&spi2_bus>;
609                         status = "disabled";
610                 };
611
612                 clock_audss: clock-controller@03810000 {
613                         compatible = "samsung,exynos4210-audss-clock";
614                         reg = <0x03810000 0x0C>;
615                         #clock-cells = <1>;
616                 };
617
618                 i2s0: i2s@3830000 {
619                         compatible = "samsung,s5pv210-i2s";
620                         reg = <0x03830000 0x100>;
621                         interrupts = <0 124 0>;
622                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
623                                 <&clock_audss EXYNOS_SCLK_I2S>;
624                         clock-names = "iis", "i2s_opclk0";
625                         dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>;
626                         dma-names = "tx", "rx", "tx-sec";
627                         pinctrl-names = "default";
628                         pinctrl-0 = <&i2s0_bus>;
629                         samsung,idma-addr = <0x03000000>;
630                         status = "disabled";
631                 };
632
633                 pwm: pwm@139D0000 {
634                         compatible = "samsung,exynos4210-pwm";
635                         reg = <0x139D0000 0x1000>;
636                         interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
637                                      <0 107 0>, <0 108 0>;
638                         #pwm-cells = <3>;
639                         status = "disabled";
640                 };
641
642                 pmu {
643                         compatible = "arm,cortex-a9-pmu";
644                         interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
645                 };
646         };
647 };
648
649 #include "exynos4415-pinctrl.dtsi"