arch/arm/boot/dts/exynos4210.dtsi

   1 /*
   2  * Samsung's Exynos4210 SoC device tree source
   3  *
   4  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  * Copyright (c) 2010-2011 Linaro Ltd.
   7  *              www.linaro.org
   8  *
   9  * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
  10  * based board files can include this file and provide values for board specfic
  11  * bindings.
  12  *
  13  * Note: This file does not include device nodes for all the controllers in
  14  * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
  15  * nodes can be added to this file.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20 */
  21
  22 #include "exynos4.dtsi"
  23 #include "exynos4210-pinctrl.dtsi"
  24
  25 / {
  26         compatible = "samsung,exynos4210", "samsung,exynos4";
  27
  28         aliases {
  29                 pinctrl0 = &pinctrl_0;
  30                 pinctrl1 = &pinctrl_1;
  31                 pinctrl2 = &pinctrl_2;
  32         };
  33
  34         pmu_system_controller: system-controller@10020000 {
  35                 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
  36                                 "clkout4", "clkout8", "clkout9";
  37                 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
  38                         <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
  39                         <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
  40                         <&clock CLK_XUSBXTI>;
  41                 #clock-cells = <1>;
  42         };
  43
  44         sysram@02020000 {
  45                 compatible = "mmio-sram";
  46                 reg = <0x02020000 0x20000>;
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49                 ranges = <0 0x02020000 0x20000>;
  50
  51                 smp-sysram@0 {
  52                         compatible = "samsung,exynos4210-sysram";
  53                         reg = <0x0 0x1000>;
  54                 };
  55
  56                 smp-sysram@1f000 {
  57                         compatible = "samsung,exynos4210-sysram-ns";
  58                         reg = <0x1f000 0x1000>;
  59                 };
  60         };
  61
  62         pd_lcd1: lcd1-power-domain@10023CA0 {
  63                 compatible = "samsung,exynos4210-pd";
  64                 reg = <0x10023CA0 0x20>;
  65         };
  66
  67         gic: interrupt-controller@10490000 {
  68                 cpu-offset = <0x8000>;
  69         };
  70
  71         combiner: interrupt-controller@10440000 {
  72                 samsung,combiner-nr = <16>;
  73                 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
  74                              <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
  75                              <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
  76                              <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
  77         };
  78
  79         mct@10050000 {
  80                 compatible = "samsung,exynos4210-mct";
  81                 reg = <0x10050000 0x800>;
  82                 interrupt-parent = <&mct_map>;
  83                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
  84                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
  85                 clock-names = "fin_pll", "mct";
  86
  87                 mct_map: mct-map {
  88                         #interrupt-cells = <1>;
  89                         #address-cells = <0>;
  90                         #size-cells = <0>;
  91                         interrupt-map = <0 &gic 0 57 0>,
  92                                         <1 &gic 0 69 0>,
  93                                         <2 &combiner 12 6>,
  94                                         <3 &combiner 12 7>,
  95                                         <4 &gic 0 42 0>,
  96                                         <5 &gic 0 48 0>;
  97                 };
  98         };
  99
 100         clock: clock-controller@10030000 {
 101                 compatible = "samsung,exynos4210-clock";
 102                 reg = <0x10030000 0x20000>;
 103                 #clock-cells = <1>;
 104         };
 105
 106         pinctrl_0: pinctrl@11400000 {
 107                 compatible = "samsung,exynos4210-pinctrl";
 108                 reg = <0x11400000 0x1000>;
 109                 interrupts = <0 47 0>;
 110         };
 111
 112         pinctrl_1: pinctrl@11000000 {
 113                 compatible = "samsung,exynos4210-pinctrl";
 114                 reg = <0x11000000 0x1000>;
 115                 interrupts = <0 46 0>;
 116
 117                 wakup_eint: wakeup-interrupt-controller {
 118                         compatible = "samsung,exynos4210-wakeup-eint";
 119                         interrupt-parent = <&gic>;
 120                         interrupts = <0 32 0>;
 121                 };
 122         };
 123
 124         pinctrl_2: pinctrl@03860000 {
 125                 compatible = "samsung,exynos4210-pinctrl";
 126                 reg = <0x03860000 0x1000>;
 127         };
 128
 129         tmu@100C0000 {
 130                 compatible = "samsung,exynos4210-tmu";
 131                 interrupt-parent = <&combiner>;
 132                 reg = <0x100C0000 0x100>;
 133                 interrupts = <2 4>;
 134                 clocks = <&clock CLK_TMU_APBIF>;
 135                 clock-names = "tmu_apbif";
 136                 status = "disabled";
 137         };
 138
 139         g2d@12800000 {
 140                 compatible = "samsung,s5pv210-g2d";
 141                 reg = <0x12800000 0x1000>;
 142                 interrupts = <0 89 0>;
 143                 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
 144                 clock-names = "sclk_fimg2d", "fimg2d";
 145                 status = "disabled";
 146         };
 147
 148         camera {
 149                 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
 150                          <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
 151                 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
 152
 153                 fimc_0: fimc@11800000 {
 154                         samsung,pix-limits = <4224 8192 1920 4224>;
 155                         samsung,mainscaler-ext;
 156                         samsung,cam-if;
 157                 };
 158
 159                 fimc_1: fimc@11810000 {
 160                         samsung,pix-limits = <4224 8192 1920 4224>;
 161                         samsung,mainscaler-ext;
 162                         samsung,cam-if;
 163                 };
 164
 165                 fimc_2: fimc@11820000 {
 166                         samsung,pix-limits = <4224 8192 1920 4224>;
 167                         samsung,mainscaler-ext;
 168                         samsung,lcd-wb;
 169                 };
 170
 171                 fimc_3: fimc@11830000 {
 172                         samsung,pix-limits = <1920 8192 1366 1920>;
 173                         samsung,rotators = <0>;
 174                         samsung,mainscaler-ext;
 175                         samsung,lcd-wb;
 176                 };
 177         };
 178 };