2 * Samsung's Exynos4210 SoC device tree source
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
10 * based board files can include this file and provide values for board specfic
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
15 * nodes can be added to this file.
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
22 #include "exynos4.dtsi"
23 #include "exynos4210-pinctrl.dtsi"
24 #include "exynos4-cpu-thermal.dtsi"
27 compatible = "samsung,exynos4210", "samsung,exynos4";
30 pinctrl0 = &pinctrl_0;
31 pinctrl1 = &pinctrl_1;
32 pinctrl2 = &pinctrl_2;
41 compatible = "arm,cortex-a9";
43 cooling-min-level = <4>;
44 cooling-max-level = <2>;
45 #cooling-cells = <2>; /* min followed by max */
50 compatible = "arm,cortex-a9";
55 sysram: sysram@02020000 {
56 compatible = "mmio-sram";
57 reg = <0x02020000 0x20000>;
60 ranges = <0 0x02020000 0x20000>;
63 compatible = "samsung,exynos4210-sysram";
68 compatible = "samsung,exynos4210-sysram-ns";
69 reg = <0x1f000 0x1000>;
73 pd_lcd1: lcd1-power-domain@10023CA0 {
74 compatible = "samsung,exynos4210-pd";
75 reg = <0x10023CA0 0x20>;
76 #power-domain-cells = <0>;
79 l2c: l2-cache-controller@10502000 {
80 compatible = "arm,pl310-cache";
81 reg = <0x10502000 0x1000>;
84 arm,tag-latency = <2 2 1>;
85 arm,data-latency = <2 2 1>;
89 compatible = "samsung,exynos4210-mct";
90 reg = <0x10050000 0x800>;
91 interrupt-parent = <&mct_map>;
92 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
93 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
94 clock-names = "fin_pll", "mct";
97 #interrupt-cells = <1>;
100 interrupt-map = <0 &gic 0 57 0>,
109 clock: clock-controller@10030000 {
110 compatible = "samsung,exynos4210-clock";
111 reg = <0x10030000 0x20000>;
115 pinctrl_0: pinctrl@11400000 {
116 compatible = "samsung,exynos4210-pinctrl";
117 reg = <0x11400000 0x1000>;
118 interrupts = <0 47 0>;
121 pinctrl_1: pinctrl@11000000 {
122 compatible = "samsung,exynos4210-pinctrl";
123 reg = <0x11000000 0x1000>;
124 interrupts = <0 46 0>;
126 wakup_eint: wakeup-interrupt-controller {
127 compatible = "samsung,exynos4210-wakeup-eint";
128 interrupt-parent = <&gic>;
129 interrupts = <0 32 0>;
133 pinctrl_2: pinctrl@03860000 {
134 compatible = "samsung,exynos4210-pinctrl";
135 reg = <0x03860000 0x1000>;
139 compatible = "samsung,exynos4210-tmu";
140 interrupt-parent = <&combiner>;
141 reg = <0x100C0000 0x100>;
143 clocks = <&clock CLK_TMU_APBIF>;
144 clock-names = "tmu_apbif";
145 samsung,tmu_gain = <15>;
146 samsung,tmu_reference_voltage = <7>;
151 cpu_thermal: cpu-thermal {
152 polling-delay-passive = <0>;
154 thermal-sensors = <&tmu 0>;
157 cpu_alert0: cpu-alert-0 {
158 temperature = <85000>; /* millicelsius */
160 cpu_alert1: cpu-alert-1 {
161 temperature = <100000>; /* millicelsius */
163 cpu_alert2: cpu-alert-2 {
164 temperature = <110000>; /* millicelsius */
171 compatible = "samsung,s5pv210-g2d";
172 reg = <0x12800000 0x1000>;
173 interrupts = <0 89 0>;
174 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
175 clock-names = "sclk_fimg2d", "fimg2d";
176 iommus = <&sysmmu_g2d>;
181 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
182 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
183 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
185 fimc_0: fimc@11800000 {
186 samsung,pix-limits = <4224 8192 1920 4224>;
187 samsung,mainscaler-ext;
191 fimc_1: fimc@11810000 {
192 samsung,pix-limits = <4224 8192 1920 4224>;
193 samsung,mainscaler-ext;
197 fimc_2: fimc@11820000 {
198 samsung,pix-limits = <4224 8192 1920 4224>;
199 samsung,mainscaler-ext;
203 fimc_3: fimc@11830000 {
204 samsung,pix-limits = <1920 8192 1366 1920>;
205 samsung,rotators = <0>;
206 samsung,mainscaler-ext;
211 mixer: mixer@12C10000 {
212 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
214 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
215 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
216 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
219 ppmu_lcd1: ppmu_lcd1@12240000 {
220 compatible = "samsung,exynos-ppmu";
221 reg = <0x12240000 0x2000>;
222 clocks = <&clock CLK_PPMULCD1>;
223 clock-names = "ppmu";
227 sysmmu_g2d: sysmmu@12A20000 {
228 compatible = "samsung,exynos-sysmmu";
229 reg = <0x12A20000 0x1000>;
230 interrupt-parent = <&combiner>;
232 clock-names = "sysmmu", "master";
233 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
234 power-domains = <&pd_lcd0>;
238 sysmmu_fimd1: sysmmu@12220000 {
239 compatible = "samsung,exynos-sysmmu";
240 interrupt-parent = <&combiner>;
241 reg = <0x12220000 0x1000>;
243 clock-names = "sysmmu", "master";
244 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
245 power-domains = <&pd_lcd1>;
251 cpu-offset = <0x8000>;
255 samsung,combiner-nr = <16>;
256 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
257 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
258 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
259 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
262 &pmu_system_controller {
263 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
264 "clkout4", "clkout8", "clkout9";
265 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
266 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
267 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;