arch/arm/boot/dts/exynos3250.dtsi

   1 /*
   2  * Samsung's Exynos3250 SoC device tree source
   3  *
   4  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include "skeleton.dtsi"
  21 #include "exynos4-cpu-thermal.dtsi"
  22 #include <dt-bindings/clock/exynos3250.h>
  23
  24 / {
  25         compatible = "samsung,exynos3250";
  26         interrupt-parent = <&gic>;
  27
  28         aliases {
  29                 pinctrl0 = &pinctrl_0;
  30                 pinctrl1 = &pinctrl_1;
  31                 mshc0 = &mshc_0;
  32                 mshc1 = &mshc_1;
  33                 spi0 = &spi_0;
  34                 spi1 = &spi_1;
  35                 i2c0 = &i2c_0;
  36                 i2c1 = &i2c_1;
  37                 i2c2 = &i2c_2;
  38                 i2c3 = &i2c_3;
  39                 i2c4 = &i2c_4;
  40                 i2c5 = &i2c_5;
  41                 i2c6 = &i2c_6;
  42                 i2c7 = &i2c_7;
  43                 serial0 = &serial_0;
  44                 serial1 = &serial_1;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50
  51                 cpu0: cpu@0 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a7";
  54                         reg = <0>;
  55                         clock-frequency = <1000000000>;
  56                 };
  57
  58                 cpu1: cpu@1 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a7";
  61                         reg = <1>;
  62                         clock-frequency = <1000000000>;
  63                 };
  64         };
  65
  66         soc: soc {
  67                 compatible = "simple-bus";
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 ranges;
  71
  72                 fixed-rate-clocks {
  73                         #address-cells = <1>;
  74                         #size-cells = <0>;
  75
  76                         xusbxti: clock@0 {
  77                                 compatible = "fixed-clock";
  78                                 #address-cells = <1>;
  79                                 #size-cells = <0>;
  80                                 reg = <0>;
  81                                 clock-frequency = <0>;
  82                                 #clock-cells = <0>;
  83                                 clock-output-names = "xusbxti";
  84                         };
  85
  86                         xxti: clock@1 {
  87                                 compatible = "fixed-clock";
  88                                 reg = <1>;
  89                                 clock-frequency = <0>;
  90                                 #clock-cells = <0>;
  91                                 clock-output-names = "xxti";
  92                         };
  93
  94                         xtcxo: clock@2 {
  95                                 compatible = "fixed-clock";
  96                                 reg = <2>;
  97                                 clock-frequency = <0>;
  98                                 #clock-cells = <0>;
  99                                 clock-output-names = "xtcxo";
 100                         };
 101                 };
 102
 103                 sysram@02020000 {
 104                         compatible = "mmio-sram";
 105                         reg = <0x02020000 0x40000>;
 106                         #address-cells = <1>;
 107                         #size-cells = <1>;
 108                         ranges = <0 0x02020000 0x40000>;
 109
 110                         smp-sysram@0 {
 111                                 compatible = "samsung,exynos4210-sysram";
 112                                 reg = <0x0 0x1000>;
 113                         };
 114
 115                         smp-sysram@3f000 {
 116                                 compatible = "samsung,exynos4210-sysram-ns";
 117                                 reg = <0x3f000 0x1000>;
 118                         };
 119                 };
 120
 121                 chipid@10000000 {
 122                         compatible = "samsung,exynos4210-chipid";
 123                         reg = <0x10000000 0x100>;
 124                 };
 125
 126                 sys_reg: syscon@10010000 {
 127                         compatible = "samsung,exynos3-sysreg", "syscon";
 128                         reg = <0x10010000 0x400>;
 129                 };
 130
 131                 pmu_system_controller: system-controller@10020000 {
 132                         compatible = "samsung,exynos3250-pmu", "syscon";
 133                         reg = <0x10020000 0x4000>;
 134                         interrupt-controller;
 135                         #interrupt-cells = <3>;
 136                         interrupt-parent = <&gic>;
 137                 };
 138
 139                 mipi_phy: video-phy@10020710 {
 140                         compatible = "samsung,s5pv210-mipi-video-phy";
 141                         reg = <0x10020710 8>;
 142                         #phy-cells = <1>;
 143                 };
 144
 145                 pd_cam: cam-power-domain@10023C00 {
 146                         compatible = "samsung,exynos4210-pd";
 147                         reg = <0x10023C00 0x20>;
 148                         #power-domain-cells = <0>;
 149                 };
 150
 151                 pd_mfc: mfc-power-domain@10023C40 {
 152                         compatible = "samsung,exynos4210-pd";
 153                         reg = <0x10023C40 0x20>;
 154                         #power-domain-cells = <0>;
 155                 };
 156
 157                 pd_g3d: g3d-power-domain@10023C60 {
 158                         compatible = "samsung,exynos4210-pd";
 159                         reg = <0x10023C60 0x20>;
 160                         #power-domain-cells = <0>;
 161                 };
 162
 163                 pd_lcd0: lcd0-power-domain@10023C80 {
 164                         compatible = "samsung,exynos4210-pd";
 165                         reg = <0x10023C80 0x20>;
 166                         #power-domain-cells = <0>;
 167                 };
 168
 169                 pd_isp: isp-power-domain@10023CA0 {
 170                         compatible = "samsung,exynos4210-pd";
 171                         reg = <0x10023CA0 0x20>;
 172                         #power-domain-cells = <0>;
 173                 };
 174
 175                 cmu: clock-controller@10030000 {
 176                         compatible = "samsung,exynos3250-cmu";
 177                         reg = <0x10030000 0x20000>;
 178                         #clock-cells = <1>;
 179                         assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
 180                                           <&cmu CLK_MOUT_ACLK_266_SUB>;
 181                         assigned-clock-parents = <&cmu CLK_FIN_PLL>,
 182                                                  <&cmu CLK_FIN_PLL>;
 183                 };
 184
 185                 cmu_dmc: clock-controller@105C0000 {
 186                         compatible = "samsung,exynos3250-cmu-dmc";
 187                         reg = <0x105C0000 0x2000>;
 188                         #clock-cells = <1>;
 189                 };
 190
 191                 rtc: rtc@10070000 {
 192                         compatible = "samsung,s3c6410-rtc";
 193                         reg = <0x10070000 0x100>;
 194                         interrupts = <0 73 0>, <0 74 0>;
 195                         interrupt-parent = <&pmu_system_controller>;
 196                         status = "disabled";
 197                 };
 198
 199                 tmu: tmu@100C0000 {
 200                         compatible = "samsung,exynos3250-tmu";
 201                         reg = <0x100C0000 0x100>;
 202                         interrupts = <0 216 0>;
 203                         clocks = <&cmu CLK_TMU_APBIF>;
 204                         clock-names = "tmu_apbif";
 205                         #include "exynos4412-tmu-sensor-conf.dtsi"
 206                         status = "disabled";
 207                 };
 208
 209                 gic: interrupt-controller@10481000 {
 210                         compatible = "arm,cortex-a15-gic";
 211                         #interrupt-cells = <3>;
 212                         interrupt-controller;
 213                         reg = <0x10481000 0x1000>,
 214                               <0x10482000 0x1000>,
 215                               <0x10484000 0x2000>,
 216                               <0x10486000 0x2000>;
 217                         interrupts = <1 9 0xf04>;
 218                 };
 219
 220                 mct@10050000 {
 221                         compatible = "samsung,exynos4210-mct";
 222                         reg = <0x10050000 0x800>;
 223                         interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
 224                                      <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
 225                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
 226                         clock-names = "fin_pll", "mct";
 227                 };
 228
 229                 pinctrl_1: pinctrl@11000000 {
 230                         compatible = "samsung,exynos3250-pinctrl";
 231                         reg = <0x11000000 0x1000>;
 232                         interrupts = <0 225 0>;
 233
 234                         wakeup-interrupt-controller {
 235                                 compatible = "samsung,exynos4210-wakeup-eint";
 236                                 interrupts = <0 48 0>;
 237                         };
 238                 };
 239
 240                 pinctrl_0: pinctrl@11400000 {
 241                         compatible = "samsung,exynos3250-pinctrl";
 242                         reg = <0x11400000 0x1000>;
 243                         interrupts = <0 240 0>;
 244                 };
 245
 246                 jpeg: codec@11830000 {
 247                         compatible = "samsung,exynos3250-jpeg";
 248                         reg = <0x11830000 0x1000>;
 249                         interrupts = <0 171 0>;
 250                         clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
 251                         clock-names = "jpeg", "sclk";
 252                         power-domains = <&pd_cam>;
 253                         assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
 254                         assigned-clock-rates = <0>, <150000000>;
 255                         assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
 256                         status = "disabled";
 257                 };
 258
 259                 fimd: fimd@11c00000 {
 260                         compatible = "samsung,exynos3250-fimd";
 261                         reg = <0x11c00000 0x30000>;
 262                         interrupt-names = "fifo", "vsync", "lcd_sys";
 263                         interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
 264                         clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
 265                         clock-names = "sclk_fimd", "fimd";
 266                         power-domains = <&pd_lcd0>;
 267                         samsung,sysreg = <&sys_reg>;
 268                         status = "disabled";
 269                 };
 270
 271                 dsi_0: dsi@11C80000 {
 272                         compatible = "samsung,exynos3250-mipi-dsi";
 273                         reg = <0x11C80000 0x10000>;
 274                         interrupts = <0 83 0>;
 275                         samsung,phy-type = <0>;
 276                         power-domains = <&pd_lcd0>;
 277                         phys = <&mipi_phy 1>;
 278                         phy-names = "dsim";
 279                         clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
 280                         clock-names = "bus_clk", "pll_clk";
 281                         #address-cells = <1>;
 282                         #size-cells = <0>;
 283                         status = "disabled";
 284                 };
 285
 286                 hsotg: hsotg@12480000 {
 287                         compatible = "snps,dwc2";
 288                         reg = <0x12480000 0x20000>;
 289                         interrupts = <0 141 0>;
 290                         clocks = <&cmu CLK_USBOTG>;
 291                         clock-names = "otg";
 292                         phys = <&exynos_usbphy 0>;
 293                         phy-names = "usb2-phy";
 294                         status = "disabled";
 295                 };
 296
 297                 mshc_0: mshc@12510000 {
 298                         compatible = "samsung,exynos5250-dw-mshc";
 299                         reg = <0x12510000 0x1000>;
 300                         interrupts = <0 142 0>;
 301                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
 302                         clock-names = "biu", "ciu";
 303                         fifo-depth = <0x80>;
 304                         #address-cells = <1>;
 305                         #size-cells = <0>;
 306                         status = "disabled";
 307                 };
 308
 309                 mshc_1: mshc@12520000 {
 310                         compatible = "samsung,exynos5250-dw-mshc";
 311                         reg = <0x12520000 0x1000>;
 312                         interrupts = <0 143 0>;
 313                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
 314                         clock-names = "biu", "ciu";
 315                         fifo-depth = <0x80>;
 316                         #address-cells = <1>;
 317                         #size-cells = <0>;
 318                         status = "disabled";
 319                 };
 320
 321                 exynos_usbphy: exynos-usbphy@125B0000 {
 322                         compatible = "samsung,exynos3250-usb2-phy";
 323                         reg = <0x125B0000 0x100>;
 324                         samsung,pmureg-phandle = <&pmu_system_controller>;
 325                         clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
 326                         clock-names = "phy", "ref";
 327                         #phy-cells = <1>;
 328                         status = "disabled";
 329                 };
 330
 331                 amba {
 332                         compatible = "arm,amba-bus";
 333                         #address-cells = <1>;
 334                         #size-cells = <1>;
 335                         ranges;
 336
 337                         pdma0: pdma@12680000 {
 338                                 compatible = "arm,pl330", "arm,primecell";
 339                                 reg = <0x12680000 0x1000>;
 340                                 interrupts = <0 138 0>;
 341                                 clocks = <&cmu CLK_PDMA0>;
 342                                 clock-names = "apb_pclk";
 343                                 #dma-cells = <1>;
 344                                 #dma-channels = <8>;
 345                                 #dma-requests = <32>;
 346                         };
 347
 348                         pdma1: pdma@12690000 {
 349                                 compatible = "arm,pl330", "arm,primecell";
 350                                 reg = <0x12690000 0x1000>;
 351                                 interrupts = <0 139 0>;
 352                                 clocks = <&cmu CLK_PDMA1>;
 353                                 clock-names = "apb_pclk";
 354                                 #dma-cells = <1>;
 355                                 #dma-channels = <8>;
 356                                 #dma-requests = <32>;
 357                         };
 358                 };
 359
 360                 adc: adc@126C0000 {
 361                         compatible = "samsung,exynos3250-adc",
 362                                      "samsung,exynos-adc-v2";
 363                         reg = <0x126C0000 0x100>;
 364                         interrupts = <0 137 0>;
 365                         clock-names = "adc", "sclk";
 366                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
 367                         #io-channel-cells = <1>;
 368                         io-channel-ranges;
 369                         samsung,syscon-phandle = <&pmu_system_controller>;
 370                         status = "disabled";
 371                 };
 372
 373                 mfc: codec@13400000 {
 374                         compatible = "samsung,mfc-v7";
 375                         reg = <0x13400000 0x10000>;
 376                         interrupts = <0 102 0>;
 377                         clock-names = "mfc", "sclk_mfc";
 378                         clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
 379                         power-domains = <&pd_mfc>;
 380                         status = "disabled";
 381                 };
 382
 383                 serial_0: serial@13800000 {
 384                         compatible = "samsung,exynos4210-uart";
 385                         reg = <0x13800000 0x100>;
 386                         interrupts = <0 109 0>;
 387                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
 388                         clock-names = "uart", "clk_uart_baud0";
 389                         pinctrl-names = "default";
 390                         pinctrl-0 = <&uart0_data &uart0_fctl>;
 391                         status = "disabled";
 392                 };
 393
 394                 serial_1: serial@13810000 {
 395                         compatible = "samsung,exynos4210-uart";
 396                         reg = <0x13810000 0x100>;
 397                         interrupts = <0 110 0>;
 398                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
 399                         clock-names = "uart", "clk_uart_baud0";
 400                         pinctrl-names = "default";
 401                         pinctrl-0 = <&uart1_data>;
 402                         status = "disabled";
 403                 };
 404
 405                 i2c_0: i2c@13860000 {
 406                         #address-cells = <1>;
 407                         #size-cells = <0>;
 408                         compatible = "samsung,s3c2440-i2c";
 409                         reg = <0x13860000 0x100>;
 410                         interrupts = <0 113 0>;
 411                         clocks = <&cmu CLK_I2C0>;
 412                         clock-names = "i2c";
 413                         pinctrl-names = "default";
 414                         pinctrl-0 = <&i2c0_bus>;
 415                         status = "disabled";
 416                 };
 417
 418                 i2c_1: i2c@13870000 {
 419                         #address-cells = <1>;
 420                         #size-cells = <0>;
 421                         compatible = "samsung,s3c2440-i2c";
 422                         reg = <0x13870000 0x100>;
 423                         interrupts = <0 114 0>;
 424                         clocks = <&cmu CLK_I2C1>;
 425                         clock-names = "i2c";
 426                         pinctrl-names = "default";
 427                         pinctrl-0 = <&i2c1_bus>;
 428                         status = "disabled";
 429                 };
 430
 431                 i2c_2: i2c@13880000 {
 432                         #address-cells = <1>;
 433                         #size-cells = <0>;
 434                         compatible = "samsung,s3c2440-i2c";
 435                         reg = <0x13880000 0x100>;
 436                         interrupts = <0 115 0>;
 437                         clocks = <&cmu CLK_I2C2>;
 438                         clock-names = "i2c";
 439                         pinctrl-names = "default";
 440                         pinctrl-0 = <&i2c2_bus>;
 441                         status = "disabled";
 442                 };
 443
 444                 i2c_3: i2c@13890000 {
 445                         #address-cells = <1>;
 446                         #size-cells = <0>;
 447                         compatible = "samsung,s3c2440-i2c";
 448                         reg = <0x13890000 0x100>;
 449                         interrupts = <0 116 0>;
 450                         clocks = <&cmu CLK_I2C3>;
 451                         clock-names = "i2c";
 452                         pinctrl-names = "default";
 453                         pinctrl-0 = <&i2c3_bus>;
 454                         status = "disabled";
 455                 };
 456
 457                 i2c_4: i2c@138A0000 {
 458                         #address-cells = <1>;
 459                         #size-cells = <0>;
 460                         compatible = "samsung,s3c2440-i2c";
 461                         reg = <0x138A0000 0x100>;
 462                         interrupts = <0 117 0>;
 463                         clocks = <&cmu CLK_I2C4>;
 464                         clock-names = "i2c";
 465                         pinctrl-names = "default";
 466                         pinctrl-0 = <&i2c4_bus>;
 467                         status = "disabled";
 468                 };
 469
 470                 i2c_5: i2c@138B0000 {
 471                         #address-cells = <1>;
 472                         #size-cells = <0>;
 473                         compatible = "samsung,s3c2440-i2c";
 474                         reg = <0x138B0000 0x100>;
 475                         interrupts = <0 118 0>;
 476                         clocks = <&cmu CLK_I2C5>;
 477                         clock-names = "i2c";
 478                         pinctrl-names = "default";
 479                         pinctrl-0 = <&i2c5_bus>;
 480                         status = "disabled";
 481                 };
 482
 483                 i2c_6: i2c@138C0000 {
 484                         #address-cells = <1>;
 485                         #size-cells = <0>;
 486                         compatible = "samsung,s3c2440-i2c";
 487                         reg = <0x138C0000 0x100>;
 488                         interrupts = <0 119 0>;
 489                         clocks = <&cmu CLK_I2C6>;
 490                         clock-names = "i2c";
 491                         pinctrl-names = "default";
 492                         pinctrl-0 = <&i2c6_bus>;
 493                         status = "disabled";
 494                 };
 495
 496                 i2c_7: i2c@138D0000 {
 497                         #address-cells = <1>;
 498                         #size-cells = <0>;
 499                         compatible = "samsung,s3c2440-i2c";
 500                         reg = <0x138D0000 0x100>;
 501                         interrupts = <0 120 0>;
 502                         clocks = <&cmu CLK_I2C7>;
 503                         clock-names = "i2c";
 504                         pinctrl-names = "default";
 505                         pinctrl-0 = <&i2c7_bus>;
 506                         status = "disabled";
 507                 };
 508
 509                 spi_0: spi@13920000 {
 510                         compatible = "samsung,exynos4210-spi";
 511                         reg = <0x13920000 0x100>;
 512                         interrupts = <0 121 0>;
 513                         dmas = <&pdma0 7>, <&pdma0 6>;
 514                         dma-names = "tx", "rx";
 515                         #address-cells = <1>;
 516                         #size-cells = <0>;
 517                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
 518                         clock-names = "spi", "spi_busclk0";
 519                         samsung,spi-src-clk = <0>;
 520                         pinctrl-names = "default";
 521                         pinctrl-0 = <&spi0_bus>;
 522                         status = "disabled";
 523                 };
 524
 525                 spi_1: spi@13930000 {
 526                         compatible = "samsung,exynos4210-spi";
 527                         reg = <0x13930000 0x100>;
 528                         interrupts = <0 122 0>;
 529                         dmas = <&pdma1 7>, <&pdma1 6>;
 530                         dma-names = "tx", "rx";
 531                         #address-cells = <1>;
 532                         #size-cells = <0>;
 533                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
 534                         clock-names = "spi", "spi_busclk0";
 535                         samsung,spi-src-clk = <0>;
 536                         pinctrl-names = "default";
 537                         pinctrl-0 = <&spi1_bus>;
 538                         status = "disabled";
 539                 };
 540
 541                 i2s2: i2s@13970000 {
 542                         compatible = "samsung,s3c6410-i2s";
 543                         reg = <0x13970000 0x100>;
 544                         interrupts = <0 126 0>;
 545                         clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
 546                         clock-names = "iis", "i2s_opclk0";
 547                         dmas = <&pdma0 14>, <&pdma0 13>;
 548                         dma-names = "tx", "rx";
 549                         pinctrl-0 = <&i2s2_bus>;
 550                         pinctrl-names = "default";
 551                         status = "disabled";
 552                 };
 553
 554                 pwm: pwm@139D0000 {
 555                         compatible = "samsung,exynos4210-pwm";
 556                         reg = <0x139D0000 0x1000>;
 557                         interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
 558                                      <0 107 0>, <0 108 0>;
 559                         #pwm-cells = <3>;
 560                         status = "disabled";
 561                 };
 562
 563                 pmu {
 564                         compatible = "arm,cortex-a7-pmu";
 565                         interrupts = <0 18 0>, <0 19 0>;
 566                 };
 567
 568                 ppmu_dmc0: ppmu_dmc0@106a0000 {
 569                         compatible = "samsung,exynos-ppmu";
 570                         reg = <0x106a0000 0x2000>;
 571                         status = "disabled";
 572                 };
 573
 574                 ppmu_dmc1: ppmu_dmc1@106b0000 {
 575                         compatible = "samsung,exynos-ppmu";
 576                         reg = <0x106b0000 0x2000>;
 577                         status = "disabled";
 578                 };
 579
 580                 ppmu_cpu: ppmu_cpu@106c0000 {
 581                         compatible = "samsung,exynos-ppmu";
 582                         reg = <0x106c0000 0x2000>;
 583                         status = "disabled";
 584                 };
 585
 586                 ppmu_rightbus: ppmu_rightbus@112a0000 {
 587                         compatible = "samsung,exynos-ppmu";
 588                         reg = <0x112a0000 0x2000>;
 589                         clocks = <&cmu CLK_PPMURIGHT>;
 590                         clock-names = "ppmu";
 591                         status = "disabled";
 592                 };
 593
 594                 ppmu_leftbus: ppmu_leftbus0@116a0000 {
 595                         compatible = "samsung,exynos-ppmu";
 596                         reg = <0x116a0000 0x2000>;
 597                         clocks = <&cmu CLK_PPMULEFT>;
 598                         clock-names = "ppmu";
 599                         status = "disabled";
 600                 };
 601
 602                 ppmu_camif: ppmu_camif@11ac0000 {
 603                         compatible = "samsung,exynos-ppmu";
 604                         reg = <0x11ac0000 0x2000>;
 605                         clocks = <&cmu CLK_PPMUCAMIF>;
 606                         clock-names = "ppmu";
 607                         status = "disabled";
 608                 };
 609
 610                 ppmu_lcd0: ppmu_lcd0@11e40000 {
 611                         compatible = "samsung,exynos-ppmu";
 612                         reg = <0x11e40000 0x2000>;
 613                         clocks = <&cmu CLK_PPMULCD0>;
 614                         clock-names = "ppmu";
 615                         status = "disabled";
 616                 };
 617
 618                 ppmu_fsys: ppmu_fsys@12630000 {
 619                         compatible = "samsung,exynos-ppmu";
 620                         reg = <0x12630000 0x2000>;
 621                         clocks = <&cmu CLK_PPMUFILE>;
 622                         clock-names = "ppmu";
 623                         status = "disabled";
 624                 };
 625
 626                 ppmu_g3d: ppmu_g3d@13220000 {
 627                         compatible = "samsung,exynos-ppmu";
 628                         reg = <0x13220000 0x2000>;
 629                         clocks = <&cmu CLK_PPMUG3D>;
 630                         clock-names = "ppmu";
 631                         status = "disabled";
 632                 };
 633
 634                 ppmu_mfc: ppmu_mfc@13660000 {
 635                         compatible = "samsung,exynos-ppmu";
 636                         reg = <0x13660000 0x2000>;
 637                         clocks = <&cmu CLK_PPMUMFC_L>;
 638                         clock-names = "ppmu";
 639                         status = "disabled";
 640                 };
 641         };
 642 };
 643
 644 #include "exynos3250-pinctrl.dtsi"