2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
13 #include "skeleton.dtsi"
15 #define MAX_SOURCES 400
16 #define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
22 compatible = "ti,dra7xx";
23 interrupt-parent = <&gic>;
40 compatible = "arm,armv7-timer";
41 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
42 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
43 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
44 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
47 gic: interrupt-controller@48211000 {
48 compatible = "arm,cortex-a15-gic";
50 #interrupt-cells = <3>;
51 arm,routable-irqs = <192>;
52 reg = <0x48211000 0x1000>,
56 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
60 * The soc node represents the soc top level view. It is used for IPs
61 * that are not memory mapped in the MPU view or for the MPU itself.
64 compatible = "ti,omap-infra";
66 compatible = "ti,omap5-mpu";
72 * XXX: Use a flat representation of the SOC interconnect.
73 * The real OMAP interconnect network is quite complex.
74 * Since it will not bring real advantage to represent that in DT for
75 * the moment, just use a fake OCP bus entry to represent the whole bus
79 compatible = "ti,dra7-l3-noc", "simple-bus";
83 ti,hwmods = "l3_main_1", "l3_main_2";
84 reg = <0x44000000 0x1000000>,
86 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
90 compatible = "ti,dra7-prm";
91 reg = <0x4ae06000 0x3000>;
92 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
99 prm_clockdomains: clockdomains {
104 compatible = "simple-bus";
106 #address-cells = <1>;
107 ranges = <0x51000000 0x51000000 0x3000
108 0x0 0x20000000 0x10000000>;
110 compatible = "ti,dra7-pcie";
111 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
112 reg-names = "rc_dbics", "ti_conf", "config";
113 interrupts = <0 232 0x4>, <0 233 0x4>;
114 #address-cells = <3>;
117 ranges = <0x81000000 0 0 0x03000 0 0x00010000
118 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
119 #interrupt-cells = <1>;
123 phy-names = "pcie-phy0";
124 interrupt-map-mask = <0 0 0 7>;
125 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
126 <0 0 0 2 &pcie1_intc 2>,
127 <0 0 0 3 &pcie1_intc 3>,
128 <0 0 0 4 &pcie1_intc 4>;
129 pcie1_intc: interrupt-controller {
130 interrupt-controller;
131 #address-cells = <0>;
132 #interrupt-cells = <1>;
138 compatible = "simple-bus";
140 #address-cells = <1>;
141 ranges = <0x51800000 0x51800000 0x3000
142 0x0 0x30000000 0x10000000>;
145 compatible = "ti,dra7-pcie";
146 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
147 reg-names = "rc_dbics", "ti_conf", "config";
148 interrupts = <0 355 0x4>, <0 356 0x4>;
149 #address-cells = <3>;
152 ranges = <0x81000000 0 0 0x03000 0 0x00010000
153 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
154 #interrupt-cells = <1>;
158 phy-names = "pcie-phy0";
159 interrupt-map-mask = <0 0 0 7>;
160 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
161 <0 0 0 2 &pcie2_intc 2>,
162 <0 0 0 3 &pcie2_intc 3>,
163 <0 0 0 4 &pcie2_intc 4>;
164 pcie2_intc: interrupt-controller {
165 interrupt-controller;
166 #address-cells = <0>;
167 #interrupt-cells = <1>;
172 cm_core_aon: cm_core_aon@4a005000 {
173 compatible = "ti,dra7-cm-core-aon";
174 reg = <0x4a005000 0x2000>;
176 cm_core_aon_clocks: clocks {
177 #address-cells = <1>;
181 cm_core_aon_clockdomains: clockdomains {
185 cm_core: cm_core@4a008000 {
186 compatible = "ti,dra7-cm-core";
187 reg = <0x4a008000 0x3000>;
189 cm_core_clocks: clocks {
190 #address-cells = <1>;
194 cm_core_clockdomains: clockdomains {
198 counter32k: counter@4ae04000 {
199 compatible = "ti,omap-counter32k";
200 reg = <0x4ae04000 0x40>;
201 ti,hwmods = "counter_32k";
204 dra7_ctrl_general: tisyscon@4a002e00 {
205 compatible = "syscon";
206 reg = <0x4a002e00 0x7c>;
209 pbias_regulator: pbias_regulator {
210 compatible = "ti,pbias-omap";
212 syscon = <&dra7_ctrl_general>;
213 pbias_mmc_reg: pbias_mmc_omap5 {
214 regulator-name = "pbias_mmc_omap5";
215 regulator-min-microvolt = <1800000>;
216 regulator-max-microvolt = <3000000>;
220 dra7_pmx_core: pinmux@4a003400 {
221 compatible = "ti,dra7-padconf", "pinctrl-single";
222 reg = <0x4a003400 0x0464>;
223 #address-cells = <1>;
225 #interrupt-cells = <1>;
226 interrupt-controller;
227 pinctrl-single,register-width = <32>;
228 pinctrl-single,function-mask = <0x3fffffff>;
231 sdma: dma-controller@4a056000 {
232 compatible = "ti,omap4430-sdma";
233 reg = <0x4a056000 0x1000>;
234 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
239 #dma-channels = <32>;
240 #dma-requests = <127>;
243 gpio1: gpio@4ae10000 {
244 compatible = "ti,omap4-gpio";
245 reg = <0x4ae10000 0x200>;
246 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
254 gpio2: gpio@48055000 {
255 compatible = "ti,omap4-gpio";
256 reg = <0x48055000 0x200>;
257 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
265 gpio3: gpio@48057000 {
266 compatible = "ti,omap4-gpio";
267 reg = <0x48057000 0x200>;
268 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
272 interrupt-controller;
273 #interrupt-cells = <2>;
276 gpio4: gpio@48059000 {
277 compatible = "ti,omap4-gpio";
278 reg = <0x48059000 0x200>;
279 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
283 interrupt-controller;
284 #interrupt-cells = <2>;
287 gpio5: gpio@4805b000 {
288 compatible = "ti,omap4-gpio";
289 reg = <0x4805b000 0x200>;
290 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
294 interrupt-controller;
295 #interrupt-cells = <2>;
298 gpio6: gpio@4805d000 {
299 compatible = "ti,omap4-gpio";
300 reg = <0x4805d000 0x200>;
301 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
309 gpio7: gpio@48051000 {
310 compatible = "ti,omap4-gpio";
311 reg = <0x48051000 0x200>;
312 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
316 interrupt-controller;
317 #interrupt-cells = <2>;
320 gpio8: gpio@48053000 {
321 compatible = "ti,omap4-gpio";
322 reg = <0x48053000 0x200>;
323 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
327 interrupt-controller;
328 #interrupt-cells = <2>;
331 uart1: serial@4806a000 {
332 compatible = "ti,omap4-uart";
333 reg = <0x4806a000 0x100>;
334 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
336 clock-frequency = <48000000>;
340 uart2: serial@4806c000 {
341 compatible = "ti,omap4-uart";
342 reg = <0x4806c000 0x100>;
343 interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
345 clock-frequency = <48000000>;
349 uart3: serial@48020000 {
350 compatible = "ti,omap4-uart";
351 reg = <0x48020000 0x100>;
352 interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
354 clock-frequency = <48000000>;
358 uart4: serial@4806e000 {
359 compatible = "ti,omap4-uart";
360 reg = <0x4806e000 0x100>;
361 interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
363 clock-frequency = <48000000>;
367 uart5: serial@48066000 {
368 compatible = "ti,omap4-uart";
369 reg = <0x48066000 0x100>;
370 interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
372 clock-frequency = <48000000>;
376 uart6: serial@48068000 {
377 compatible = "ti,omap4-uart";
378 reg = <0x48068000 0x100>;
379 interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
381 clock-frequency = <48000000>;
385 uart7: serial@48420000 {
386 compatible = "ti,omap4-uart";
387 reg = <0x48420000 0x100>;
388 interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
390 clock-frequency = <48000000>;
394 uart8: serial@48422000 {
395 compatible = "ti,omap4-uart";
396 reg = <0x48422000 0x100>;
397 interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
399 clock-frequency = <48000000>;
403 uart9: serial@48424000 {
404 compatible = "ti,omap4-uart";
405 reg = <0x48424000 0x100>;
406 interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
408 clock-frequency = <48000000>;
412 uart10: serial@4ae2b000 {
413 compatible = "ti,omap4-uart";
414 reg = <0x4ae2b000 0x100>;
415 interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
416 ti,hwmods = "uart10";
417 clock-frequency = <48000000>;
421 mailbox1: mailbox@4a0f4000 {
422 compatible = "ti,omap4-mailbox";
423 reg = <0x4a0f4000 0x200>;
424 ti,hwmods = "mailbox1";
425 ti,mbox-num-users = <3>;
426 ti,mbox-num-fifos = <8>;
430 mailbox2: mailbox@4883a000 {
431 compatible = "ti,omap4-mailbox";
432 reg = <0x4883a000 0x200>;
433 ti,hwmods = "mailbox2";
434 ti,mbox-num-users = <4>;
435 ti,mbox-num-fifos = <12>;
439 mailbox3: mailbox@4883c000 {
440 compatible = "ti,omap4-mailbox";
441 reg = <0x4883c000 0x200>;
442 ti,hwmods = "mailbox3";
443 ti,mbox-num-users = <4>;
444 ti,mbox-num-fifos = <12>;
448 mailbox4: mailbox@4883e000 {
449 compatible = "ti,omap4-mailbox";
450 reg = <0x4883e000 0x200>;
451 ti,hwmods = "mailbox4";
452 ti,mbox-num-users = <4>;
453 ti,mbox-num-fifos = <12>;
457 mailbox5: mailbox@48840000 {
458 compatible = "ti,omap4-mailbox";
459 reg = <0x48840000 0x200>;
460 ti,hwmods = "mailbox5";
461 ti,mbox-num-users = <4>;
462 ti,mbox-num-fifos = <12>;
466 mailbox6: mailbox@48842000 {
467 compatible = "ti,omap4-mailbox";
468 reg = <0x48842000 0x200>;
469 ti,hwmods = "mailbox6";
470 ti,mbox-num-users = <4>;
471 ti,mbox-num-fifos = <12>;
475 mailbox7: mailbox@48844000 {
476 compatible = "ti,omap4-mailbox";
477 reg = <0x48844000 0x200>;
478 ti,hwmods = "mailbox7";
479 ti,mbox-num-users = <4>;
480 ti,mbox-num-fifos = <12>;
484 mailbox8: mailbox@48846000 {
485 compatible = "ti,omap4-mailbox";
486 reg = <0x48846000 0x200>;
487 ti,hwmods = "mailbox8";
488 ti,mbox-num-users = <4>;
489 ti,mbox-num-fifos = <12>;
493 mailbox9: mailbox@4885e000 {
494 compatible = "ti,omap4-mailbox";
495 reg = <0x4885e000 0x200>;
496 ti,hwmods = "mailbox9";
497 ti,mbox-num-users = <4>;
498 ti,mbox-num-fifos = <12>;
502 mailbox10: mailbox@48860000 {
503 compatible = "ti,omap4-mailbox";
504 reg = <0x48860000 0x200>;
505 ti,hwmods = "mailbox10";
506 ti,mbox-num-users = <4>;
507 ti,mbox-num-fifos = <12>;
511 mailbox11: mailbox@48862000 {
512 compatible = "ti,omap4-mailbox";
513 reg = <0x48862000 0x200>;
514 ti,hwmods = "mailbox11";
515 ti,mbox-num-users = <4>;
516 ti,mbox-num-fifos = <12>;
520 mailbox12: mailbox@48864000 {
521 compatible = "ti,omap4-mailbox";
522 reg = <0x48864000 0x200>;
523 ti,hwmods = "mailbox12";
524 ti,mbox-num-users = <4>;
525 ti,mbox-num-fifos = <12>;
529 mailbox13: mailbox@48802000 {
530 compatible = "ti,omap4-mailbox";
531 reg = <0x48802000 0x200>;
532 ti,hwmods = "mailbox13";
533 ti,mbox-num-users = <4>;
534 ti,mbox-num-fifos = <12>;
538 timer1: timer@4ae18000 {
539 compatible = "ti,omap5430-timer";
540 reg = <0x4ae18000 0x80>;
541 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
542 ti,hwmods = "timer1";
546 timer2: timer@48032000 {
547 compatible = "ti,omap5430-timer";
548 reg = <0x48032000 0x80>;
549 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
550 ti,hwmods = "timer2";
553 timer3: timer@48034000 {
554 compatible = "ti,omap5430-timer";
555 reg = <0x48034000 0x80>;
556 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
557 ti,hwmods = "timer3";
560 timer4: timer@48036000 {
561 compatible = "ti,omap5430-timer";
562 reg = <0x48036000 0x80>;
563 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
564 ti,hwmods = "timer4";
567 timer5: timer@48820000 {
568 compatible = "ti,omap5430-timer";
569 reg = <0x48820000 0x80>;
570 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
571 ti,hwmods = "timer5";
575 timer6: timer@48822000 {
576 compatible = "ti,omap5430-timer";
577 reg = <0x48822000 0x80>;
578 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
579 ti,hwmods = "timer6";
584 timer7: timer@48824000 {
585 compatible = "ti,omap5430-timer";
586 reg = <0x48824000 0x80>;
587 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
588 ti,hwmods = "timer7";
592 timer8: timer@48826000 {
593 compatible = "ti,omap5430-timer";
594 reg = <0x48826000 0x80>;
595 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
596 ti,hwmods = "timer8";
601 timer9: timer@4803e000 {
602 compatible = "ti,omap5430-timer";
603 reg = <0x4803e000 0x80>;
604 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
605 ti,hwmods = "timer9";
608 timer10: timer@48086000 {
609 compatible = "ti,omap5430-timer";
610 reg = <0x48086000 0x80>;
611 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
612 ti,hwmods = "timer10";
615 timer11: timer@48088000 {
616 compatible = "ti,omap5430-timer";
617 reg = <0x48088000 0x80>;
618 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
619 ti,hwmods = "timer11";
623 timer13: timer@48828000 {
624 compatible = "ti,omap5430-timer";
625 reg = <0x48828000 0x80>;
626 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
627 ti,hwmods = "timer13";
631 timer14: timer@4882a000 {
632 compatible = "ti,omap5430-timer";
633 reg = <0x4882a000 0x80>;
634 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
635 ti,hwmods = "timer14";
639 timer15: timer@4882c000 {
640 compatible = "ti,omap5430-timer";
641 reg = <0x4882c000 0x80>;
642 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
643 ti,hwmods = "timer15";
647 timer16: timer@4882e000 {
648 compatible = "ti,omap5430-timer";
649 reg = <0x4882e000 0x80>;
650 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
651 ti,hwmods = "timer16";
656 compatible = "ti,omap4-wdt";
657 reg = <0x4ae14000 0x80>;
658 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
659 ti,hwmods = "wd_timer2";
662 hwspinlock: spinlock@4a0f6000 {
663 compatible = "ti,omap4-hwspinlock";
664 reg = <0x4a0f6000 0x1000>;
665 ti,hwmods = "spinlock";
670 compatible = "ti,omap5-dmm";
671 reg = <0x4e000000 0x800>;
672 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
677 compatible = "ti,omap4-i2c";
678 reg = <0x48070000 0x100>;
679 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
680 #address-cells = <1>;
687 compatible = "ti,omap4-i2c";
688 reg = <0x48072000 0x100>;
689 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
690 #address-cells = <1>;
697 compatible = "ti,omap4-i2c";
698 reg = <0x48060000 0x100>;
699 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
700 #address-cells = <1>;
707 compatible = "ti,omap4-i2c";
708 reg = <0x4807a000 0x100>;
709 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
710 #address-cells = <1>;
717 compatible = "ti,omap4-i2c";
718 reg = <0x4807c000 0x100>;
719 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
720 #address-cells = <1>;
727 compatible = "ti,omap4-hsmmc";
728 reg = <0x4809c000 0x400>;
729 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
732 ti,needs-special-reset;
733 dmas = <&sdma 61>, <&sdma 62>;
734 dma-names = "tx", "rx";
736 pbias-supply = <&pbias_mmc_reg>;
740 compatible = "ti,omap4-hsmmc";
741 reg = <0x480b4000 0x400>;
742 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
744 ti,needs-special-reset;
745 dmas = <&sdma 47>, <&sdma 48>;
746 dma-names = "tx", "rx";
751 compatible = "ti,omap4-hsmmc";
752 reg = <0x480ad000 0x400>;
753 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
755 ti,needs-special-reset;
756 dmas = <&sdma 77>, <&sdma 78>;
757 dma-names = "tx", "rx";
762 compatible = "ti,omap4-hsmmc";
763 reg = <0x480d1000 0x400>;
764 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
766 ti,needs-special-reset;
767 dmas = <&sdma 57>, <&sdma 58>;
768 dma-names = "tx", "rx";
772 abb_mpu: regulator-abb-mpu {
773 compatible = "ti,abb-v3";
774 regulator-name = "abb_mpu";
775 #address-cells = <0>;
777 clocks = <&sys_clkin1>;
778 ti,settling-time = <50>;
779 ti,clock-cycles = <16>;
781 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
782 <0x4ae06014 0x4>, <0x4a003b20 0x8>,
784 reg-names = "setup-address", "control-address",
785 "int-address", "efuse-address",
787 ti,tranxdone-status-mask = <0x80>;
788 /* LDOVBBMPU_FBB_MUX_CTRL */
789 ti,ldovbb-override-mask = <0x400>;
790 /* LDOVBBMPU_FBB_VSET_OUT */
791 ti,ldovbb-vset-mask = <0x1F>;
794 * NOTE: only FBB mode used but actual vset will
795 * determine final biasing
798 /*uV ABB efuse rbb_m fbb_m vset_m*/
799 1060000 0 0x0 0 0x02000000 0x01F00000
800 1160000 0 0x4 0 0x02000000 0x01F00000
801 1210000 0 0x8 0 0x02000000 0x01F00000
805 abb_ivahd: regulator-abb-ivahd {
806 compatible = "ti,abb-v3";
807 regulator-name = "abb_ivahd";
808 #address-cells = <0>;
810 clocks = <&sys_clkin1>;
811 ti,settling-time = <50>;
812 ti,clock-cycles = <16>;
814 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
815 <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
817 reg-names = "setup-address", "control-address",
818 "int-address", "efuse-address",
820 ti,tranxdone-status-mask = <0x40000000>;
821 /* LDOVBBIVA_FBB_MUX_CTRL */
822 ti,ldovbb-override-mask = <0x400>;
823 /* LDOVBBIVA_FBB_VSET_OUT */
824 ti,ldovbb-vset-mask = <0x1F>;
827 * NOTE: only FBB mode used but actual vset will
828 * determine final biasing
831 /*uV ABB efuse rbb_m fbb_m vset_m*/
832 1055000 0 0x0 0 0x02000000 0x01F00000
833 1150000 0 0x4 0 0x02000000 0x01F00000
834 1250000 0 0x8 0 0x02000000 0x01F00000
838 abb_dspeve: regulator-abb-dspeve {
839 compatible = "ti,abb-v3";
840 regulator-name = "abb_dspeve";
841 #address-cells = <0>;
843 clocks = <&sys_clkin1>;
844 ti,settling-time = <50>;
845 ti,clock-cycles = <16>;
847 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
848 <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
850 reg-names = "setup-address", "control-address",
851 "int-address", "efuse-address",
853 ti,tranxdone-status-mask = <0x20000000>;
854 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
855 ti,ldovbb-override-mask = <0x400>;
856 /* LDOVBBDSPEVE_FBB_VSET_OUT */
857 ti,ldovbb-vset-mask = <0x1F>;
860 * NOTE: only FBB mode used but actual vset will
861 * determine final biasing
864 /*uV ABB efuse rbb_m fbb_m vset_m*/
865 1055000 0 0x0 0 0x02000000 0x01F00000
866 1150000 0 0x4 0 0x02000000 0x01F00000
867 1250000 0 0x8 0 0x02000000 0x01F00000
871 abb_gpu: regulator-abb-gpu {
872 compatible = "ti,abb-v3";
873 regulator-name = "abb_gpu";
874 #address-cells = <0>;
876 clocks = <&sys_clkin1>;
877 ti,settling-time = <50>;
878 ti,clock-cycles = <16>;
880 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
881 <0x4ae06010 0x4>, <0x4a003b08 0x8>,
883 reg-names = "setup-address", "control-address",
884 "int-address", "efuse-address",
886 ti,tranxdone-status-mask = <0x10000000>;
887 /* LDOVBBGPU_FBB_MUX_CTRL */
888 ti,ldovbb-override-mask = <0x400>;
889 /* LDOVBBGPU_FBB_VSET_OUT */
890 ti,ldovbb-vset-mask = <0x1F>;
893 * NOTE: only FBB mode used but actual vset will
894 * determine final biasing
897 /*uV ABB efuse rbb_m fbb_m vset_m*/
898 1090000 0 0x0 0 0x02000000 0x01F00000
899 1210000 0 0x4 0 0x02000000 0x01F00000
900 1280000 0 0x8 0 0x02000000 0x01F00000
904 mcspi1: spi@48098000 {
905 compatible = "ti,omap4-mcspi";
906 reg = <0x48098000 0x200>;
907 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
908 #address-cells = <1>;
910 ti,hwmods = "mcspi1";
920 dma-names = "tx0", "rx0", "tx1", "rx1",
921 "tx2", "rx2", "tx3", "rx3";
925 mcspi2: spi@4809a000 {
926 compatible = "ti,omap4-mcspi";
927 reg = <0x4809a000 0x200>;
928 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
929 #address-cells = <1>;
931 ti,hwmods = "mcspi2";
937 dma-names = "tx0", "rx0", "tx1", "rx1";
941 mcspi3: spi@480b8000 {
942 compatible = "ti,omap4-mcspi";
943 reg = <0x480b8000 0x200>;
944 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
945 #address-cells = <1>;
947 ti,hwmods = "mcspi3";
949 dmas = <&sdma 15>, <&sdma 16>;
950 dma-names = "tx0", "rx0";
954 mcspi4: spi@480ba000 {
955 compatible = "ti,omap4-mcspi";
956 reg = <0x480ba000 0x200>;
957 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
958 #address-cells = <1>;
960 ti,hwmods = "mcspi4";
962 dmas = <&sdma 70>, <&sdma 71>;
963 dma-names = "tx0", "rx0";
967 qspi: qspi@4b300000 {
968 compatible = "ti,dra7xxx-qspi";
969 reg = <0x4b300000 0x100>;
970 reg-names = "qspi_base";
971 #address-cells = <1>;
974 clocks = <&qspi_gfclk_div>;
977 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
981 omap_control_sata: control-phy@4a002374 {
982 compatible = "ti,control-phy-pipe3";
983 reg = <0x4a002374 0x4>;
985 clocks = <&sys_clkin1>;
986 clock-names = "sysclk";
991 compatible = "ti,omap-ocp2scp";
992 #address-cells = <1>;
995 reg = <0x4a090000 0x20>;
996 ti,hwmods = "ocp2scp3";
997 sata_phy: phy@4A096000 {
998 compatible = "ti,phy-pipe3-sata";
999 reg = <0x4A096000 0x80>, /* phy_rx */
1000 <0x4A096400 0x64>, /* phy_tx */
1001 <0x4A096800 0x40>; /* pll_ctrl */
1002 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1003 ctrl-module = <&omap_control_sata>;
1004 clocks = <&sys_clkin1>;
1005 clock-names = "sysclk";
1009 pcie1_phy: pciephy@4a094000 {
1010 compatible = "ti,phy-pipe3-pcie";
1011 reg = <0x4a094000 0x80>, /* phy_rx */
1012 <0x4a094400 0x64>; /* phy_tx */
1013 reg-names = "phy_rx", "phy_tx";
1014 ctrl-module = <&omap_control_pcie1phy>;
1015 clocks = <&dpll_pcie_ref_ck>,
1016 <&dpll_pcie_ref_m2ldo_ck>,
1017 <&optfclk_pciephy1_32khz>,
1018 <&optfclk_pciephy1_clk>,
1019 <&optfclk_pciephy1_div_clk>,
1020 <&optfclk_pciephy_div>;
1021 clock-names = "dpll_ref", "dpll_ref_m2",
1022 "wkupclk", "refclk",
1023 "div-clk", "phy-div";
1026 ti,hwmods = "pcie1-phy";
1029 pcie2_phy: pciephy@4a095000 {
1030 compatible = "ti,phy-pipe3-pcie";
1031 reg = <0x4a095000 0x80>, /* phy_rx */
1032 <0x4a095400 0x64>; /* phy_tx */
1033 reg-names = "phy_rx", "phy_tx";
1034 ctrl-module = <&omap_control_pcie2phy>;
1035 clocks = <&dpll_pcie_ref_ck>,
1036 <&dpll_pcie_ref_m2ldo_ck>,
1037 <&optfclk_pciephy2_32khz>,
1038 <&optfclk_pciephy2_clk>,
1039 <&optfclk_pciephy2_div_clk>,
1040 <&optfclk_pciephy_div>;
1041 clock-names = "dpll_ref", "dpll_ref_m2",
1042 "wkupclk", "refclk",
1043 "div-clk", "phy-div";
1045 ti,hwmods = "pcie2-phy";
1047 status = "disabled";
1051 sata: sata@4a141100 {
1052 compatible = "snps,dwc-ahci";
1053 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1054 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1056 phy-names = "sata-phy";
1057 clocks = <&sata_ref_clk>;
1061 omap_control_pcie1phy: control-phy@0x4a003c40 {
1062 compatible = "ti,control-phy-pcie";
1063 reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1064 reg-names = "power", "control_sma", "pcie_pcs";
1065 clocks = <&sys_clkin1>;
1066 clock-names = "sysclk";
1069 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1070 compatible = "ti,control-phy-pcie";
1071 reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1072 reg-names = "power", "control_sma", "pcie_pcs";
1073 clocks = <&sys_clkin1>;
1074 clock-names = "sysclk";
1075 status = "disabled";
1078 omap_control_usb2phy1: control-phy@4a002300 {
1079 compatible = "ti,control-phy-usb2";
1080 reg = <0x4a002300 0x4>;
1081 reg-names = "power";
1084 omap_control_usb3phy1: control-phy@4a002370 {
1085 compatible = "ti,control-phy-pipe3";
1086 reg = <0x4a002370 0x4>;
1087 reg-names = "power";
1090 omap_control_usb2phy2: control-phy@0x4a002e74 {
1091 compatible = "ti,control-phy-usb2-dra7";
1092 reg = <0x4a002e74 0x4>;
1093 reg-names = "power";
1098 compatible = "ti,omap-ocp2scp";
1099 #address-cells = <1>;
1102 reg = <0x4a080000 0x20>;
1103 ti,hwmods = "ocp2scp1";
1105 usb2_phy1: phy@4a084000 {
1106 compatible = "ti,omap-usb2";
1107 reg = <0x4a084000 0x400>;
1108 ctrl-module = <&omap_control_usb2phy1>;
1109 clocks = <&usb_phy1_always_on_clk32k>,
1110 <&usb_otg_ss1_refclk960m>;
1111 clock-names = "wkupclk",
1116 usb2_phy2: phy@4a085000 {
1117 compatible = "ti,omap-usb2";
1118 reg = <0x4a085000 0x400>;
1119 ctrl-module = <&omap_control_usb2phy2>;
1120 clocks = <&usb_phy2_always_on_clk32k>,
1121 <&usb_otg_ss2_refclk960m>;
1122 clock-names = "wkupclk",
1127 usb3_phy1: phy@4a084400 {
1128 compatible = "ti,omap-usb3";
1129 reg = <0x4a084400 0x80>,
1132 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1133 ctrl-module = <&omap_control_usb3phy1>;
1134 clocks = <&usb_phy3_always_on_clk32k>,
1136 <&usb_otg_ss1_refclk960m>;
1137 clock-names = "wkupclk",
1144 omap_dwc3_1@48880000 {
1145 compatible = "ti,dwc3";
1146 ti,hwmods = "usb_otg_ss1";
1147 reg = <0x48880000 0x10000>;
1148 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1149 #address-cells = <1>;
1153 usb1: usb@48890000 {
1154 compatible = "snps,dwc3";
1155 reg = <0x48890000 0x17000>;
1156 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1157 phys = <&usb2_phy1>, <&usb3_phy1>;
1158 phy-names = "usb2-phy", "usb3-phy";
1160 maximum-speed = "super-speed";
1165 omap_dwc3_2@488c0000 {
1166 compatible = "ti,dwc3";
1167 ti,hwmods = "usb_otg_ss2";
1168 reg = <0x488c0000 0x10000>;
1169 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1170 #address-cells = <1>;
1174 usb2: usb@488d0000 {
1175 compatible = "snps,dwc3";
1176 reg = <0x488d0000 0x17000>;
1177 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1178 phys = <&usb2_phy2>;
1179 phy-names = "usb2-phy";
1181 maximum-speed = "high-speed";
1186 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1187 omap_dwc3_3@48900000 {
1188 compatible = "ti,dwc3";
1189 ti,hwmods = "usb_otg_ss3";
1190 reg = <0x48900000 0x10000>;
1191 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1192 #address-cells = <1>;
1196 status = "disabled";
1197 usb3: usb@48910000 {
1198 compatible = "snps,dwc3";
1199 reg = <0x48910000 0x17000>;
1200 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1202 maximum-speed = "high-speed";
1207 omap_dwc3_4@48940000 {
1208 compatible = "ti,dwc3";
1209 ti,hwmods = "usb_otg_ss4";
1210 reg = <0x48940000 0x10000>;
1211 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
1212 #address-cells = <1>;
1216 status = "disabled";
1217 usb4: usb@48950000 {
1218 compatible = "snps,dwc3";
1219 reg = <0x48950000 0x17000>;
1220 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1222 maximum-speed = "high-speed";
1228 compatible = "ti,am3352-elm";
1229 reg = <0x48078000 0xfc0>; /* device IO registers */
1230 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1232 status = "disabled";
1235 gpmc: gpmc@50000000 {
1236 compatible = "ti,am3352-gpmc";
1238 reg = <0x50000000 0x37c>; /* device IO registers */
1239 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1241 gpmc,num-waitpins = <2>;
1242 #address-cells = <2>;
1244 status = "disabled";
1248 compatible = "ti,dra7-atl";
1249 reg = <0x4843c000 0x3ff>;
1251 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1252 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1253 clocks = <&atl_gfclk_mux>;
1254 clock-names = "fck";
1255 status = "disabled";
1258 crossbar_mpu: crossbar@4a020000 {
1259 compatible = "ti,irq-crossbar";
1260 reg = <0x4a002a48 0x130>;
1261 ti,max-irqs = <160>;
1262 ti,max-crossbar-sources = <MAX_SOURCES>;
1264 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1265 ti,irqs-skip = <10 133 139 140>;
1266 ti,irqs-safe-map = <0>;
1271 /include/ "dra7xx-clocks.dtsi"