2 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include <dt-bindings/clock/berlin2q.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "skeleton.dtsi"
15 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
16 compatible = "marvell,berlin2q", "marvell,berlin";
21 enable-method = "marvell,berlin-smp";
24 compatible = "arm,cortex-a9";
26 next-level-cache = <&l2>;
31 compatible = "arm,cortex-a9";
33 next-level-cache = <&l2>;
38 compatible = "arm,cortex-a9";
40 next-level-cache = <&l2>;
45 compatible = "arm,cortex-a9";
47 next-level-cache = <&l2>;
53 compatible = "fixed-clock";
55 clock-frequency = <25000000>;
59 compatible = "simple-bus";
63 ranges = <0 0xf7000000 0x1000000>;
64 interrupt-parent = <&gic>;
66 sdhci0: sdhci@ab0000 {
67 compatible = "mrvl,pxav3-mmc";
68 reg = <0xab0000 0x200>;
69 clocks = <&chip CLKID_SDIO1XIN>;
70 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
74 sdhci1: sdhci@ab0800 {
75 compatible = "mrvl,pxav3-mmc";
76 reg = <0xab0800 0x200>;
77 clocks = <&chip CLKID_SDIO1XIN>;
78 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
82 sdhci2: sdhci@ab1000 {
83 compatible = "mrvl,pxav3-mmc";
84 reg = <0xab1000 0x200>;
85 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
86 clocks = <&chip CLKID_SDIO1XIN>;
90 l2: l2-cache-controller@ac0000 {
91 compatible = "arm,pl310-cache";
92 reg = <0xac0000 0x1000>;
94 arm,data-latency = <2 2 2>;
95 arm,tag-latency = <2 2 2>;
98 scu: snoop-control-unit@ad0000 {
99 compatible = "arm,cortex-a9-scu";
100 reg = <0xad0000 0x58>;
104 compatible = "arm,cortex-a9-twd-timer";
105 reg = <0xad0600 0x20>;
106 clocks = <&chip CLKID_TWD>;
107 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
110 gic: interrupt-controller@ad1000 {
111 compatible = "arm,cortex-a9-gic";
112 reg = <0xad1000 0x1000>, <0xad0100 0x100>;
113 interrupt-controller;
114 #interrupt-cells = <3>;
117 eth0: ethernet@b90000 {
118 compatible = "marvell,pxa168-eth";
119 reg = <0xb90000 0x10000>;
120 clocks = <&chip CLKID_GETH0>;
121 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
122 /* set by bootloader */
123 local-mac-address = [00 00 00 00 00 00];
124 #address-cells = <1>;
126 phy-handle = <ðphy0>;
129 ethphy0: ethernet-phy@0 {
135 compatible = "marvell,berlin-cpu-ctrl";
136 reg = <0xdd0000 0x10000>;
140 compatible = "simple-bus";
141 #address-cells = <1>;
144 ranges = <0 0xe80000 0x10000>;
145 interrupt-parent = <&aic>;
148 compatible = "snps,dw-apb-gpio";
149 reg = <0x0400 0x400>;
150 #address-cells = <1>;
154 compatible = "snps,dw-apb-gpio-port";
157 snps,nr-gpios = <32>;
159 interrupt-controller;
160 #interrupt-cells = <2>;
166 compatible = "snps,dw-apb-gpio";
167 reg = <0x0800 0x400>;
168 #address-cells = <1>;
172 compatible = "snps,dw-apb-gpio-port";
175 snps,nr-gpios = <32>;
177 interrupt-controller;
178 #interrupt-cells = <2>;
184 compatible = "snps,dw-apb-gpio";
185 reg = <0x0c00 0x400>;
186 #address-cells = <1>;
190 compatible = "snps,dw-apb-gpio-port";
193 snps,nr-gpios = <32>;
195 interrupt-controller;
196 #interrupt-cells = <2>;
202 compatible = "snps,dw-apb-gpio";
203 reg = <0x1000 0x400>;
204 #address-cells = <1>;
208 compatible = "snps,dw-apb-gpio-port";
211 snps,nr-gpios = <32>;
213 interrupt-controller;
214 #interrupt-cells = <2>;
220 compatible = "snps,designware-i2c";
221 #address-cells = <1>;
223 reg = <0x1400 0x100>;
224 interrupt-parent = <&aic>;
226 clocks = <&chip CLKID_CFG>;
227 pinctrl-0 = <&twsi0_pmux>;
228 pinctrl-names = "default";
233 compatible = "snps,designware-i2c";
234 #address-cells = <1>;
236 reg = <0x1800 0x100>;
237 interrupt-parent = <&aic>;
239 clocks = <&chip CLKID_CFG>;
240 pinctrl-0 = <&twsi1_pmux>;
241 pinctrl-names = "default";
246 compatible = "snps,dw-apb-timer";
248 clocks = <&chip CLKID_CFG>;
249 clock-names = "timer";
254 compatible = "snps,dw-apb-timer";
256 clocks = <&chip CLKID_CFG>;
257 clock-names = "timer";
262 compatible = "snps,dw-apb-timer";
264 clocks = <&chip CLKID_CFG>;
265 clock-names = "timer";
270 compatible = "snps,dw-apb-timer";
272 clocks = <&chip CLKID_CFG>;
273 clock-names = "timer";
278 compatible = "snps,dw-apb-timer";
280 clocks = <&chip CLKID_CFG>;
281 clock-names = "timer";
286 compatible = "snps,dw-apb-timer";
288 clocks = <&chip CLKID_CFG>;
289 clock-names = "timer";
294 compatible = "snps,dw-apb-timer";
296 clocks = <&chip CLKID_CFG>;
297 clock-names = "timer";
302 compatible = "snps,dw-apb-timer";
304 clocks = <&chip CLKID_CFG>;
305 clock-names = "timer";
309 aic: interrupt-controller@3800 {
310 compatible = "snps,dw-apb-ictl";
312 interrupt-controller;
313 #interrupt-cells = <1>;
314 interrupt-parent = <&gic>;
315 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
319 compatible = "snps,dw-apb-gpio";
320 reg = <0x5000 0x400>;
321 #address-cells = <1>;
325 compatible = "snps,dw-apb-gpio-port";
328 snps,nr-gpios = <32>;
334 compatible = "snps,dw-apb-gpio";
335 reg = <0xc000 0x400>;
336 #address-cells = <1>;
340 compatible = "snps,dw-apb-gpio-port";
343 snps,nr-gpios = <32>;
349 chip: chip-control@ea0000 {
350 compatible = "marvell,berlin2q-chip-ctrl";
352 reg = <0xea0000 0x400>, <0xdd0170 0x10>;
354 clock-names = "refclk";
356 twsi0_pmux: twsi0-pmux {
361 twsi1_pmux: twsi1-pmux {
368 compatible = "simple-bus";
369 #address-cells = <1>;
372 ranges = <0 0xfc0000 0x10000>;
373 interrupt-parent = <&sic>;
376 compatible = "snps,designware-i2c";
377 #address-cells = <1>;
379 reg = <0x7000 0x100>;
380 interrupt-parent = <&sic>;
383 pinctrl-0 = <&twsi2_pmux>;
384 pinctrl-names = "default";
389 compatible = "snps,designware-i2c";
390 #address-cells = <1>;
392 reg = <0x8000 0x100>;
393 interrupt-parent = <&sic>;
396 pinctrl-0 = <&twsi3_pmux>;
397 pinctrl-names = "default";
402 compatible = "snps,dw-apb-uart";
403 reg = <0x9000 0x100>;
404 interrupt-parent = <&sic>;
408 pinctrl-0 = <&uart0_pmux>;
409 pinctrl-names = "default";
414 compatible = "snps,dw-apb-uart";
415 reg = <0xa000 0x100>;
416 interrupt-parent = <&sic>;
420 pinctrl-0 = <&uart1_pmux>;
421 pinctrl-names = "default";
425 sysctrl: pin-controller@d000 {
426 compatible = "marvell,berlin2q-system-ctrl";
427 reg = <0xd000 0x100>;
429 uart0_pmux: uart0-pmux {
434 uart1_pmux: uart1-pmux {
439 twsi2_pmux: twsi2-pmux {
444 twsi3_pmux: twsi3-pmux {
450 sic: interrupt-controller@e000 {
451 compatible = "snps,dw-apb-ictl";
453 interrupt-controller;
454 #interrupt-cells = <1>;
455 interrupt-parent = <&gic>;
456 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;