2 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include <dt-bindings/clock/berlin2q.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "skeleton.dtsi"
15 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
16 compatible = "marvell,berlin2q", "marvell,berlin";
21 enable-method = "marvell,berlin-smp";
24 compatible = "arm,cortex-a9";
26 next-level-cache = <&l2>;
31 compatible = "arm,cortex-a9";
33 next-level-cache = <&l2>;
38 compatible = "arm,cortex-a9";
40 next-level-cache = <&l2>;
45 compatible = "arm,cortex-a9";
47 next-level-cache = <&l2>;
53 compatible = "fixed-clock";
55 clock-frequency = <25000000>;
59 compatible = "simple-bus";
63 ranges = <0 0xf7000000 0x1000000>;
64 interrupt-parent = <&gic>;
66 sdhci0: sdhci@ab0000 {
67 compatible = "mrvl,pxav3-mmc";
68 reg = <0xab0000 0x200>;
69 clocks = <&chip CLKID_SDIO1XIN>;
70 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
74 sdhci1: sdhci@ab0800 {
75 compatible = "mrvl,pxav3-mmc";
76 reg = <0xab0800 0x200>;
77 clocks = <&chip CLKID_SDIO1XIN>;
78 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
82 sdhci2: sdhci@ab1000 {
83 compatible = "mrvl,pxav3-mmc";
84 reg = <0xab1000 0x200>;
85 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
86 clocks = <&chip CLKID_SDIO1XIN>;
90 l2: l2-cache-controller@ac0000 {
91 compatible = "arm,pl310-cache";
92 reg = <0xac0000 0x1000>;
94 arm,data-latency = <2 2 2>;
95 arm,tag-latency = <2 2 2>;
98 scu: snoop-control-unit@ad0000 {
99 compatible = "arm,cortex-a9-scu";
100 reg = <0xad0000 0x58>;
104 compatible = "arm,cortex-a9-twd-timer";
105 reg = <0xad0600 0x20>;
106 clocks = <&chip CLKID_TWD>;
107 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
110 gic: interrupt-controller@ad1000 {
111 compatible = "arm,cortex-a9-gic";
112 reg = <0xad1000 0x1000>, <0xad0100 0x100>;
113 interrupt-controller;
114 #interrupt-cells = <3>;
118 compatible = "marvell,berlin-cpu-ctrl";
119 reg = <0xdd0000 0x10000>;
123 compatible = "simple-bus";
124 #address-cells = <1>;
127 ranges = <0 0xe80000 0x10000>;
128 interrupt-parent = <&aic>;
131 compatible = "snps,dw-apb-gpio";
132 reg = <0x0400 0x400>;
133 #address-cells = <1>;
137 compatible = "snps,dw-apb-gpio-port";
140 snps,nr-gpios = <32>;
142 interrupt-controller;
143 #interrupt-cells = <2>;
149 compatible = "snps,dw-apb-gpio";
150 reg = <0x0800 0x400>;
151 #address-cells = <1>;
155 compatible = "snps,dw-apb-gpio-port";
158 snps,nr-gpios = <32>;
160 interrupt-controller;
161 #interrupt-cells = <2>;
167 compatible = "snps,dw-apb-gpio";
168 reg = <0x0c00 0x400>;
169 #address-cells = <1>;
173 compatible = "snps,dw-apb-gpio-port";
176 snps,nr-gpios = <32>;
178 interrupt-controller;
179 #interrupt-cells = <2>;
185 compatible = "snps,dw-apb-gpio";
186 reg = <0x1000 0x400>;
187 #address-cells = <1>;
191 compatible = "snps,dw-apb-gpio-port";
194 snps,nr-gpios = <32>;
196 interrupt-controller;
197 #interrupt-cells = <2>;
203 compatible = "snps,designware-i2c";
204 #address-cells = <1>;
206 reg = <0x1400 0x100>;
207 interrupt-parent = <&aic>;
209 clocks = <&chip CLKID_CFG>;
210 pinctrl-0 = <&twsi0_pmux>;
211 pinctrl-names = "default";
216 compatible = "snps,designware-i2c";
217 #address-cells = <1>;
219 reg = <0x1800 0x100>;
220 interrupt-parent = <&aic>;
222 clocks = <&chip CLKID_CFG>;
223 pinctrl-0 = <&twsi1_pmux>;
224 pinctrl-names = "default";
229 compatible = "snps,dw-apb-timer";
231 clocks = <&chip CLKID_CFG>;
232 clock-names = "timer";
237 compatible = "snps,dw-apb-timer";
239 clocks = <&chip CLKID_CFG>;
240 clock-names = "timer";
245 compatible = "snps,dw-apb-timer";
247 clocks = <&chip CLKID_CFG>;
248 clock-names = "timer";
253 compatible = "snps,dw-apb-timer";
255 clocks = <&chip CLKID_CFG>;
256 clock-names = "timer";
261 compatible = "snps,dw-apb-timer";
263 clocks = <&chip CLKID_CFG>;
264 clock-names = "timer";
269 compatible = "snps,dw-apb-timer";
271 clocks = <&chip CLKID_CFG>;
272 clock-names = "timer";
277 compatible = "snps,dw-apb-timer";
279 clocks = <&chip CLKID_CFG>;
280 clock-names = "timer";
285 compatible = "snps,dw-apb-timer";
287 clocks = <&chip CLKID_CFG>;
288 clock-names = "timer";
292 aic: interrupt-controller@3800 {
293 compatible = "snps,dw-apb-ictl";
295 interrupt-controller;
296 #interrupt-cells = <1>;
297 interrupt-parent = <&gic>;
298 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
302 compatible = "snps,dw-apb-gpio";
303 reg = <0x5000 0x400>;
304 #address-cells = <1>;
308 compatible = "snps,dw-apb-gpio-port";
311 snps,nr-gpios = <32>;
317 compatible = "snps,dw-apb-gpio";
318 reg = <0xc000 0x400>;
319 #address-cells = <1>;
323 compatible = "snps,dw-apb-gpio-port";
326 snps,nr-gpios = <32>;
332 chip: chip-control@ea0000 {
333 compatible = "marvell,berlin2q-chip-ctrl";
335 reg = <0xea0000 0x400>, <0xdd0170 0x10>;
337 clock-names = "refclk";
339 twsi0_pmux: twsi0-pmux {
344 twsi1_pmux: twsi1-pmux {
351 compatible = "simple-bus";
352 #address-cells = <1>;
355 ranges = <0 0xfc0000 0x10000>;
356 interrupt-parent = <&sic>;
359 compatible = "snps,designware-i2c";
360 #address-cells = <1>;
362 reg = <0x7000 0x100>;
363 interrupt-parent = <&sic>;
366 pinctrl-0 = <&twsi2_pmux>;
367 pinctrl-names = "default";
372 compatible = "snps,designware-i2c";
373 #address-cells = <1>;
375 reg = <0x8000 0x100>;
376 interrupt-parent = <&sic>;
379 pinctrl-0 = <&twsi3_pmux>;
380 pinctrl-names = "default";
385 compatible = "snps,dw-apb-uart";
386 reg = <0x9000 0x100>;
387 interrupt-parent = <&sic>;
391 pinctrl-0 = <&uart0_pmux>;
392 pinctrl-names = "default";
397 compatible = "snps,dw-apb-uart";
398 reg = <0xa000 0x100>;
399 interrupt-parent = <&sic>;
403 pinctrl-0 = <&uart1_pmux>;
404 pinctrl-names = "default";
408 sysctrl: pin-controller@d000 {
409 compatible = "marvell,berlin2q-system-ctrl";
410 reg = <0xd000 0x100>;
412 uart0_pmux: uart0-pmux {
417 uart1_pmux: uart1-pmux {
422 twsi2_pmux: twsi2-pmux {
427 twsi3_pmux: twsi3-pmux {
433 sic: interrupt-controller@e000 {
434 compatible = "snps,dw-apb-ictl";
436 interrupt-controller;
437 #interrupt-cells = <1>;
438 interrupt-parent = <&gic>;
439 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;