2 * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 * based on GPL'ed 2.6 kernel sources
7 * (c) Marvell International Ltd.
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include "skeleton.dtsi"
15 #include <dt-bindings/clock/berlin2.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 model = "Marvell Armada 1500 (BG2) SoC";
20 compatible = "marvell,berlin2", "marvell,berlin";
25 enable-method = "marvell,berlin-smp";
28 compatible = "marvell,pj4b";
30 next-level-cache = <&l2>;
35 compatible = "marvell,pj4b";
37 next-level-cache = <&l2>;
43 compatible = "fixed-clock";
45 clock-frequency = <25000000>;
49 compatible = "simple-bus";
52 interrupt-parent = <&gic>;
54 ranges = <0 0xf7000000 0x1000000>;
56 l2: l2-cache-controller@ac0000 {
57 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
58 reg = <0xac0000 0x1000>;
63 scu: snoop-control-unit@ad0000 {
64 compatible = "arm,cortex-a9-scu";
65 reg = <0xad0000 0x58>;
68 gic: interrupt-controller@ad1000 {
69 compatible = "arm,cortex-a9-gic";
70 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
72 #interrupt-cells = <3>;
76 compatible = "arm,cortex-a9-twd-timer";
77 reg = <0xad0600 0x20>;
78 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
79 clocks = <&chip CLKID_TWD>;
83 compatible = "marvell,berlin-cpu-ctrl";
84 reg = <0xdd0000 0x10000>;
88 compatible = "simple-bus";
92 ranges = <0 0xe80000 0x10000>;
93 interrupt-parent = <&aic>;
96 compatible = "snps,dw-apb-gpio";
102 compatible = "snps,dw-apb-gpio-port";
107 interrupt-controller;
108 #interrupt-cells = <2>;
114 compatible = "snps,dw-apb-gpio";
115 reg = <0x0800 0x400>;
116 #address-cells = <1>;
120 compatible = "snps,dw-apb-gpio-port";
125 interrupt-controller;
126 #interrupt-cells = <2>;
132 compatible = "snps,dw-apb-gpio";
133 reg = <0x0c00 0x400>;
134 #address-cells = <1>;
138 compatible = "snps,dw-apb-gpio-port";
143 interrupt-controller;
144 #interrupt-cells = <2>;
150 compatible = "snps,dw-apb-gpio";
151 reg = <0x1000 0x400>;
152 #address-cells = <1>;
156 compatible = "snps,dw-apb-gpio-port";
161 interrupt-controller;
162 #interrupt-cells = <2>;
168 compatible = "snps,dw-apb-timer";
171 clocks = <&chip CLKID_CFG>;
172 clock-names = "timer";
177 compatible = "snps,dw-apb-timer";
180 clocks = <&chip CLKID_CFG>;
181 clock-names = "timer";
186 compatible = "snps,dw-apb-timer";
189 clocks = <&chip CLKID_CFG>;
190 clock-names = "timer";
195 compatible = "snps,dw-apb-timer";
198 clocks = <&chip CLKID_CFG>;
199 clock-names = "timer";
204 compatible = "snps,dw-apb-timer";
207 clocks = <&chip CLKID_CFG>;
208 clock-names = "timer";
213 compatible = "snps,dw-apb-timer";
216 clocks = <&chip CLKID_CFG>;
217 clock-names = "timer";
222 compatible = "snps,dw-apb-timer";
225 clocks = <&chip CLKID_CFG>;
226 clock-names = "timer";
231 compatible = "snps,dw-apb-timer";
234 clocks = <&chip CLKID_CFG>;
235 clock-names = "timer";
239 aic: interrupt-controller@3000 {
240 compatible = "snps,dw-apb-ictl";
241 reg = <0x3000 0xc00>;
242 interrupt-controller;
243 #interrupt-cells = <1>;
244 interrupt-parent = <&gic>;
245 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
249 chip: chip-control@ea0000 {
250 compatible = "marvell,berlin2-chip-ctrl";
252 reg = <0xea0000 0x400>;
254 clock-names = "refclk";
258 compatible = "simple-bus";
259 #address-cells = <1>;
262 ranges = <0 0xfc0000 0x10000>;
263 interrupt-parent = <&sic>;
265 sm_gpio1: gpio@5000 {
266 compatible = "snps,dw-apb-gpio";
267 reg = <0x5000 0x400>;
268 #address-cells = <1>;
272 compatible = "snps,dw-apb-gpio-port";
280 sm_gpio0: gpio@c000 {
281 compatible = "snps,dw-apb-gpio";
282 reg = <0xc000 0x400>;
283 #address-cells = <1>;
287 compatible = "snps,dw-apb-gpio-port";
292 interrupt-controller;
293 #interrupt-cells = <2>;
299 compatible = "snps,dw-apb-uart";
300 reg = <0x9000 0x100>;
305 pinctrl-0 = <&uart0_pmux>;
306 pinctrl-names = "default";
311 compatible = "snps,dw-apb-uart";
312 reg = <0xa000 0x100>;
317 pinctrl-0 = <&uart1_pmux>;
318 pinctrl-names = "default";
323 compatible = "snps,dw-apb-uart";
324 reg = <0xb000 0x100>;
329 pinctrl-0 = <&uart2_pmux>;
330 pinctrl-names = "default";
334 sysctrl: system-controller@d000 {
335 compatible = "marvell,berlin2-system-ctrl";
336 reg = <0xd000 0x100>;
338 uart0_pmux: uart0-pmux {
343 uart1_pmux: uart1-pmux {
348 uart2_pmux: uart2-pmux {
354 sic: interrupt-controller@e000 {
355 compatible = "snps,dw-apb-ictl";
356 reg = <0xe000 0x400>;
357 interrupt-controller;
358 #interrupt-cells = <1>;
359 interrupt-parent = <&gic>;
360 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;