arch/arm/boot/dts/atlas6.dtsi

   1 /*
   2  * DTS file for CSR SiRFatlas6 SoC
   3  *
   4  * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10 / {
  11         compatible = "sirf,atlas6";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&intc>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         reg = <0x0>;
  22                         d-cache-line-size = <32>;
  23                         i-cache-line-size = <32>;
  24                         d-cache-size = <32768>;
  25                         i-cache-size = <32768>;
  26                         /* from bootloader */
  27                         timebase-frequency = <0>;
  28                         bus-frequency = <0>;
  29                         clock-frequency = <0>;
  30                         clocks = <&clks 12>;
  31                         operating-points = <
  32                                 /* kHz    uV */
  33                                 200000  1025000
  34                                 400000  1025000
  35                                 600000  1050000
  36                                 800000  1100000
  37                         >;
  38                         clock-latency = <150000>;
  39                 };
  40         };
  41
  42         arm-pmu {
  43                 compatible = "arm,cortex-a9-pmu";
  44                 interrupts = <29>;
  45         };
  46
  47         axi {
  48                 compatible = "simple-bus";
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 ranges = <0x40000000 0x40000000 0x80000000>;
  52
  53                 intc: interrupt-controller@80020000 {
  54                         #interrupt-cells = <1>;
  55                         interrupt-controller;
  56                         compatible = "sirf,prima2-intc";
  57                         reg = <0x80020000 0x1000>;
  58                 };
  59
  60                 sys-iobg {
  61                         compatible = "simple-bus";
  62                         #address-cells = <1>;
  63                         #size-cells = <1>;
  64                         ranges = <0x88000000 0x88000000 0x40000>;
  65
  66                         clks: clock-controller@88000000 {
  67                                 compatible = "sirf,atlas6-clkc";
  68                                 reg = <0x88000000 0x1000>;
  69                                 interrupts = <3>;
  70                                 #clock-cells = <1>;
  71                         };
  72
  73                         rstc: reset-controller@88010000 {
  74                                 compatible = "sirf,prima2-rstc";
  75                                 reg = <0x88010000 0x1000>;
  76                                 #reset-cells = <1>;
  77                         };
  78
  79                         rsc-controller@88020000 {
  80                                 compatible = "sirf,prima2-rsc";
  81                                 reg = <0x88020000 0x1000>;
  82                         };
  83
  84                         cphifbg@88030000 {
  85                                 compatible = "sirf,prima2-cphifbg";
  86                                 reg = <0x88030000 0x1000>;
  87                                 clocks = <&clks 42>;
  88                         };
  89                 };
  90
  91                 mem-iobg {
  92                         compatible = "simple-bus";
  93                         #address-cells = <1>;
  94                         #size-cells = <1>;
  95                         ranges = <0x90000000 0x90000000 0x10000>;
  96
  97                         memory-controller@90000000 {
  98                                 compatible = "sirf,prima2-memc";
  99                                 reg = <0x90000000 0x2000>;
 100                                 interrupts = <27>;
 101                                 clocks = <&clks 5>;
 102                         };
 103
 104                         memc-monitor {
 105                                 compatible = "sirf,prima2-memcmon";
 106                                 reg = <0x90002000 0x200>;
 107                                 interrupts = <4>;
 108                                 clocks = <&clks 32>;
 109                         };
 110                 };
 111
 112                 disp-iobg {
 113                         compatible = "simple-bus";
 114                         #address-cells = <1>;
 115                         #size-cells = <1>;
 116                         ranges = <0x90010000 0x90010000 0x30000>;
 117
 118                         lcd@90010000 {
 119                                 compatible = "sirf,prima2-lcd";
 120                                 reg = <0x90010000 0x20000>;
 121                                 interrupts = <30>;
 122                                 clocks = <&clks 34>;
 123                                 display=<&display>;
 124                                 /* later transfer to pwm */
 125                                 bl-gpio = <&gpio 7 0>;
 126                                 default-panel = <&panel0>;
 127                         };
 128
 129                         vpp@90020000 {
 130                                 compatible = "sirf,prima2-vpp";
 131                                 reg = <0x90020000 0x10000>;
 132                                 interrupts = <31>;
 133                                 clocks = <&clks 35>;
 134                         };
 135                 };
 136
 137                 graphics-iobg {
 138                         compatible = "simple-bus";
 139                         #address-cells = <1>;
 140                         #size-cells = <1>;
 141                         ranges = <0x98000000 0x98000000 0x8000000>;
 142
 143                         graphics@98000000 {
 144                                 compatible = "powervr,sgx510";
 145                                 reg = <0x98000000 0x8000000>;
 146                                 interrupts = <6>;
 147                                 clocks = <&clks 32>;
 148                         };
 149                 };
 150
 151                 graphics2d-iobg {
 152                         compatible = "simple-bus";
 153                         #address-cells = <1>;
 154                         #size-cells = <1>;
 155                         ranges = <0xa0000000 0xa0000000 0x8000000>;
 156
 157                         ble@a0000000 {
 158                                 compatible = "sirf,atlas6-ble";
 159                                 reg = <0xa0000000 0x2000>;
 160                                 interrupts = <5>;
 161                                 clocks = <&clks 33>;
 162                         };
 163                 };
 164
 165                 dsp-iobg {
 166                         compatible = "simple-bus";
 167                         #address-cells = <1>;
 168                         #size-cells = <1>;
 169                         ranges = <0xa8000000 0xa8000000 0x2000000>;
 170
 171                         dspif@a8000000 {
 172                                 compatible = "sirf,prima2-dspif";
 173                                 reg = <0xa8000000 0x10000>;
 174                                 interrupts = <9>;
 175                                 resets = <&rstc 1>;
 176                         };
 177
 178                         gps@a8010000 {
 179                                 compatible = "sirf,prima2-gps";
 180                                 reg = <0xa8010000 0x10000>;
 181                                 interrupts = <7>;
 182                                 clocks = <&clks 9>;
 183                                 resets = <&rstc 2>;
 184                         };
 185
 186                         dsp@a9000000 {
 187                                 compatible = "sirf,prima2-dsp";
 188                                 reg = <0xa9000000 0x1000000>;
 189                                 interrupts = <8>;
 190                                 clocks = <&clks 8>;
 191                                 resets = <&rstc 0>;
 192                         };
 193                 };
 194
 195                 peri-iobg {
 196                         compatible = "simple-bus";
 197                         #address-cells = <1>;
 198                         #size-cells = <1>;
 199                         ranges = <0xb0000000 0xb0000000 0x180000>,
 200                                <0x56000000 0x56000000 0x1b00000>;
 201
 202                         timer@b0020000 {
 203                                 compatible = "sirf,prima2-tick";
 204                                 reg = <0xb0020000 0x1000>;
 205                                 interrupts = <0>;
 206                                 clocks = <&clks 11>;
 207                         };
 208
 209                         nand@b0030000 {
 210                                 compatible = "sirf,prima2-nand";
 211                                 reg = <0xb0030000 0x10000>;
 212                                 interrupts = <41>;
 213                                 clocks = <&clks 26>;
 214                         };
 215
 216                         audio@b0040000 {
 217                                 compatible = "sirf,prima2-audio";
 218                                 reg = <0xb0040000 0x10000>;
 219                                 interrupts = <35>;
 220                                 clocks = <&clks 27>;
 221                         };
 222
 223                         uart0: uart@b0050000 {
 224                                 cell-index = <0>;
 225                                 compatible = "sirf,prima2-uart";
 226                                 reg = <0xb0050000 0x1000>;
 227                                 interrupts = <17>;
 228                                 fifosize = <128>;
 229                                 clocks = <&clks 13>;
 230                                 dmas = <&dmac1 5>, <&dmac0 2>;
 231                                 dma-names = "rx", "tx";
 232                         };
 233
 234                         uart1: uart@b0060000 {
 235                                 cell-index = <1>;
 236                                 compatible = "sirf,prima2-uart";
 237                                 reg = <0xb0060000 0x1000>;
 238                                 interrupts = <18>;
 239                                 fifosize = <32>;
 240                                 clocks = <&clks 14>;
 241                                 dma-names = "no-rx", "no-tx";
 242                         };
 243
 244                         uart2: uart@b0070000 {
 245                                 cell-index = <2>;
 246                                 compatible = "sirf,prima2-uart";
 247                                 reg = <0xb0070000 0x1000>;
 248                                 interrupts = <19>;
 249                                 fifosize = <128>;
 250                                 clocks = <&clks 15>;
 251                                 dmas = <&dmac0 6>, <&dmac0 7>;
 252                                 dma-names = "rx", "tx";
 253                         };
 254
 255                         usp0: usp@b0080000 {
 256                                 cell-index = <0>;
 257                                 compatible = "sirf,prima2-usp";
 258                                 reg = <0xb0080000 0x10000>;
 259                                 interrupts = <20>;
 260                                 fifosize = <128>;
 261                                 clocks = <&clks 28>;
 262                                 dmas = <&dmac1 1>, <&dmac1 2>;
 263                                 dma-names = "rx", "tx";
 264                         };
 265
 266                         usp1: usp@b0090000 {
 267                                 cell-index = <1>;
 268                                 compatible = "sirf,prima2-usp";
 269                                 reg = <0xb0090000 0x10000>;
 270                                 interrupts = <21>;
 271                                 fifosize = <128>;
 272                                 clocks = <&clks 29>;
 273                                 dmas = <&dmac0 14>, <&dmac0 15>;
 274                                 dma-names = "rx", "tx";
 275                         };
 276
 277                         dmac0: dma-controller@b00b0000 {
 278                                 cell-index = <0>;
 279                                 compatible = "sirf,prima2-dmac";
 280                                 reg = <0xb00b0000 0x10000>;
 281                                 interrupts = <12>;
 282                                 clocks = <&clks 24>;
 283                                 #dma-cells = <1>;
 284                         };
 285
 286                         dmac1: dma-controller@b0160000 {
 287                                 cell-index = <1>;
 288                                 compatible = "sirf,prima2-dmac";
 289                                 reg = <0xb0160000 0x10000>;
 290                                 interrupts = <13>;
 291                                 clocks = <&clks 25>;
 292                                 #dma-cells = <1>;
 293                         };
 294
 295                         vip@b00C0000 {
 296                                 compatible = "sirf,prima2-vip";
 297                                 reg = <0xb00C0000 0x10000>;
 298                                 clocks = <&clks 31>;
 299                                 interrupts = <14>;
 300                                 sirf,vip-dma-rx-channel = <16>;
 301                         };
 302
 303                         spi0: spi@b00d0000 {
 304                                 cell-index = <0>;
 305                                 compatible = "sirf,prima2-spi";
 306                                 reg = <0xb00d0000 0x10000>;
 307                                 interrupts = <15>;
 308                                 sirf,spi-num-chipselects = <1>;
 309                                 dmas = <&dmac1 9>,
 310                                      <&dmac1 4>;
 311                                 dma-names = "rx", "tx";
 312                                 #address-cells = <1>;
 313                                 #size-cells = <0>;
 314                                 clocks = <&clks 19>;
 315                                 status = "disabled";
 316                         };
 317
 318                         spi1: spi@b0170000 {
 319                                 cell-index = <1>;
 320                                 compatible = "sirf,prima2-spi";
 321                                 reg = <0xb0170000 0x10000>;
 322                                 interrupts = <16>;
 323                                 sirf,spi-num-chipselects = <1>;
 324                                 dmas = <&dmac0 12>,
 325                                      <&dmac0 13>;
 326                                 dma-names = "rx", "tx";
 327                                 #address-cells = <1>;
 328                                 #size-cells = <0>;
 329                                 clocks = <&clks 20>;
 330                                 status = "disabled";
 331                         };
 332
 333                         i2c0: i2c@b00e0000 {
 334                                 cell-index = <0>;
 335                                 compatible = "sirf,prima2-i2c";
 336                                 reg = <0xb00e0000 0x10000>;
 337                                 interrupts = <24>;
 338                                 #address-cells = <1>;
 339                                 #size-cells = <0>;
 340                                 clocks = <&clks 17>;
 341                         };
 342
 343                         i2c1: i2c@b00f0000 {
 344                                 cell-index = <1>;
 345                                 compatible = "sirf,prima2-i2c";
 346                                 reg = <0xb00f0000 0x10000>;
 347                                 interrupts = <25>;
 348                                 #address-cells = <1>;
 349                                 #size-cells = <0>;
 350                                 clocks = <&clks 18>;
 351                         };
 352
 353                         tsc@b0110000 {
 354                                 compatible = "sirf,prima2-tsc";
 355                                 reg = <0xb0110000 0x10000>;
 356                                 interrupts = <33>;
 357                                 clocks = <&clks 16>;
 358                         };
 359
 360                         gpio: pinctrl@b0120000 {
 361                                 #gpio-cells = <2>;
 362                                 #interrupt-cells = <2>;
 363                                 compatible = "sirf,atlas6-pinctrl";
 364                                 reg = <0xb0120000 0x10000>;
 365                                 interrupts = <43 44 45 46 47>;
 366                                 gpio-controller;
 367                                 interrupt-controller;
 368
 369                                 lcd_16pins_a: lcd0@0 {
 370                                         lcd {
 371                                                 sirf,pins = "lcd_16bitsgrp";
 372                                                 sirf,function = "lcd_16bits";
 373                                         };
 374                                 };
 375                                 lcd_18pins_a: lcd0@1 {
 376                                         lcd {
 377                                                 sirf,pins = "lcd_18bitsgrp";
 378                                                 sirf,function = "lcd_18bits";
 379                                         };
 380                                 };
 381                                 lcd_24pins_a: lcd0@2 {
 382                                         lcd {
 383                                                 sirf,pins = "lcd_24bitsgrp";
 384                                                 sirf,function = "lcd_24bits";
 385                                         };
 386                                 };
 387                                 lcdrom_pins_a: lcdrom0@0 {
 388                                         lcd {
 389                                                 sirf,pins = "lcdromgrp";
 390                                                 sirf,function = "lcdrom";
 391                                         };
 392                                 };
 393                                 uart0_pins_a: uart0@0 {
 394                                         uart {
 395                                                 sirf,pins = "uart0grp";
 396                                                 sirf,function = "uart0";
 397                                         };
 398                                 };
 399                                 uart0_noflow_pins_a: uart0@1 {
 400                                         uart {
 401                                                 sirf,pins = "uart0_nostreamctrlgrp";
 402                                                 sirf,function = "uart0_nostreamctrl";
 403                                         };
 404                                 };
 405                                 uart1_pins_a: uart1@0 {
 406                                         uart {
 407                                                 sirf,pins = "uart1grp";
 408                                                 sirf,function = "uart1";
 409                                         };
 410                                 };
 411                                 uart2_pins_a: uart2@0 {
 412                                         uart {
 413                                                 sirf,pins = "uart2grp";
 414                                                 sirf,function = "uart2";
 415                                         };
 416                                 };
 417                                 uart2_noflow_pins_a: uart2@1 {
 418                                         uart {
 419                                                 sirf,pins = "uart2_nostreamctrlgrp";
 420                                                 sirf,function = "uart2_nostreamctrl";
 421                                         };
 422                                 };
 423                                 spi0_pins_a: spi0@0 {
 424                                         spi {
 425                                                 sirf,pins = "spi0grp";
 426                                                 sirf,function = "spi0";
 427                                         };
 428                                 };
 429                                 spi1_pins_a: spi1@0 {
 430                                         spi {
 431                                                 sirf,pins = "spi1grp";
 432                                                 sirf,function = "spi1";
 433                                         };
 434                                 };
 435                                 i2c0_pins_a: i2c0@0 {
 436                                         i2c {
 437                                                 sirf,pins = "i2c0grp";
 438                                                 sirf,function = "i2c0";
 439                                         };
 440                                 };
 441                                 i2c1_pins_a: i2c1@0 {
 442                                         i2c {
 443                                                 sirf,pins = "i2c1grp";
 444                                                 sirf,function = "i2c1";
 445                                         };
 446                                 };
 447                                 pwm0_pins_a: pwm0@0 {
 448                                         pwm {
 449                                                 sirf,pins = "pwm0grp";
 450                                                 sirf,function = "pwm0";
 451                                         };
 452                                 };
 453                                 pwm1_pins_a: pwm1@0 {
 454                                         pwm {
 455                                                 sirf,pins = "pwm1grp";
 456                                                 sirf,function = "pwm1";
 457                                         };
 458                                 };
 459                                 pwm2_pins_a: pwm2@0 {
 460                                         pwm {
 461                                                 sirf,pins = "pwm2grp";
 462                                                 sirf,function = "pwm2";
 463                                         };
 464                                 };
 465                                 pwm3_pins_a: pwm3@0 {
 466                                         pwm {
 467                                                 sirf,pins = "pwm3grp";
 468                                                 sirf,function = "pwm3";
 469                                         };
 470                                 };
 471                                 pwm4_pins_a: pwm4@0 {
 472                                         pwm {
 473                                                 sirf,pins = "pwm4grp";
 474                                                 sirf,function = "pwm4";
 475                                         };
 476                                 };
 477                                 gps_pins_a: gps@0 {
 478                                         gps {
 479                                                 sirf,pins = "gpsgrp";
 480                                                 sirf,function = "gps";
 481                                         };
 482                                 };
 483                                 vip_pins_a: vip@0 {
 484                                         vip {
 485                                                 sirf,pins = "vipgrp";
 486                                                 sirf,function = "vip";
 487                                         };
 488                                 };
 489                                 sdmmc0_pins_a: sdmmc0@0 {
 490                                         sdmmc0 {
 491                                                 sirf,pins = "sdmmc0grp";
 492                                                 sirf,function = "sdmmc0";
 493                                         };
 494                                 };
 495                                 sdmmc1_pins_a: sdmmc1@0 {
 496                                         sdmmc1 {
 497                                                 sirf,pins = "sdmmc1grp";
 498                                                 sirf,function = "sdmmc1";
 499                                         };
 500                                 };
 501                                 sdmmc2_pins_a: sdmmc2@0 {
 502                                         sdmmc2 {
 503                                                 sirf,pins = "sdmmc2grp";
 504                                                 sirf,function = "sdmmc2";
 505                                         };
 506                                 };
 507                                 sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
 508                                         sdmmc2_nowp {
 509                                                 sirf,pins = "sdmmc2_nowpgrp";
 510                                                 sirf,function = "sdmmc2_nowp";
 511                                         };
 512                                 };
 513                                 sdmmc3_pins_a: sdmmc3@0 {
 514                                         sdmmc3 {
 515                                                 sirf,pins = "sdmmc3grp";
 516                                                 sirf,function = "sdmmc3";
 517                                         };
 518                                 };
 519                                 sdmmc5_pins_a: sdmmc5@0 {
 520                                         sdmmc5 {
 521                                                 sirf,pins = "sdmmc5grp";
 522                                                 sirf,function = "sdmmc5";
 523                                         };
 524                                 };
 525                                 i2s_pins_a: i2s@0 {
 526                                         i2s {
 527                                                 sirf,pins = "i2sgrp";
 528                                                 sirf,function = "i2s";
 529                                         };
 530                                 };
 531                                 i2s_no_din_pins_a: i2s_no_din@0 {
 532                                         i2s_no_din {
 533                                                 sirf,pins = "i2s_no_dingrp";
 534                                                 sirf,function = "i2s_no_din";
 535                                         };
 536                                 };
 537                                 i2s_6chn_pins_a: i2s_6chn@0 {
 538                                         i2s_6chn {
 539                                                 sirf,pins = "i2s_6chngrp";
 540                                                 sirf,function = "i2s_6chn";
 541                                         };
 542                                 };
 543                                 ac97_pins_a: ac97@0 {
 544                                         ac97 {
 545                                                 sirf,pins = "ac97grp";
 546                                                 sirf,function = "ac97";
 547                                         };
 548                                 };
 549                                 nand_pins_a: nand@0 {
 550                                         nand {
 551                                                 sirf,pins = "nandgrp";
 552                                                 sirf,function = "nand";
 553                                         };
 554                                 };
 555                                 usp0_pins_a: usp0@0 {
 556                                         usp0 {
 557                                                 sirf,pins = "usp0grp";
 558                                                 sirf,function = "usp0";
 559                                         };
 560                                 };
 561                                 usp0_uart_nostreamctrl_pins_a: usp0@1 {
 562                                         usp0 {
 563                                                 sirf,pins = "usp0_uart_nostreamctrl_grp";
 564                                                 sirf,function = "usp0_uart_nostreamctrl";
 565                                         };
 566                                 };
 567                                 usp0_only_utfs_pins_a: usp0@2 {
 568                                         usp0 {
 569                                                 sirf,pins = "usp0_only_utfs_grp";
 570                                                 sirf,function = "usp0_only_utfs";
 571                                         };
 572                                 };
 573                                 usp0_only_urfs_pins_a: usp0@3 {
 574                                         usp0 {
 575                                                 sirf,pins = "usp0_only_urfs_grp";
 576                                                 sirf,function = "usp0_only_urfs";
 577                                         };
 578                                 };
 579                                 usp1_pins_a: usp1@0 {
 580                                         usp1 {
 581                                                 sirf,pins = "usp1grp";
 582                                                 sirf,function = "usp1";
 583                                         };
 584                                 };
 585                                 usp1_uart_nostreamctrl_pins_a: usp1@1 {
 586                                         usp1 {
 587                                                 sirf,pins = "usp1_uart_nostreamctrl_grp";
 588                                                 sirf,function = "usp1_uart_nostreamctrl";
 589                                         };
 590                                 };
 591                                 usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
 592                                         usb0_upli_drvbus {
 593                                                 sirf,pins = "usb0_upli_drvbusgrp";
 594                                                 sirf,function = "usb0_upli_drvbus";
 595                                         };
 596                                 };
 597                                 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
 598                                         usb1_utmi_drvbus {
 599                                                 sirf,pins = "usb1_utmi_drvbusgrp";
 600                                                 sirf,function = "usb1_utmi_drvbus";
 601                                         };
 602                                 };
 603                                 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
 604                                         usb1_dp_dn {
 605                                                 sirf,pins = "usb1_dp_dngrp";
 606                                                 sirf,function = "usb1_dp_dn";
 607                                         };
 608                                 };
 609                                 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
 610                                         uart1_route_io_usb1 {
 611                                                 sirf,pins = "uart1_route_io_usb1grp";
 612                                                 sirf,function = "uart1_route_io_usb1";
 613                                         };
 614                                 };
 615                                 warm_rst_pins_a: warm_rst@0 {
 616                                         warm_rst {
 617                                                 sirf,pins = "warm_rstgrp";
 618                                                 sirf,function = "warm_rst";
 619                                         };
 620                                 };
 621                                 pulse_count_pins_a: pulse_count@0 {
 622                                         pulse_count {
 623                                                 sirf,pins = "pulse_countgrp";
 624                                                 sirf,function = "pulse_count";
 625                                         };
 626                                 };
 627                                 cko0_pins_a: cko0@0 {
 628                                         cko0 {
 629                                                 sirf,pins = "cko0grp";
 630                                                 sirf,function = "cko0";
 631                                         };
 632                                 };
 633                                 cko1_pins_a: cko1@0 {
 634                                         cko1 {
 635                                                 sirf,pins = "cko1grp";
 636                                                 sirf,function = "cko1";
 637                                         };
 638                                 };
 639                         };
 640
 641                         pwm@b0130000 {
 642                                 compatible = "sirf,prima2-pwm";
 643                                 reg = <0xb0130000 0x10000>;
 644                                 clocks = <&clks 21>;
 645                         };
 646
 647                         efusesys@b0140000 {
 648                                 compatible = "sirf,prima2-efuse";
 649                                 reg = <0xb0140000 0x10000>;
 650                                 clocks = <&clks 22>;
 651                         };
 652
 653                         pulsec@b0150000 {
 654                                 compatible = "sirf,prima2-pulsec";
 655                                 reg = <0xb0150000 0x10000>;
 656                                 interrupts = <48>;
 657                                 clocks = <&clks 23>;
 658                         };
 659
 660                         pci-iobg {
 661                                 compatible = "sirf,prima2-pciiobg", "simple-bus";
 662                                 #address-cells = <1>;
 663                                 #size-cells = <1>;
 664                                 ranges = <0x56000000 0x56000000 0x1b00000>;
 665
 666                                 sd0: sdhci@56000000 {
 667                                         cell-index = <0>;
 668                                         compatible = "sirf,prima2-sdhc";
 669                                         reg = <0x56000000 0x100000>;
 670                                         interrupts = <38>;
 671                                         bus-width = <8>;
 672                                         clocks = <&clks 36>;
 673                                 };
 674
 675                                 sd1: sdhci@56100000 {
 676                                         cell-index = <1>;
 677                                         compatible = "sirf,prima2-sdhc";
 678                                         reg = <0x56100000 0x100000>;
 679                                         interrupts = <38>;
 680                                         status = "disabled";
 681                                         bus-width = <4>;
 682                                         clocks = <&clks 36>;
 683                                 };
 684
 685                                 sd2: sdhci@56200000 {
 686                                         cell-index = <2>;
 687                                         compatible = "sirf,prima2-sdhc";
 688                                         reg = <0x56200000 0x100000>;
 689                                         interrupts = <23>;
 690                                         status = "disabled";
 691                                         bus-width = <4>;
 692                                         clocks = <&clks 37>;
 693                                 };
 694
 695                                 sd3: sdhci@56300000 {
 696                                         cell-index = <3>;
 697                                         compatible = "sirf,prima2-sdhc";
 698                                         reg = <0x56300000 0x100000>;
 699                                         interrupts = <23>;
 700                                         status = "disabled";
 701                                         bus-width = <4>;
 702                                         clocks = <&clks 37>;
 703                                 };
 704
 705                                 sd5: sdhci@56500000 {
 706                                         cell-index = <5>;
 707                                         compatible = "sirf,prima2-sdhc";
 708                                         reg = <0x56500000 0x100000>;
 709                                         interrupts = <39>;
 710                                         status = "disabled";
 711                                         bus-width = <4>;
 712                                         clocks = <&clks 38>;
 713                                 };
 714
 715                                 pci-copy@57900000 {
 716                                         compatible = "sirf,prima2-pcicp";
 717                                         reg = <0x57900000 0x100000>;
 718                                         interrupts = <40>;
 719                                 };
 720
 721                                 rom-interface@57a00000 {
 722                                         compatible = "sirf,prima2-romif";
 723                                         reg = <0x57a00000 0x100000>;
 724                                 };
 725                         };
 726                 };
 727
 728                 rtc-iobg {
 729                         compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
 730                         #address-cells = <1>;
 731                         #size-cells = <1>;
 732                         reg = <0x80030000 0x10000>;
 733
 734                         gpsrtc@1000 {
 735                                 compatible = "sirf,prima2-gpsrtc";
 736                                 reg = <0x1000 0x1000>;
 737                                 interrupts = <55 56 57>;
 738                         };
 739
 740                         sysrtc@2000 {
 741                                 compatible = "sirf,prima2-sysrtc";
 742                                 reg = <0x2000 0x1000>;
 743                                 interrupts = <52 53 54>;
 744                         };
 745
 746                         minigpsrtc@2000 {
 747                                 compatible = "sirf,prima2-minigpsrtc";
 748                                 reg = <0x2000 0x1000>;
 749                                 interrupts = <54>;
 750                         };
 751
 752                         pwrc@3000 {
 753                                 compatible = "sirf,prima2-pwrc";
 754                                 reg = <0x3000 0x1000>;
 755                                 interrupts = <32>;
 756                         };
 757                 };
 758
 759                 uus-iobg {
 760                         compatible = "simple-bus";
 761                         #address-cells = <1>;
 762                         #size-cells = <1>;
 763                         ranges = <0xb8000000 0xb8000000 0x40000>;
 764
 765                         usb0: usb@b00e0000 {
 766                                 compatible = "chipidea,ci13611a-prima2";
 767                                 reg = <0xb8000000 0x10000>;
 768                                 interrupts = <10>;
 769                                 clocks = <&clks 40>;
 770                         };
 771
 772                         usb1: usb@b00f0000 {
 773                                 compatible = "chipidea,ci13611a-prima2";
 774                                 reg = <0xb8010000 0x10000>;
 775                                 interrupts = <11>;
 776                                 clocks = <&clks 41>;
 777                         };
 778
 779                         security@b00f0000 {
 780                                 compatible = "sirf,prima2-security";
 781                                 reg = <0xb8030000 0x10000>;
 782                                 interrupts = <42>;
 783                                 clocks = <&clks 7>;
 784                         };
 785                 };
 786         };
 787 };