2 * Device Tree Include file for Marvell Armada XP family SoC
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
15 * Contains definitions specific to the Armada XP SoC that are not
16 * common to all Armada SoCs.
19 #include "armada-370-xp.dtsi"
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
30 compatible = "marvell,armadaxp-mbus", "simple-bus";
33 compatible = "marvell,bootrom";
34 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
39 compatible = "marvell,armada-xp-sdram-controller";
44 compatible = "marvell,aurora-system-cache";
45 reg = <0x08000 0x1000>;
46 cache-id-part = <0x100>;
52 pinctrl-0 = <&spi0_pins>;
53 pinctrl-names = "default";
57 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
58 reg = <0x11000 0x100>;
62 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
63 reg = <0x11100 0x100>;
67 compatible = "snps,dw-apb-uart";
68 pinctrl-0 = <&uart2_pins>;
69 pinctrl-names = "default";
70 reg = <0x12200 0x100>;
74 clocks = <&coreclk 0>;
79 compatible = "snps,dw-apb-uart";
80 pinctrl-0 = <&uart3_pins>;
81 pinctrl-names = "default";
82 reg = <0x12300 0x100>;
86 clocks = <&coreclk 0>;
90 system-controller@18200 {
91 compatible = "marvell,armada-370-xp-system-controller";
92 reg = <0x18200 0x500>;
95 gateclk: clock-gating-control@18220 {
96 compatible = "marvell,armada-xp-gating-clock";
98 clocks = <&coreclk 0>;
102 coreclk: mvebu-sar@18230 {
103 compatible = "marvell,armada-xp-core-clock";
104 reg = <0x18230 0x08>;
109 compatible = "marvell,armadaxp-thermal";
115 cpuclk: clock-complex@18700 {
117 compatible = "marvell,armada-xp-cpu-clock";
118 reg = <0x18700 0xA0>, <0x1c054 0x10>;
119 clocks = <&coreclk 1>;
122 interrupt-controller@20000 {
123 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
127 compatible = "marvell,armada-xp-timer";
128 clocks = <&coreclk 2>, <&refclk>;
129 clock-names = "nbclk", "fixed";
133 compatible = "marvell,armada-xp-wdt";
134 clocks = <&coreclk 2>, <&refclk>;
135 clock-names = "nbclk", "fixed";
139 compatible = "marvell,armada-370-cpu-reset";
140 reg = <0x20800 0x20>;
143 eth2: ethernet@30000 {
144 compatible = "marvell,armada-370-neta";
145 reg = <0x30000 0x4000>;
147 clocks = <&gateclk 2>;
152 clocks = <&gateclk 18>;
156 clocks = <&gateclk 19>;
160 compatible = "marvell,orion-ehci";
161 reg = <0x52000 0x500>;
163 clocks = <&gateclk 20>;
168 compatible = "marvell,orion-xor";
171 clocks = <&gateclk 22>;
188 compatible = "marvell,orion-xor";
191 clocks = <&gateclk 28>;
210 /* 25 MHz reference crystal */
212 compatible = "fixed-clock";
214 clock-frequency = <25000000>;
220 ge0_gmii_pins: ge0-gmii-pins {
222 "mpp0", "mpp1", "mpp2", "mpp3",
223 "mpp4", "mpp5", "mpp6", "mpp7",
224 "mpp8", "mpp9", "mpp10", "mpp11",
225 "mpp12", "mpp13", "mpp14", "mpp15",
226 "mpp16", "mpp17", "mpp18", "mpp19",
227 "mpp20", "mpp21", "mpp22", "mpp23";
228 marvell,function = "ge0";
231 ge0_rgmii_pins: ge0-rgmii-pins {
233 "mpp0", "mpp1", "mpp2", "mpp3",
234 "mpp4", "mpp5", "mpp6", "mpp7",
235 "mpp8", "mpp9", "mpp10", "mpp11";
236 marvell,function = "ge0";
239 ge1_rgmii_pins: ge1-rgmii-pins {
241 "mpp12", "mpp13", "mpp14", "mpp15",
242 "mpp16", "mpp17", "mpp18", "mpp19",
243 "mpp20", "mpp21", "mpp22", "mpp23";
244 marvell,function = "ge1";
247 sdio_pins: sdio-pins {
248 marvell,pins = "mpp30", "mpp31", "mpp32",
249 "mpp33", "mpp34", "mpp35";
250 marvell,function = "sd0";
253 spi0_pins: spi0-pins {
254 marvell,pins = "mpp36", "mpp37",
256 marvell,function = "spi";
259 uart2_pins: uart2-pins {
260 marvell,pins = "mpp42", "mpp43";
261 marvell,function = "uart2";
264 uart3_pins: uart3-pins {
265 marvell,pins = "mpp44", "mpp45";
266 marvell,function = "uart3";