2 * Device Tree Include file for Marvell Armada XP family SoC
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
15 * Contains definitions specific to the Armada XP SoC that are not
16 * common to all Armada SoCs.
19 /include/ "armada-370-xp.dtsi"
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
32 compatible = "marvell,aurora-system-cache";
33 reg = <0x08000 0x1000>;
34 cache-id-part = <0x100>;
38 interrupt-controller@20000 {
39 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
42 armada-370-xp-pmsu@22000 {
43 compatible = "marvell,armada-370-xp-pmsu";
44 reg = <0x22100 0x430>, <0x20800 0x20>;
48 compatible = "snps,dw-apb-uart";
49 reg = <0x12200 0x100>;
56 compatible = "snps,dw-apb-uart";
57 reg = <0x12300 0x100>;
68 coreclk: mvebu-sar@18230 {
69 compatible = "marvell,armada-xp-core-clock";
74 cpuclk: clock-complex@18700 {
76 compatible = "marvell,armada-xp-cpu-clock";
78 clocks = <&coreclk 1>;
81 gateclk: clock-gating-control@18220 {
82 compatible = "marvell,armada-xp-gating-clock";
84 clocks = <&coreclk 0>;
88 system-controller@18200 {
89 compatible = "marvell,armada-370-xp-system-controller";
90 reg = <0x18200 0x500>;
93 eth2: ethernet@30000 {
94 compatible = "marvell,armada-370-neta";
95 reg = <0x30000 0x4000>;
97 clocks = <&gateclk 2>;
102 compatible = "marvell,orion-xor";
105 clocks = <&gateclk 22>;
122 compatible = "marvell,orion-xor";
125 clocks = <&gateclk 28>;
142 clocks = <&gateclk 18>;
146 clocks = <&gateclk 19>;
150 compatible = "marvell,orion-ehci";
151 reg = <0x52000 0x500>;
153 clocks = <&gateclk 20>;
158 compatible = "marvell,armadaxp-thermal";