2 * Device Tree Include file for Marvell Armada XP family SoC
4 * Copyright (C) 2012 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
12 * Contains definitions specific to the Armada XP MV78260 SoC that are not
13 * common to all Armada XP SoCs.
16 #include "armada-xp.dtsi"
19 model = "Marvell Armada XP MV78260 SoC";
20 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
34 compatible = "marvell,sheeva-v7";
41 compatible = "marvell,sheeva-v7";
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
50 * configured as x4 or quad x1 lanes. One unit is
54 compatible = "marvell,armada-xp-pcie";
61 bus-range = <0x00 0xff>;
64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
65 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
66 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
67 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
68 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
69 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
70 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
71 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
72 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
73 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
74 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
75 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
76 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
77 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
78 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
79 0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
80 0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
81 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
82 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
86 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
87 reg = <0x0800 0 0 0 0>;
90 #interrupt-cells = <1>;
91 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
92 0x81000000 0 0 0x81000000 0x1 0 1 0>;
93 interrupt-map-mask = <0 0 0 0>;
94 interrupt-map = <0 0 0 0 &mpic 58>;
95 marvell,pcie-port = <0>;
96 marvell,pcie-lane = <0>;
97 clocks = <&gateclk 5>;
103 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
104 reg = <0x1000 0 0 0 0>;
105 #address-cells = <3>;
107 #interrupt-cells = <1>;
108 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
109 0x81000000 0 0 0x81000000 0x2 0 1 0>;
110 interrupt-map-mask = <0 0 0 0>;
111 interrupt-map = <0 0 0 0 &mpic 59>;
112 marvell,pcie-port = <0>;
113 marvell,pcie-lane = <1>;
114 clocks = <&gateclk 6>;
120 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
121 reg = <0x1800 0 0 0 0>;
122 #address-cells = <3>;
124 #interrupt-cells = <1>;
125 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
126 0x81000000 0 0 0x81000000 0x3 0 1 0>;
127 interrupt-map-mask = <0 0 0 0>;
128 interrupt-map = <0 0 0 0 &mpic 60>;
129 marvell,pcie-port = <0>;
130 marvell,pcie-lane = <2>;
131 clocks = <&gateclk 7>;
137 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
138 reg = <0x2000 0 0 0 0>;
139 #address-cells = <3>;
141 #interrupt-cells = <1>;
142 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
143 0x81000000 0 0 0x81000000 0x4 0 1 0>;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &mpic 61>;
146 marvell,pcie-port = <0>;
147 marvell,pcie-lane = <3>;
148 clocks = <&gateclk 8>;
154 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
155 reg = <0x4800 0 0 0 0>;
156 #address-cells = <3>;
158 #interrupt-cells = <1>;
159 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
160 0x81000000 0 0 0x81000000 0x9 0 1 0>;
161 interrupt-map-mask = <0 0 0 0>;
162 interrupt-map = <0 0 0 0 &mpic 99>;
163 marvell,pcie-port = <2>;
164 marvell,pcie-lane = <0>;
165 clocks = <&gateclk 26>;
171 assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
172 reg = <0x5000 0 0 0 0>;
173 #address-cells = <3>;
175 #interrupt-cells = <1>;
176 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
177 0x81000000 0 0 0x81000000 0xa 0 1 0>;
178 interrupt-map-mask = <0 0 0 0>;
179 interrupt-map = <0 0 0 0 &mpic 103>;
180 marvell,pcie-port = <3>;
181 marvell,pcie-lane = <0>;
182 clocks = <&gateclk 27>;
189 compatible = "marvell,mv78260-pinctrl";
190 reg = <0x18000 0x38>;
192 sdio_pins: sdio-pins {
193 marvell,pins = "mpp30", "mpp31", "mpp32",
194 "mpp33", "mpp34", "mpp35";
195 marvell,function = "sd0";
200 compatible = "marvell,orion-gpio";
201 reg = <0x18100 0x40>;
205 interrupt-controller;
206 #interrupt-cells = <2>;
207 interrupts = <82>, <83>, <84>, <85>;
211 compatible = "marvell,orion-gpio";
212 reg = <0x18140 0x40>;
216 interrupt-controller;
217 #interrupt-cells = <2>;
218 interrupts = <87>, <88>, <89>, <90>;
222 compatible = "marvell,orion-gpio";
223 reg = <0x18180 0x40>;
227 interrupt-controller;
228 #interrupt-cells = <2>;
233 compatible = "marvell,armada-370-neta";
234 reg = <0x34000 0x4000>;
236 clocks = <&gateclk 1>;