2 * Device Tree Include file for Marvell Armada XP family SoC
4 * Copyright (C) 2012 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
12 * Contains definitions specific to the Armada XP MV78230 SoC that are not
13 * common to all Armada XP SoCs.
16 /include/ "armada-xp.dtsi"
19 model = "Marvell Armada XP MV78230 SoC";
20 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
33 compatible = "marvell,sheeva-v7";
40 compatible = "marvell,sheeva-v7";
48 compatible = "marvell,mv78230-pinctrl";
49 reg = <0xd0018000 0x38>;
51 sdio_pins: sdio-pins {
52 marvell,pins = "mpp30", "mpp31", "mpp32",
53 "mpp33", "mpp34", "mpp35";
54 marvell,function = "sd0";
58 gpio0: gpio@d0018100 {
59 compatible = "marvell,orion-gpio";
60 reg = <0xd0018100 0x40>;
65 #interrupts-cells = <2>;
66 interrupts = <82>, <83>, <84>, <85>;
69 gpio1: gpio@d0018140 {
70 compatible = "marvell,orion-gpio";
71 reg = <0xd0018140 0x40>;
76 #interrupts-cells = <2>;
77 interrupts = <87>, <88>, <89>;
81 * MV78230 has 2 PCIe units Gen2.0: One unit can be
82 * configured as x4 or quad x1 lanes. One unit is
86 compatible = "marvell,armada-xp-pcie";
93 bus-range = <0x00 0xff>;
95 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
96 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
97 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
98 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
99 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
100 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
101 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
105 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
106 reg = <0x0800 0 0 0 0>;
107 #address-cells = <3>;
109 #interrupt-cells = <1>;
111 interrupt-map-mask = <0 0 0 0>;
112 interrupt-map = <0 0 0 0 &mpic 58>;
113 marvell,pcie-port = <0>;
114 marvell,pcie-lane = <0>;
115 clocks = <&gateclk 5>;
121 assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>;
122 reg = <0x1000 0 0 0 0>;
123 #address-cells = <3>;
125 #interrupt-cells = <1>;
127 interrupt-map-mask = <0 0 0 0>;
128 interrupt-map = <0 0 0 0 &mpic 59>;
129 marvell,pcie-port = <0>;
130 marvell,pcie-lane = <1>;
131 clocks = <&gateclk 6>;
137 assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>;
138 reg = <0x1800 0 0 0 0>;
139 #address-cells = <3>;
141 #interrupt-cells = <1>;
143 interrupt-map-mask = <0 0 0 0>;
144 interrupt-map = <0 0 0 0 &mpic 60>;
145 marvell,pcie-port = <0>;
146 marvell,pcie-lane = <2>;
147 clocks = <&gateclk 7>;
153 assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>;
154 reg = <0x2000 0 0 0 0>;
155 #address-cells = <3>;
157 #interrupt-cells = <1>;
159 interrupt-map-mask = <0 0 0 0>;
160 interrupt-map = <0 0 0 0 &mpic 61>;
161 marvell,pcie-port = <0>;
162 marvell,pcie-lane = <3>;
163 clocks = <&gateclk 8>;
169 assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>;
170 reg = <0x4800 0 0 0 0>;
171 #address-cells = <3>;
173 #interrupt-cells = <1>;
175 interrupt-map-mask = <0 0 0 0>;
176 interrupt-map = <0 0 0 0 &mpic 99>;
177 marvell,pcie-port = <2>;
178 marvell,pcie-lane = <0>;
179 clocks = <&gateclk 26>;