2 * Device Tree file for Marvell Armada XP development board
5 * Copyright (C) 2013-2014 Marvell
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
15 * Note: this Device Tree assumes that the bootloader has remapped the
16 * internal registers to 0xf1000000 (instead of the default
17 * 0xd0000000). The 0xf1000000 is the default used by the recent,
18 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
19 * boards were delivered with an older version of the bootloader that
20 * left internal registers mapped at 0xd0000000. If you are in this
21 * situation, you should either update your bootloader (preferred
22 * solution) or the below Device Tree should be adjusted.
26 #include <dt-bindings/gpio/gpio.h>
27 #include "armada-xp-mv78460.dtsi"
30 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
31 compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
34 bootargs = "console=ttyS0,115200 earlyprintk";
38 device_type = "memory";
40 * 8 GB of plug-in RAM modules by default.The amount
41 * of memory available can be changed by the
42 * bootloader according the size of the module
43 * actually plugged. However, memory between
44 * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
45 * the address range used for I/O (internal registers,
48 reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
49 <0x00000001 0x00000000 0x00000001 0x00000000>;
54 ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
55 <&gpio0 17 GPIO_ACTIVE_LOW>,
56 <&gpio0 18 GPIO_ACTIVE_LOW>;
61 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
62 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
63 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
68 /* Device Bus parameters are required */
71 devbus,bus-width = <16>;
72 devbus,turn-off-ps = <60000>;
73 devbus,badr-skew-ps = <0>;
74 devbus,acc-first-ps = <124000>;
75 devbus,acc-next-ps = <248000>;
76 devbus,rd-setup-ps = <0>;
77 devbus,rd-hold-ps = <0>;
79 /* Write parameters */
80 devbus,sync-enable = <0>;
81 devbus,wr-high-ps = <60000>;
82 devbus,wr-low-ps = <60000>;
83 devbus,ale-wr-ps = <60000>;
87 compatible = "cfi-flash";
97 * The 3 slots are physically present as
98 * standard PCIe slots on the board.
128 pinctrl-0 = <&pic_pins>;
129 pinctrl-names = "default";
130 pic_pins: pic-pins-0 {
131 marvell,pins = "mpp16", "mpp17",
133 marvell,function = "gpio";
142 phy0: ethernet-phy@0 {
146 phy1: ethernet-phy@1 {
150 phy2: ethernet-phy@2 {
154 phy3: ethernet-phy@3 {
180 /* Front-side USB slot */
185 /* Back-side USB slot */
194 #address-cells = <1>;
196 compatible = "n25q128a13";
197 reg = <0>; /* Chip select 0 */
198 spi-max-frequency = <108000000>;
205 marvell,nand-keep-config;
206 marvell,nand-enable-arbiter;