arch/arm/boot/dts/armada-xp-gp.dts

   1 /*
   2  * Device Tree file for Marvell Armada XP development board
   3  * (DB-MV784MP-GP)
   4  *
   5  * Copyright (C) 2013 Marvell
   6  *
   7  * Lior Amsalem <alior@marvell.com>
   8  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 /dts-v1/;
  17 /include/ "armada-xp-mv78460.dtsi"
  18
  19 / {
  20         model = "Marvell Armada XP Development Board DB-MV784MP-GP";
  21         compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
  22
  23         chosen {
  24                 bootargs = "console=ttyS0,115200 earlyprintk";
  25         };
  26
  27         memory {
  28                 device_type = "memory";
  29                 /*
  30                  * 8 GB of plug-in RAM modules by default.The amount
  31                  * of memory available can be changed by the
  32                  * bootloader according the size of the module
  33                  * actually plugged. Only 7GB are usable because
  34                  * addresses from 0xC0000000 to 0xffffffff are used by
  35                  * the internal registers of the SoC.
  36                  */
  37                 reg = <0x00000000 0x00000000 0x00000000 0xC0000000>,
  38                       <0x00000001 0x00000000 0x00000001 0x00000000>;
  39         };
  40
  41         soc {
  42                 ranges = <0          0 0xd0000000 0x100000
  43                           0xf0000000 0 0xf0000000 0x1000000>;
  44
  45                 internal-regs {
  46                         serial@12000 {
  47                                 clock-frequency = <250000000>;
  48                                 status = "okay";
  49                         };
  50                         serial@12100 {
  51                                 clock-frequency = <250000000>;
  52                                 status = "okay";
  53                         };
  54                         serial@12200 {
  55                                 clock-frequency = <250000000>;
  56                                 status = "okay";
  57                         };
  58                         serial@12300 {
  59                                 clock-frequency = <250000000>;
  60                                 status = "okay";
  61                         };
  62
  63                         sata@a0000 {
  64                                 nr-ports = <2>;
  65                                 status = "okay";
  66                         };
  67
  68                         mdio {
  69                                 phy0: ethernet-phy@0 {
  70                                         reg = <16>;
  71                                 };
  72
  73                                 phy1: ethernet-phy@1 {
  74                                         reg = <17>;
  75                                 };
  76
  77                                 phy2: ethernet-phy@2 {
  78                                         reg = <18>;
  79                                 };
  80
  81                                 phy3: ethernet-phy@3 {
  82                                         reg = <19>;
  83                                 };
  84                         };
  85
  86                         ethernet@70000 {
  87                                 status = "okay";
  88                                 phy = <&phy0>;
  89                                 phy-mode = "rgmii-id";
  90                         };
  91                         ethernet@74000 {
  92                                 status = "okay";
  93                                 phy = <&phy1>;
  94                                 phy-mode = "rgmii-id";
  95                         };
  96                         ethernet@30000 {
  97                                 status = "okay";
  98                                 phy = <&phy2>;
  99                                 phy-mode = "rgmii-id";
 100                         };
 101                         ethernet@34000 {
 102                                 status = "okay";
 103                                 phy = <&phy3>;
 104                                 phy-mode = "rgmii-id";
 105                         };
 106
 107                         spi0: spi@10600 {
 108                                 status = "okay";
 109
 110                                 spi-flash@0 {
 111                                         #address-cells = <1>;
 112                                         #size-cells = <1>;
 113                                         compatible = "n25q128a13";
 114                                         reg = <0>; /* Chip select 0 */
 115                                         spi-max-frequency = <108000000>;
 116                                 };
 117                         };
 118
 119                         devbus-bootcs@10400 {
 120                                 status = "okay";
 121                                 ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
 122
 123                                 /* Device Bus parameters are required */
 124
 125                                 /* Read parameters */
 126                                 devbus,bus-width    = <8>;
 127                                 devbus,turn-off-ps  = <60000>;
 128                                 devbus,badr-skew-ps = <0>;
 129                                 devbus,acc-first-ps = <124000>;
 130                                 devbus,acc-next-ps  = <248000>;
 131                                 devbus,rd-setup-ps  = <0>;
 132                                 devbus,rd-hold-ps   = <0>;
 133
 134                                 /* Write parameters */
 135                                 devbus,sync-enable = <0>;
 136                                 devbus,wr-high-ps  = <60000>;
 137                                 devbus,wr-low-ps   = <60000>;
 138                                 devbus,ale-wr-ps   = <60000>;
 139
 140                                 /* NOR 16 MiB */
 141                                 nor@0 {
 142                                         compatible = "cfi-flash";
 143                                         reg = <0 0x1000000>;
 144                                         bank-width = <2>;
 145                                 };
 146                         };
 147
 148                         pcie-controller {
 149                                 status = "okay";
 150
 151                                 /*
 152                                  * The 3 slots are physically present as
 153                                  * standard PCIe slots on the board.
 154                                  */
 155                                 pcie@1,0 {
 156                                         /* Port 0, Lane 0 */
 157                                         status = "okay";
 158                                 };
 159                                 pcie@9,0 {
 160                                         /* Port 2, Lane 0 */
 161                                         status = "okay";
 162                                 };
 163                                 pcie@10,0 {
 164                                         /* Port 3, Lane 0 */
 165                                         status = "okay";
 166                                 };
 167                         };
 168                 };
 169         };
 170 };