2 * Device Tree Include file for Marvell Armada 38x family of SoCs.
4 * Copyright (C) 2014 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
15 #include "skeleton.dtsi"
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
19 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
22 model = "Marvell Armada 38x family SoC";
23 compatible = "marvell,armada38x";
34 compatible = "marvell,armada380-mbus", "marvell,armada370-mbus",
38 controller = <&mbusc>;
39 interrupt-parent = <&gic>;
40 pcie-mem-aperture = <0xe0000000 0x8000000>;
41 pcie-io-aperture = <0xe8000000 0x100000>;
44 compatible = "marvell,bootrom";
45 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
49 compatible = "marvell,mvebu-devbus";
50 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
51 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
54 clocks = <&coreclk 0>;
59 compatible = "marvell,mvebu-devbus";
60 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
61 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
64 clocks = <&coreclk 0>;
69 compatible = "marvell,mvebu-devbus";
70 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
71 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
74 clocks = <&coreclk 0>;
79 compatible = "marvell,mvebu-devbus";
80 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
81 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
84 clocks = <&coreclk 0>;
89 compatible = "marvell,mvebu-devbus";
90 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
91 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
94 clocks = <&coreclk 0>;
99 compatible = "simple-bus";
100 #address-cells = <1>;
102 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
104 L2: cache-controller@8000 {
105 compatible = "arm,pl310-cache";
106 reg = <0x8000 0x1000>;
112 compatible = "arm,cortex-a9-twd-timer";
114 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
115 clocks = <&coreclk 2>;
118 gic: interrupt-controller@d000 {
119 compatible = "arm,cortex-a9-gic";
120 #interrupt-cells = <3>;
122 interrupt-controller;
123 reg = <0xd000 0x1000>,
128 compatible = "marvell,orion-spi";
129 reg = <0x10600 0x50>;
130 #address-cells = <1>;
133 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&coreclk 0>;
139 compatible = "marvell,orion-spi";
140 reg = <0x10680 0x50>;
141 #address-cells = <1>;
144 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&coreclk 0>;
150 compatible = "marvell,mv64xxx-i2c";
151 reg = <0x11000 0x20>;
152 #address-cells = <1>;
154 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&coreclk 0>;
161 compatible = "marvell,mv64xxx-i2c";
162 reg = <0x11100 0x20>;
163 #address-cells = <1>;
165 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&coreclk 0>;
172 compatible = "snps,dw-apb-uart";
173 reg = <0x12000 0x100>;
175 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
181 compatible = "snps,dw-apb-uart";
182 reg = <0x12100 0x100>;
184 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
190 compatible = "marvell,mv88f6820-pinctrl";
191 reg = <0x18000 0x20>;
195 compatible = "marvell,orion-gpio";
196 reg = <0x18100 0x40>;
200 interrupt-controller;
201 #interrupt-cells = <2>;
202 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
209 compatible = "marvell,orion-gpio";
210 reg = <0x18140 0x40>;
214 interrupt-controller;
215 #interrupt-cells = <2>;
216 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
222 system-controller@18200 {
223 compatible = "marvell,armada-380-system-controller",
224 "marvell,armada-370-xp-system-controller";
225 reg = <0x18200 0x100>;
228 gateclk: clock-gating-control@18220 {
229 compatible = "marvell,armada-380-gating-clock";
231 clocks = <&coreclk 0>;
235 coreclk: mvebu-sar@18600 {
236 compatible = "marvell,armada-380-core-clock";
237 reg = <0x18600 0x04>;
241 mbusc: mbus-controller@20000 {
242 compatible = "marvell,mbus-controller";
243 reg = <0x20000 0x100>, <0x20180 0x20>;
246 mpic: interrupt-controller@20000 {
247 compatible = "marvell,mpic";
248 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
249 #interrupt-cells = <1>;
251 interrupt-controller;
253 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
257 compatible = "marvell,armada-380-timer",
258 "marvell,armada-xp-timer";
259 reg = <0x20300 0x30>, <0x21040 0x30>;
260 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
261 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
262 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
263 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
266 clocks = <&coreclk 2>, <&refclk>;
267 clock-names = "nbclk", "fixed";
270 eth1: ethernet@30000 {
271 compatible = "marvell,armada-370-neta";
272 reg = <0x30000 0x4000>;
273 interrupts-extended = <&mpic 10>;
274 clocks = <&gateclk 3>;
278 eth2: ethernet@34000 {
279 compatible = "marvell,armada-370-neta";
280 reg = <0x34000 0x4000>;
281 interrupts-extended = <&mpic 12>;
282 clocks = <&gateclk 2>;
287 compatible = "marvell,orion-xor";
290 clocks = <&gateclk 22>;
294 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
299 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
307 compatible = "marvell,orion-xor";
310 clocks = <&gateclk 28>;
314 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
319 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
326 eth0: ethernet@70000 {
327 compatible = "marvell,armada-370-neta";
328 reg = <0x70000 0x4000>;
329 interrupts-extended = <&mpic 8>;
330 clocks = <&gateclk 4>;
335 #address-cells = <1>;
337 compatible = "marvell,orion-mdio";
339 clocks = <&gateclk 4>;
342 coredivclk: clock@e4250 {
343 compatible = "marvell,armada-380-corediv-clock";
347 clock-output-names = "nand";
351 compatible = "marvell,armada370-nand";
352 reg = <0xd0000 0x54>;
353 #address-cells = <1>;
355 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&coredivclk 0>;
363 /* 2 GHz fixed main PLL */
365 compatible = "fixed-clock";
367 clock-frequency = <2000000000>;
370 /* 25 MHz reference crystal */
372 compatible = "fixed-clock";
374 clock-frequency = <25000000>;