2 * Device Tree Include file for Marvell Armada 38x family of SoCs.
4 * Copyright (C) 2014 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
49 #include "skeleton.dtsi"
50 #include <dt-bindings/interrupt-controller/arm-gic.h>
51 #include <dt-bindings/interrupt-controller/irq.h>
53 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
56 model = "Marvell Armada 38x family SoC";
57 compatible = "marvell,armada380";
65 compatible = "marvell,armada380-mbus", "simple-bus";
68 controller = <&mbusc>;
69 interrupt-parent = <&gic>;
70 pcie-mem-aperture = <0xe0000000 0x8000000>;
71 pcie-io-aperture = <0xe8000000 0x100000>;
74 compatible = "marvell,bootrom";
75 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
79 compatible = "marvell,mvebu-devbus";
80 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
81 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
84 clocks = <&coreclk 0>;
89 compatible = "marvell,mvebu-devbus";
90 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
91 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
94 clocks = <&coreclk 0>;
99 compatible = "marvell,mvebu-devbus";
100 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
101 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
102 #address-cells = <1>;
104 clocks = <&coreclk 0>;
109 compatible = "marvell,mvebu-devbus";
110 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
111 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
112 #address-cells = <1>;
114 clocks = <&coreclk 0>;
119 compatible = "marvell,mvebu-devbus";
120 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
121 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
122 #address-cells = <1>;
124 clocks = <&coreclk 0>;
129 compatible = "simple-bus";
130 #address-cells = <1>;
132 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
134 L2: cache-controller@8000 {
135 compatible = "arm,pl310-cache";
136 reg = <0x8000 0x1000>;
142 compatible = "arm,cortex-a9-scu";
147 compatible = "arm,cortex-a9-twd-timer";
149 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
150 clocks = <&coreclk 2>;
153 gic: interrupt-controller@d000 {
154 compatible = "arm,cortex-a9-gic";
155 #interrupt-cells = <3>;
157 interrupt-controller;
158 reg = <0xd000 0x1000>,
163 compatible = "marvell,orion-spi";
164 reg = <0x10600 0x50>;
165 #address-cells = <1>;
168 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&coreclk 0>;
174 compatible = "marvell,orion-spi";
175 reg = <0x10680 0x50>;
176 #address-cells = <1>;
179 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&coreclk 0>;
185 compatible = "marvell,mv64xxx-i2c";
186 reg = <0x11000 0x20>;
187 #address-cells = <1>;
189 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&coreclk 0>;
196 compatible = "marvell,mv64xxx-i2c";
197 reg = <0x11100 0x20>;
198 #address-cells = <1>;
200 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&coreclk 0>;
206 uart0: serial@12000 {
207 compatible = "snps,dw-apb-uart";
208 reg = <0x12000 0x100>;
210 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&coreclk 0>;
216 uart1: serial@12100 {
217 compatible = "snps,dw-apb-uart";
218 reg = <0x12100 0x100>;
220 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&coreclk 0>;
226 pinctrl: pinctrl@18000 {
227 reg = <0x18000 0x20>;
229 ge0_rgmii_pins: ge-rgmii-pins-0 {
230 marvell,pins = "mpp6", "mpp7", "mpp8",
231 "mpp9", "mpp10", "mpp11",
232 "mpp12", "mpp13", "mpp14",
233 "mpp15", "mpp16", "mpp17";
234 marvell,function = "ge0";
237 ge1_rgmii_pins: ge-rgmii-pins-1 {
238 marvell,pins = "mpp21", "mpp27", "mpp28",
239 "mpp29", "mpp30", "mpp31",
240 "mpp32", "mpp37", "mpp38",
241 "mpp39", "mpp40", "mpp41";
242 marvell,function = "ge1";
245 i2c0_pins: i2c-pins-0 {
246 marvell,pins = "mpp2", "mpp3";
247 marvell,function = "i2c0";
250 mdio_pins: mdio-pins {
251 marvell,pins = "mpp4", "mpp5";
252 marvell,function = "ge";
255 ref_clk0_pins: ref-clk-pins-0 {
256 marvell,pins = "mpp45";
257 marvell,function = "ref";
260 ref_clk1_pins: ref-clk-pins-1 {
261 marvell,pins = "mpp46";
262 marvell,function = "ref";
265 spi0_pins: spi-pins-0 {
266 marvell,pins = "mpp22", "mpp23", "mpp24",
268 marvell,function = "spi0";
271 spi1_pins: spi-pins-1 {
272 marvell,pins = "mpp56", "mpp57", "mpp58",
274 marvell,function = "spi1";
277 uart0_pins: uart-pins-0 {
278 marvell,pins = "mpp0", "mpp1";
279 marvell,function = "ua0";
282 uart1_pins: uart-pins-1 {
283 marvell,pins = "mpp19", "mpp20";
284 marvell,function = "ua1";
287 sdhci_pins: sdhci-pins {
288 marvell,pins = "mpp48", "mpp49", "mpp50",
289 "mpp52", "mpp53", "mpp54",
290 "mpp55", "mpp57", "mpp58",
292 marvell,function = "sd0";
295 sata0_pins: sata-pins-0 {
296 marvell,pins = "mpp20";
297 marvell,function = "sata0";
300 sata1_pins: sata-pins-1 {
301 marvell,pins = "mpp19";
302 marvell,function = "sata1";
305 sata2_pins: sata-pins-2 {
306 marvell,pins = "mpp47";
307 marvell,function = "sata2";
310 sata3_pins: sata-pins-3 {
311 marvell,pins = "mpp44";
312 marvell,function = "sata3";
317 compatible = "marvell,orion-gpio";
318 reg = <0x18100 0x40>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
324 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
331 compatible = "marvell,orion-gpio";
332 reg = <0x18140 0x40>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
344 system-controller@18200 {
345 compatible = "marvell,armada-380-system-controller",
346 "marvell,armada-370-xp-system-controller";
347 reg = <0x18200 0x100>;
350 gateclk: clock-gating-control@18220 {
351 compatible = "marvell,armada-380-gating-clock";
353 clocks = <&coreclk 0>;
357 coreclk: mvebu-sar@18600 {
358 compatible = "marvell,armada-380-core-clock";
359 reg = <0x18600 0x04>;
363 mbusc: mbus-controller@20000 {
364 compatible = "marvell,mbus-controller";
365 reg = <0x20000 0x100>, <0x20180 0x20>;
368 mpic: interrupt-controller@20a00 {
369 compatible = "marvell,mpic";
370 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
371 #interrupt-cells = <1>;
373 interrupt-controller;
375 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
379 compatible = "marvell,armada-380-timer",
380 "marvell,armada-xp-timer";
381 reg = <0x20300 0x30>, <0x21040 0x30>;
382 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
383 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
384 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
385 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
388 clocks = <&coreclk 2>, <&refclk>;
389 clock-names = "nbclk", "fixed";
393 compatible = "marvell,armada-380-wdt";
394 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
395 clocks = <&coreclk 2>, <&refclk>;
396 clock-names = "nbclk", "fixed";
400 compatible = "marvell,armada-370-cpu-reset";
401 reg = <0x20800 0x10>;
404 mpcore-soc-ctrl@20d20 {
405 compatible = "marvell,armada-380-mpcore-soc-ctrl";
406 reg = <0x20d20 0x6c>;
409 coherency-fabric@21010 {
410 compatible = "marvell,armada-380-coherency-fabric";
411 reg = <0x21010 0x1c>;
415 compatible = "marvell,armada-380-pmsu";
416 reg = <0x22000 0x1000>;
419 eth1: ethernet@30000 {
420 compatible = "marvell,armada-370-neta";
421 reg = <0x30000 0x4000>;
422 interrupts-extended = <&mpic 10>;
423 clocks = <&gateclk 3>;
427 eth2: ethernet@34000 {
428 compatible = "marvell,armada-370-neta";
429 reg = <0x34000 0x4000>;
430 interrupts-extended = <&mpic 12>;
431 clocks = <&gateclk 2>;
436 compatible = "marvell,orion-ehci";
437 reg = <0x58000 0x500>;
438 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&gateclk 18>;
444 compatible = "marvell,orion-xor";
447 clocks = <&gateclk 22>;
451 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
456 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
464 compatible = "marvell,orion-xor";
467 clocks = <&gateclk 28>;
471 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
476 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
483 eth0: ethernet@70000 {
484 compatible = "marvell,armada-370-neta";
485 reg = <0x70000 0x4000>;
486 interrupts-extended = <&mpic 8>;
487 clocks = <&gateclk 4>;
492 #address-cells = <1>;
494 compatible = "marvell,orion-mdio";
496 clocks = <&gateclk 4>;
500 compatible = "marvell,armada-380-rtc";
501 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
502 reg-names = "rtc", "rtc-soc";
503 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
507 compatible = "marvell,armada-380-ahci";
508 reg = <0xa8000 0x2000>;
509 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&gateclk 15>;
515 compatible = "marvell,armada-380-ahci";
516 reg = <0xe0000 0x2000>;
517 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&gateclk 30>;
522 coredivclk: clock@e4250 {
523 compatible = "marvell,armada-380-corediv-clock";
527 clock-output-names = "nand";
531 compatible = "marvell,armada380-thermal";
532 reg = <0xe4078 0x4>, <0xe4074 0x4>;
537 compatible = "marvell,armada370-nand";
538 reg = <0xd0000 0x54>;
539 #address-cells = <1>;
541 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&coredivclk 0>;
547 compatible = "marvell,armada-380-sdhci";
548 reg-names = "sdhci", "mbus", "conf-sdio3";
549 reg = <0xd8000 0x1000>,
552 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&gateclk 17>;
554 mrvl,clk-delay-cycles = <0x1F>;
559 compatible = "marvell,armada-380-xhci";
560 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
561 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&gateclk 9>;
567 compatible = "marvell,armada-380-xhci";
568 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
569 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&gateclk 10>;
577 /* 2 GHz fixed main PLL */
579 compatible = "fixed-clock";
581 clock-frequency = <2000000000>;
584 /* 25 MHz reference crystal */
586 compatible = "fixed-clock";
588 clock-frequency = <25000000>;