arch/arm/boot/dts/armada-38x.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 38x family of SoCs.
   3  *
   4  * Copyright (C) 2014 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  */
  14
  15 #include "skeleton.dtsi"
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/interrupt-controller/irq.h>
  18
  19 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  20
  21 / {
  22         model = "Marvell Armada 38x family SoC";
  23         compatible = "marvell,armada380";
  24
  25         aliases {
  26                 gpio0 = &gpio0;
  27                 gpio1 = &gpio1;
  28                 ethernet0 = &eth0;
  29                 ethernet1 = &eth1;
  30                 ethernet2 = &eth2;
  31         };
  32
  33         soc {
  34                 compatible = "marvell,armada380-mbus", "marvell,armada370-mbus",
  35                              "simple-bus";
  36                 #address-cells = <2>;
  37                 #size-cells = <1>;
  38                 controller = <&mbusc>;
  39                 interrupt-parent = <&gic>;
  40                 pcie-mem-aperture = <0xe0000000 0x8000000>;
  41                 pcie-io-aperture  = <0xe8000000 0x100000>;
  42
  43                 bootrom {
  44                         compatible = "marvell,bootrom";
  45                         reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
  46                 };
  47
  48                 devbus-bootcs {
  49                         compatible = "marvell,mvebu-devbus";
  50                         reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
  51                         ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
  52                         #address-cells = <1>;
  53                         #size-cells = <1>;
  54                         clocks = <&coreclk 0>;
  55                         status = "disabled";
  56                 };
  57
  58                 devbus-cs0 {
  59                         compatible = "marvell,mvebu-devbus";
  60                         reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
  61                         ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
  62                         #address-cells = <1>;
  63                         #size-cells = <1>;
  64                         clocks = <&coreclk 0>;
  65                         status = "disabled";
  66                 };
  67
  68                 devbus-cs1 {
  69                         compatible = "marvell,mvebu-devbus";
  70                         reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
  71                         ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
  72                         #address-cells = <1>;
  73                         #size-cells = <1>;
  74                         clocks = <&coreclk 0>;
  75                         status = "disabled";
  76                 };
  77
  78                 devbus-cs2 {
  79                         compatible = "marvell,mvebu-devbus";
  80                         reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
  81                         ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
  82                         #address-cells = <1>;
  83                         #size-cells = <1>;
  84                         clocks = <&coreclk 0>;
  85                         status = "disabled";
  86                 };
  87
  88                 devbus-cs3 {
  89                         compatible = "marvell,mvebu-devbus";
  90                         reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
  91                         ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
  92                         #address-cells = <1>;
  93                         #size-cells = <1>;
  94                         clocks = <&coreclk 0>;
  95                         status = "disabled";
  96                 };
  97
  98                 internal-regs {
  99                         compatible = "simple-bus";
 100                         #address-cells = <1>;
 101                         #size-cells = <1>;
 102                         ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
 103
 104                         L2: cache-controller@8000 {
 105                                 compatible = "arm,pl310-cache";
 106                                 reg = <0x8000 0x1000>;
 107                                 cache-unified;
 108                                 cache-level = <2>;
 109                         };
 110
 111                         scu@c000 {
 112                                 compatible = "arm,cortex-a9-scu";
 113                                 reg = <0xc000 0x58>;
 114                         };
 115
 116                         timer@c600 {
 117                                 compatible = "arm,cortex-a9-twd-timer";
 118                                 reg = <0xc600 0x20>;
 119                                 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
 120                                 clocks = <&coreclk 2>;
 121                         };
 122
 123                         gic: interrupt-controller@d000 {
 124                                 compatible = "arm,cortex-a9-gic";
 125                                 #interrupt-cells = <3>;
 126                                 #size-cells = <0>;
 127                                 interrupt-controller;
 128                                 reg = <0xd000 0x1000>,
 129                                       <0xc100 0x100>;
 130                         };
 131
 132                         spi0: spi@10600 {
 133                                 compatible = "marvell,orion-spi";
 134                                 reg = <0x10600 0x50>;
 135                                 #address-cells = <1>;
 136                                 #size-cells = <0>;
 137                                 cell-index = <0>;
 138                                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 139                                 clocks = <&coreclk 0>;
 140                                 status = "disabled";
 141                         };
 142
 143                         spi1: spi@10680 {
 144                                 compatible = "marvell,orion-spi";
 145                                 reg = <0x10680 0x50>;
 146                                 #address-cells = <1>;
 147                                 #size-cells = <0>;
 148                                 cell-index = <1>;
 149                                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 150                                 clocks = <&coreclk 0>;
 151                                 status = "disabled";
 152                         };
 153
 154                         i2c0: i2c@11000 {
 155                                 compatible = "marvell,mv64xxx-i2c";
 156                                 reg = <0x11000 0x20>;
 157                                 #address-cells = <1>;
 158                                 #size-cells = <0>;
 159                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 160                                 timeout-ms = <1000>;
 161                                 clocks = <&coreclk 0>;
 162                                 status = "disabled";
 163                         };
 164
 165                         i2c1: i2c@11100 {
 166                                 compatible = "marvell,mv64xxx-i2c";
 167                                 reg = <0x11100 0x20>;
 168                                 #address-cells = <1>;
 169                                 #size-cells = <0>;
 170                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 171                                 timeout-ms = <1000>;
 172                                 clocks = <&coreclk 0>;
 173                                 status = "disabled";
 174                         };
 175
 176                         serial@12000 {
 177                                 compatible = "snps,dw-apb-uart";
 178                                 reg = <0x12000 0x100>;
 179                                 reg-shift = <2>;
 180                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 181                                 reg-io-width = <1>;
 182                                 clocks = <&coreclk 0>;
 183                                 status = "disabled";
 184                         };
 185
 186                         serial@12100 {
 187                                 compatible = "snps,dw-apb-uart";
 188                                 reg = <0x12100 0x100>;
 189                                 reg-shift = <2>;
 190                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 191                                 reg-io-width = <1>;
 192                                 clocks = <&coreclk 0>;
 193                                 status = "disabled";
 194                         };
 195
 196                         pinctrl@18000 {
 197                                 reg = <0x18000 0x20>;
 198
 199                                 ge0_rgmii_pins: ge-rgmii-pins-0 {
 200                                         marvell,pins = "mpp6", "mpp7", "mpp8",
 201                                                        "mpp9", "mpp10", "mpp11",
 202                                                        "mpp12", "mpp13", "mpp14",
 203                                                        "mpp15", "mpp16", "mpp17";
 204                                         marvell,function = "ge0";
 205                                 };
 206
 207                                 i2c0_pins: i2c-pins-0 {
 208                                         marvell,pins = "mpp2", "mpp3";
 209                                         marvell,function = "i2c0";
 210                                 };
 211
 212                                 mdio_pins: mdio-pins {
 213                                         marvell,pins = "mpp4", "mpp5";
 214                                         marvell,function = "ge";
 215                                 };
 216
 217                                 ref_clk0_pins: ref-clk-pins-0 {
 218                                         marvell,pins = "mpp45";
 219                                         marvell,function = "ref";
 220                                 };
 221
 222                                 spi1_pins: spi-pins-1 {
 223                                         marvell,pins = "mpp56", "mpp57", "mpp58",
 224                                                        "mpp59";
 225                                         marvell,function = "spi1";
 226                                 };
 227
 228                                 uart0_pins: uart-pins-0 {
 229                                         marvell,pins = "mpp0", "mpp1";
 230                                         marvell,function = "ua0";
 231                                 };
 232
 233                                 uart1_pins: uart-pins-1 {
 234                                         marvell,pins = "mpp19", "mpp20";
 235                                         marvell,function = "ua1";
 236                                 };
 237                         };
 238
 239                         gpio0: gpio@18100 {
 240                                 compatible = "marvell,orion-gpio";
 241                                 reg = <0x18100 0x40>;
 242                                 ngpios = <32>;
 243                                 gpio-controller;
 244                                 #gpio-cells = <2>;
 245                                 interrupt-controller;
 246                                 #interrupt-cells = <2>;
 247                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 248                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 249                                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 250                                              <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 251                         };
 252
 253                         gpio1: gpio@18140 {
 254                                 compatible = "marvell,orion-gpio";
 255                                 reg = <0x18140 0x40>;
 256                                 ngpios = <28>;
 257                                 gpio-controller;
 258                                 #gpio-cells = <2>;
 259                                 interrupt-controller;
 260                                 #interrupt-cells = <2>;
 261                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 262                                              <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 263                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 264                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 265                         };
 266
 267                         system-controller@18200 {
 268                                 compatible = "marvell,armada-380-system-controller",
 269                                              "marvell,armada-370-xp-system-controller";
 270                                 reg = <0x18200 0x100>;
 271                         };
 272
 273                         gateclk: clock-gating-control@18220 {
 274                                 compatible = "marvell,armada-380-gating-clock";
 275                                 reg = <0x18220 0x4>;
 276                                 clocks = <&coreclk 0>;
 277                                 #clock-cells = <1>;
 278                         };
 279
 280                         coreclk: mvebu-sar@18600 {
 281                                 compatible = "marvell,armada-380-core-clock";
 282                                 reg = <0x18600 0x04>;
 283                                 #clock-cells = <1>;
 284                         };
 285
 286                         mbusc: mbus-controller@20000 {
 287                                 compatible = "marvell,mbus-controller";
 288                                 reg = <0x20000 0x100>, <0x20180 0x20>;
 289                         };
 290
 291                         mpic: interrupt-controller@20000 {
 292                                 compatible = "marvell,mpic";
 293                                 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
 294                                 #interrupt-cells = <1>;
 295                                 #size-cells = <1>;
 296                                 interrupt-controller;
 297                                 msi-controller;
 298                                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
 299                         };
 300
 301                         timer@20300 {
 302                                 compatible = "marvell,armada-380-timer",
 303                                              "marvell,armada-xp-timer";
 304                                 reg = <0x20300 0x30>, <0x21040 0x30>;
 305                                 interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
 306                                                       <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
 307                                                       <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 308                                                       <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 309                                                       <&mpic 5>,
 310                                                       <&mpic 6>;
 311                                 clocks = <&coreclk 2>, <&refclk>;
 312                                 clock-names = "nbclk", "fixed";
 313                         };
 314
 315                         watchdog@20300 {
 316                                 compatible = "marvell,armada-380-wdt";
 317                                 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
 318                                 clocks = <&coreclk 2>, <&refclk>;
 319                                 clock-names = "nbclk", "fixed";
 320                         };
 321
 322                         cpurst@20800 {
 323                                 compatible = "marvell,armada-370-cpu-reset";
 324                                 reg = <0x20800 0x10>;
 325                         };
 326
 327                         mpcore-soc-ctrl@20d20 {
 328                                 compatible = "marvell,armada-380-mpcore-soc-ctrl";
 329                                 reg = <0x20d20 0x6c>;
 330                         };
 331
 332                         coherency-fabric@21010 {
 333                                 compatible = "marvell,armada-380-coherency-fabric";
 334                                 reg = <0x21010 0x1c>;
 335                         };
 336
 337                         pmsu@22000 {
 338                                 compatible = "marvell,armada-380-pmsu";
 339                                 reg = <0x22000 0x1000>;
 340                         };
 341
 342                         eth1: ethernet@30000 {
 343                                 compatible = "marvell,armada-370-neta";
 344                                 reg = <0x30000 0x4000>;
 345                                 interrupts-extended = <&mpic 10>;
 346                                 clocks = <&gateclk 3>;
 347                                 status = "disabled";
 348                         };
 349
 350                         eth2: ethernet@34000 {
 351                                 compatible = "marvell,armada-370-neta";
 352                                 reg = <0x34000 0x4000>;
 353                                 interrupts-extended = <&mpic 12>;
 354                                 clocks = <&gateclk 2>;
 355                                 status = "disabled";
 356                         };
 357
 358                         usb@50000 {
 359                                 compatible = "marvell,orion-ehci";
 360                                 reg = <0x58000 0x500>;
 361                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 362                                 clocks = <&gateclk 18>;
 363                                 status = "disabled";
 364                         };
 365
 366                         xor@60800 {
 367                                 compatible = "marvell,orion-xor";
 368                                 reg = <0x60800 0x100
 369                                        0x60a00 0x100>;
 370                                 clocks = <&gateclk 22>;
 371                                 status = "okay";
 372
 373                                 xor00 {
 374                                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 375                                         dmacap,memcpy;
 376                                         dmacap,xor;
 377                                 };
 378                                 xor01 {
 379                                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 380                                         dmacap,memcpy;
 381                                         dmacap,xor;
 382                                         dmacap,memset;
 383                                 };
 384                         };
 385
 386                         xor@60900 {
 387                                 compatible = "marvell,orion-xor";
 388                                 reg = <0x60900 0x100
 389                                        0x60b00 0x100>;
 390                                 clocks = <&gateclk 28>;
 391                                 status = "okay";
 392
 393                                 xor10 {
 394                                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 395                                         dmacap,memcpy;
 396                                         dmacap,xor;
 397                                 };
 398                                 xor11 {
 399                                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 400                                         dmacap,memcpy;
 401                                         dmacap,xor;
 402                                         dmacap,memset;
 403                                 };
 404                         };
 405
 406                         eth0: ethernet@70000 {
 407                                 compatible = "marvell,armada-370-neta";
 408                                 reg = <0x70000 0x4000>;
 409                                 interrupts-extended = <&mpic 8>;
 410                                 clocks = <&gateclk 4>;
 411                                 status = "disabled";
 412                         };
 413
 414                         mdio@72004 {
 415                                 #address-cells = <1>;
 416                                 #size-cells = <0>;
 417                                 compatible = "marvell,orion-mdio";
 418                                 reg = <0x72004 0x4>;
 419                                 clocks = <&gateclk 4>;
 420                         };
 421
 422                         sata@a8000 {
 423                                 compatible = "marvell,armada-380-ahci";
 424                                 reg = <0xa8000 0x2000>;
 425                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 426                                 clocks = <&gateclk 15>;
 427                                 status = "disabled";
 428                         };
 429
 430                         sata@e0000 {
 431                                 compatible = "marvell,armada-380-ahci";
 432                                 reg = <0xe0000 0x2000>;
 433                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 434                                 clocks = <&gateclk 30>;
 435                                 status = "disabled";
 436                         };
 437
 438                         coredivclk: clock@e4250 {
 439                                 compatible = "marvell,armada-380-corediv-clock";
 440                                 reg = <0xe4250 0xc>;
 441                                 #clock-cells = <1>;
 442                                 clocks = <&mainpll>;
 443                                 clock-output-names = "nand";
 444                         };
 445
 446                         thermal@e8078 {
 447                                 compatible = "marvell,armada380-thermal";
 448                                 reg = <0xe4078 0x4>, <0xe4074 0x4>;
 449                                 status = "okay";
 450                         };
 451
 452                         flash@d0000 {
 453                                 compatible = "marvell,armada370-nand";
 454                                 reg = <0xd0000 0x54>;
 455                                 #address-cells = <1>;
 456                                 #size-cells = <1>;
 457                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 458                                 clocks = <&coredivclk 0>;
 459                                 status = "disabled";
 460                         };
 461
 462                         sdhci@d8000 {
 463                                 compatible = "marvell,armada-380-sdhci";
 464                                 reg = <0xd8000 0x1000>, <0xdc000 0x100>;
 465                                 interrupts = <0 25 0x4>;
 466                                 clocks = <&gateclk 17>;
 467                                 mrvl,clk-delay-cycles = <0x1F>;
 468                                 status = "disabled";
 469                         };
 470
 471                         usb3@f0000 {
 472                                 compatible = "marvell,armada-380-xhci";
 473                                 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
 474                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 475                                 clocks = <&gateclk 9>;
 476                                 status = "disabled";
 477                         };
 478
 479                         usb3@f8000 {
 480                                 compatible = "marvell,armada-380-xhci";
 481                                 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
 482                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 483                                 clocks = <&gateclk 10>;
 484                                 status = "disabled";
 485                         };
 486                 };
 487         };
 488
 489         clocks {
 490                 /* 2 GHz fixed main PLL */
 491                 mainpll: mainpll {
 492                         compatible = "fixed-clock";
 493                         #clock-cells = <0>;
 494                         clock-frequency = <2000000000>;
 495                 };
 496
 497                 /* 25 MHz reference crystal */
 498                 refclk: oscillator {
 499                         compatible = "fixed-clock";
 500                         #clock-cells = <0>;
 501                         clock-frequency = <25000000>;
 502                 };
 503         };
 504 };