2 * Device Tree Include file for Marvell Armada 38x family of SoCs.
4 * Copyright (C) 2014 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
15 #include "skeleton.dtsi"
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
19 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
22 model = "Marvell Armada 38x family SoC";
23 compatible = "marvell,armada380";
34 compatible = "marvell,armada380-mbus", "marvell,armada370-mbus",
38 controller = <&mbusc>;
39 interrupt-parent = <&gic>;
40 pcie-mem-aperture = <0xe0000000 0x8000000>;
41 pcie-io-aperture = <0xe8000000 0x100000>;
44 compatible = "marvell,bootrom";
45 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
49 compatible = "marvell,mvebu-devbus";
50 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
51 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
54 clocks = <&coreclk 0>;
59 compatible = "marvell,mvebu-devbus";
60 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
61 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
64 clocks = <&coreclk 0>;
69 compatible = "marvell,mvebu-devbus";
70 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
71 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
74 clocks = <&coreclk 0>;
79 compatible = "marvell,mvebu-devbus";
80 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
81 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
84 clocks = <&coreclk 0>;
89 compatible = "marvell,mvebu-devbus";
90 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
91 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
94 clocks = <&coreclk 0>;
99 compatible = "simple-bus";
100 #address-cells = <1>;
102 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
104 L2: cache-controller@8000 {
105 compatible = "arm,pl310-cache";
106 reg = <0x8000 0x1000>;
112 compatible = "arm,cortex-a9-scu";
117 compatible = "arm,cortex-a9-twd-timer";
119 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
120 clocks = <&coreclk 2>;
123 gic: interrupt-controller@d000 {
124 compatible = "arm,cortex-a9-gic";
125 #interrupt-cells = <3>;
127 interrupt-controller;
128 reg = <0xd000 0x1000>,
133 compatible = "marvell,orion-spi";
134 reg = <0x10600 0x50>;
135 #address-cells = <1>;
138 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&coreclk 0>;
144 compatible = "marvell,orion-spi";
145 reg = <0x10680 0x50>;
146 #address-cells = <1>;
149 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&coreclk 0>;
155 compatible = "marvell,mv64xxx-i2c";
156 reg = <0x11000 0x20>;
157 #address-cells = <1>;
159 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&coreclk 0>;
166 compatible = "marvell,mv64xxx-i2c";
167 reg = <0x11100 0x20>;
168 #address-cells = <1>;
170 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&coreclk 0>;
177 compatible = "snps,dw-apb-uart";
178 reg = <0x12000 0x100>;
180 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&coreclk 0>;
187 compatible = "snps,dw-apb-uart";
188 reg = <0x12100 0x100>;
190 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&coreclk 0>;
197 reg = <0x18000 0x20>;
199 ge0_rgmii_pins: ge-rgmii-pins-0 {
200 marvell,pins = "mpp6", "mpp7", "mpp8",
201 "mpp9", "mpp10", "mpp11",
202 "mpp12", "mpp13", "mpp14",
203 "mpp15", "mpp16", "mpp17";
204 marvell,function = "ge0";
207 ge1_rgmii_pins: ge-rgmii-pins-1 {
208 marvell,pins = "mpp21", "mpp27", "mpp28",
209 "mpp29", "mpp30", "mpp31",
210 "mpp32", "mpp37", "mpp38",
211 "mpp39", "mpp40", "mpp41";
212 marvell,function = "ge1";
215 i2c0_pins: i2c-pins-0 {
216 marvell,pins = "mpp2", "mpp3";
217 marvell,function = "i2c0";
220 mdio_pins: mdio-pins {
221 marvell,pins = "mpp4", "mpp5";
222 marvell,function = "ge";
225 ref_clk0_pins: ref-clk-pins-0 {
226 marvell,pins = "mpp45";
227 marvell,function = "ref";
230 ref_clk1_pins: ref-clk-pins-1 {
231 marvell,pins = "mpp46";
232 marvell,function = "ref";
235 spi0_pins: spi-pins-0 {
236 marvell,pins = "mpp22", "mpp23", "mpp24",
238 marvell,function = "spi0";
241 spi1_pins: spi-pins-1 {
242 marvell,pins = "mpp56", "mpp57", "mpp58",
244 marvell,function = "spi1";
247 uart0_pins: uart-pins-0 {
248 marvell,pins = "mpp0", "mpp1";
249 marvell,function = "ua0";
252 uart1_pins: uart-pins-1 {
253 marvell,pins = "mpp19", "mpp20";
254 marvell,function = "ua1";
257 sdhci_pins: sdhci-pins {
258 marvell,pins = "mpp48", "mpp49", "mpp50",
259 "mpp52", "mpp53", "mpp54",
260 "mpp55", "mpp57", "mpp58",
262 marvell,function = "sd0";
265 sata0_pins: sata-pins-0 {
266 marvell,pins = "mpp20";
267 marvell,function = "sata0";
270 sata1_pins: sata-pins-1 {
271 marvell,pins = "mpp19";
272 marvell,function = "sata1";
275 sata2_pins: sata-pins-2 {
276 marvell,pins = "mpp47";
277 marvell,function = "sata2";
280 sata3_pins: sata-pins-3 {
281 marvell,pins = "mpp44";
282 marvell,function = "sata3";
287 compatible = "marvell,orion-gpio";
288 reg = <0x18100 0x40>;
292 interrupt-controller;
293 #interrupt-cells = <2>;
294 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
301 compatible = "marvell,orion-gpio";
302 reg = <0x18140 0x40>;
306 interrupt-controller;
307 #interrupt-cells = <2>;
308 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
314 system-controller@18200 {
315 compatible = "marvell,armada-380-system-controller",
316 "marvell,armada-370-xp-system-controller";
317 reg = <0x18200 0x100>;
320 gateclk: clock-gating-control@18220 {
321 compatible = "marvell,armada-380-gating-clock";
323 clocks = <&coreclk 0>;
327 coreclk: mvebu-sar@18600 {
328 compatible = "marvell,armada-380-core-clock";
329 reg = <0x18600 0x04>;
333 mbusc: mbus-controller@20000 {
334 compatible = "marvell,mbus-controller";
335 reg = <0x20000 0x100>, <0x20180 0x20>;
338 mpic: interrupt-controller@20000 {
339 compatible = "marvell,mpic";
340 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
341 #interrupt-cells = <1>;
343 interrupt-controller;
345 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
349 compatible = "marvell,armada-380-timer",
350 "marvell,armada-xp-timer";
351 reg = <0x20300 0x30>, <0x21040 0x30>;
352 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
353 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
354 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
355 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
358 clocks = <&coreclk 2>, <&refclk>;
359 clock-names = "nbclk", "fixed";
363 compatible = "marvell,armada-380-wdt";
364 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
365 clocks = <&coreclk 2>, <&refclk>;
366 clock-names = "nbclk", "fixed";
370 compatible = "marvell,armada-370-cpu-reset";
371 reg = <0x20800 0x10>;
374 mpcore-soc-ctrl@20d20 {
375 compatible = "marvell,armada-380-mpcore-soc-ctrl";
376 reg = <0x20d20 0x6c>;
379 coherency-fabric@21010 {
380 compatible = "marvell,armada-380-coherency-fabric";
381 reg = <0x21010 0x1c>;
385 compatible = "marvell,armada-380-pmsu";
386 reg = <0x22000 0x1000>;
389 eth1: ethernet@30000 {
390 compatible = "marvell,armada-370-neta";
391 reg = <0x30000 0x4000>;
392 interrupts-extended = <&mpic 10>;
393 clocks = <&gateclk 3>;
397 eth2: ethernet@34000 {
398 compatible = "marvell,armada-370-neta";
399 reg = <0x34000 0x4000>;
400 interrupts-extended = <&mpic 12>;
401 clocks = <&gateclk 2>;
406 compatible = "marvell,orion-ehci";
407 reg = <0x58000 0x500>;
408 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&gateclk 18>;
414 compatible = "marvell,orion-xor";
417 clocks = <&gateclk 22>;
421 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
426 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
434 compatible = "marvell,orion-xor";
437 clocks = <&gateclk 28>;
441 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
446 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
453 eth0: ethernet@70000 {
454 compatible = "marvell,armada-370-neta";
455 reg = <0x70000 0x4000>;
456 interrupts-extended = <&mpic 8>;
457 clocks = <&gateclk 4>;
462 #address-cells = <1>;
464 compatible = "marvell,orion-mdio";
466 clocks = <&gateclk 4>;
470 compatible = "marvell,armada-380-ahci";
471 reg = <0xa8000 0x2000>;
472 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&gateclk 15>;
478 compatible = "marvell,armada-380-ahci";
479 reg = <0xe0000 0x2000>;
480 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&gateclk 30>;
485 coredivclk: clock@e4250 {
486 compatible = "marvell,armada-380-corediv-clock";
490 clock-output-names = "nand";
494 compatible = "marvell,armada380-thermal";
495 reg = <0xe4078 0x4>, <0xe4074 0x4>;
500 compatible = "marvell,armada370-nand";
501 reg = <0xd0000 0x54>;
502 #address-cells = <1>;
504 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&coredivclk 0>;
510 compatible = "marvell,armada-380-sdhci";
511 reg = <0xd8000 0x1000>, <0xdc000 0x100>;
512 interrupts = <0 25 0x4>;
513 clocks = <&gateclk 17>;
514 mrvl,clk-delay-cycles = <0x1F>;
519 compatible = "marvell,armada-380-xhci";
520 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
521 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&gateclk 9>;
527 compatible = "marvell,armada-380-xhci";
528 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
529 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&gateclk 10>;
537 /* 2 GHz fixed main PLL */
539 compatible = "fixed-clock";
541 clock-frequency = <2000000000>;
544 /* 25 MHz reference crystal */
546 compatible = "fixed-clock";
548 clock-frequency = <25000000>;