2 * Device Tree Include file for Marvell Armada 375 family SoC
4 * Copyright (C) 2014 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
14 * a) This file is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of the
17 * License, or (at your option) any later version.
19 * This file is distributed in the hope that it will be useful
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "skeleton.dtsi"
49 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
51 #include <dt-bindings/phy/phy.h>
53 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
56 model = "Marvell Armada 375 family SoC";
57 compatible = "marvell,armada375";
68 /* 2 GHz fixed main PLL */
70 compatible = "fixed-clock";
72 clock-frequency = <2000000000>;
74 /* 25 MHz reference crystal */
76 compatible = "fixed-clock";
78 clock-frequency = <25000000>;
85 enable-method = "marvell,armada-375-smp";
89 compatible = "arm,cortex-a9";
94 compatible = "arm,cortex-a9";
100 compatible = "arm,cortex-a9-pmu";
101 interrupts-extended = <&mpic 3>;
105 compatible = "marvell,armada375-mbus", "simple-bus";
106 #address-cells = <2>;
108 controller = <&mbusc>;
109 interrupt-parent = <&gic>;
110 pcie-mem-aperture = <0xe0000000 0x8000000>;
111 pcie-io-aperture = <0xe8000000 0x100000>;
114 compatible = "marvell,bootrom";
115 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
119 compatible = "marvell,mvebu-devbus";
120 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
121 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
122 #address-cells = <1>;
124 clocks = <&coreclk 0>;
129 compatible = "marvell,mvebu-devbus";
130 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
131 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
132 #address-cells = <1>;
134 clocks = <&coreclk 0>;
139 compatible = "marvell,mvebu-devbus";
140 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
141 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
142 #address-cells = <1>;
144 clocks = <&coreclk 0>;
149 compatible = "marvell,mvebu-devbus";
150 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
151 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
152 #address-cells = <1>;
154 clocks = <&coreclk 0>;
159 compatible = "marvell,mvebu-devbus";
160 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
161 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
162 #address-cells = <1>;
164 clocks = <&coreclk 0>;
169 compatible = "simple-bus";
170 #address-cells = <1>;
172 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
174 L2: cache-controller@8000 {
175 compatible = "arm,pl310-cache";
176 reg = <0x8000 0x1000>;
182 compatible = "arm,cortex-a9-scu";
187 compatible = "arm,cortex-a9-twd-timer";
189 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
190 clocks = <&coreclk 2>;
193 gic: interrupt-controller@d000 {
194 compatible = "arm,cortex-a9-gic";
195 #interrupt-cells = <3>;
197 interrupt-controller;
198 reg = <0xd000 0x1000>,
203 #address-cells = <1>;
205 compatible = "marvell,orion-mdio";
207 clocks = <&gateclk 19>;
210 /* Network controller */
212 compatible = "marvell,armada-375-pp2";
213 reg = <0xf0000 0xa000>, /* Packet Processor regs */
214 <0xc0000 0x3060>, /* LMS regs */
215 <0xc4000 0x100>, /* eth0 regs */
216 <0xc5000 0x100>; /* eth1 regs */
217 clocks = <&gateclk 3>, <&gateclk 19>;
218 clock-names = "pp_clk", "gop_clk";
222 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
228 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
235 compatible = "marvell,orion-rtc";
236 reg = <0x10300 0x20>;
237 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
241 compatible = "marvell,orion-spi";
242 reg = <0x10600 0x50>;
243 #address-cells = <1>;
246 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&coreclk 0>;
252 compatible = "marvell,orion-spi";
253 reg = <0x10680 0x50>;
254 #address-cells = <1>;
257 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&coreclk 0>;
263 compatible = "marvell,mv64xxx-i2c";
264 reg = <0x11000 0x20>;
265 #address-cells = <1>;
267 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&coreclk 0>;
274 compatible = "marvell,mv64xxx-i2c";
275 reg = <0x11100 0x20>;
276 #address-cells = <1>;
278 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&coreclk 0>;
284 uart0: serial@12000 {
285 compatible = "snps,dw-apb-uart";
286 reg = <0x12000 0x100>;
288 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&coreclk 0>;
294 uart1: serial@12100 {
295 compatible = "snps,dw-apb-uart";
296 reg = <0x12100 0x100>;
298 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&coreclk 0>;
305 compatible = "marvell,mv88f6720-pinctrl";
306 reg = <0x18000 0x24>;
308 i2c0_pins: i2c0-pins {
309 marvell,pins = "mpp14", "mpp15";
310 marvell,function = "i2c0";
313 i2c1_pins: i2c1-pins {
314 marvell,pins = "mpp61", "mpp62";
315 marvell,function = "i2c1";
318 nand_pins: nand-pins {
319 marvell,pins = "mpp0", "mpp1", "mpp2",
320 "mpp3", "mpp4", "mpp5",
321 "mpp6", "mpp7", "mpp8",
322 "mpp9", "mpp10", "mpp11",
324 marvell,function = "nand";
327 sdio_pins: sdio-pins {
328 marvell,pins = "mpp24", "mpp25", "mpp26",
329 "mpp27", "mpp28", "mpp29";
330 marvell,function = "sd";
333 spi0_pins: spi0-pins {
334 marvell,pins = "mpp0", "mpp1", "mpp4",
335 "mpp5", "mpp8", "mpp9";
336 marvell,function = "spi0";
341 compatible = "marvell,orion-gpio";
342 reg = <0x18100 0x40>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
348 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
355 compatible = "marvell,orion-gpio";
356 reg = <0x18140 0x40>;
360 interrupt-controller;
361 #interrupt-cells = <2>;
362 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
365 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
369 compatible = "marvell,orion-gpio";
370 reg = <0x18180 0x40>;
374 interrupt-controller;
375 #interrupt-cells = <2>;
376 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
379 system-controller@18200 {
380 compatible = "marvell,armada-375-system-controller";
381 reg = <0x18200 0x100>;
384 gateclk: clock-gating-control@18220 {
385 compatible = "marvell,armada-375-gating-clock";
387 clocks = <&coreclk 0>;
391 usbcluster: usb-cluster@18400 {
392 compatible = "marvell,armada-375-usb-cluster";
397 mbusc: mbus-controller@20000 {
398 compatible = "marvell,mbus-controller";
399 reg = <0x20000 0x100>, <0x20180 0x20>;
402 mpic: interrupt-controller@20a00 {
403 compatible = "marvell,mpic";
404 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
405 #interrupt-cells = <1>;
407 interrupt-controller;
409 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
413 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
414 reg = <0x20300 0x30>, <0x21040 0x30>;
415 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
416 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
417 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
418 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
421 clocks = <&coreclk 0>, <&refclk>;
422 clock-names = "nbclk", "fixed";
426 compatible = "marvell,armada-375-wdt";
427 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
428 clocks = <&coreclk 0>, <&refclk>;
429 clock-names = "nbclk", "fixed";
433 compatible = "marvell,armada-370-cpu-reset";
434 reg = <0x20800 0x10>;
437 coherency-fabric@21010 {
438 compatible = "marvell,armada-375-coherency-fabric";
439 reg = <0x21010 0x1c>;
443 compatible = "marvell,orion-ehci";
444 reg = <0x50000 0x500>;
445 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&gateclk 18>;
447 phys = <&usbcluster PHY_TYPE_USB2>;
453 compatible = "marvell,orion-ehci";
454 reg = <0x54000 0x500>;
455 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&gateclk 26>;
461 compatible = "marvell,armada-375-xhci";
462 reg = <0x58000 0x20000>,<0x5b880 0x80>;
463 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&gateclk 16>;
465 phys = <&usbcluster PHY_TYPE_USB3>;
471 compatible = "marvell,orion-xor";
474 clocks = <&gateclk 22>;
478 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
483 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
491 compatible = "marvell,orion-xor";
494 clocks = <&gateclk 23>;
498 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
503 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
511 compatible = "marvell,orion-sata";
512 reg = <0xa0000 0x5000>;
513 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&gateclk 14>, <&gateclk 20>;
515 clock-names = "0", "1";
520 compatible = "marvell,armada370-nand";
521 reg = <0xd0000 0x54>;
522 #address-cells = <1>;
524 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&gateclk 11>;
530 compatible = "marvell,orion-sdio";
531 reg = <0xd4000 0x200>;
532 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&gateclk 17>;
542 compatible = "marvell,armada375-thermal";
543 reg = <0xe8078 0x4>, <0xe807c 0x8>;
547 coreclk: mvebu-sar@e8204 {
548 compatible = "marvell,armada-375-core-clock";
549 reg = <0xe8204 0x04>;
553 coredivclk: corediv-clock@e8250 {
554 compatible = "marvell,armada-375-corediv-clock";
558 clock-output-names = "nand";
563 compatible = "marvell,armada-370-pcie";
567 #address-cells = <3>;
570 msi-parent = <&mpic>;
571 bus-range = <0x00 0xff>;
574 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
575 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
576 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
577 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
578 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
579 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
583 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
584 reg = <0x0800 0 0 0 0>;
585 #address-cells = <3>;
587 #interrupt-cells = <1>;
588 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
589 0x81000000 0 0 0x81000000 0x1 0 1 0>;
590 interrupt-map-mask = <0 0 0 0>;
591 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
592 marvell,pcie-port = <0>;
593 marvell,pcie-lane = <0>;
594 clocks = <&gateclk 5>;
600 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
601 reg = <0x1000 0 0 0 0>;
602 #address-cells = <3>;
604 #interrupt-cells = <1>;
605 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
606 0x81000000 0 0 0x81000000 0x2 0 1 0>;
607 interrupt-map-mask = <0 0 0 0>;
608 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
609 marvell,pcie-port = <0>;
610 marvell,pcie-lane = <1>;
611 clocks = <&gateclk 6>;