2 * Device Tree Include file for Marvell Armada 375 family SoC
4 * Copyright (C) 2014 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include "skeleton.dtsi"
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/phy/phy.h>
19 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
22 model = "Marvell Armada 375 family SoC";
23 compatible = "marvell,armada375";
34 /* 2 GHz fixed main PLL */
36 compatible = "fixed-clock";
38 clock-frequency = <2000000000>;
40 /* 25 MHz reference crystal */
42 compatible = "fixed-clock";
44 clock-frequency = <25000000>;
51 enable-method = "marvell,armada-375-smp";
55 compatible = "arm,cortex-a9";
60 compatible = "arm,cortex-a9";
66 compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus";
69 controller = <&mbusc>;
70 interrupt-parent = <&gic>;
71 pcie-mem-aperture = <0xe0000000 0x8000000>;
72 pcie-io-aperture = <0xe8000000 0x100000>;
75 compatible = "marvell,bootrom";
76 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
80 compatible = "marvell,mvebu-devbus";
81 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
82 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
85 clocks = <&coreclk 0>;
90 compatible = "marvell,mvebu-devbus";
91 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
92 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
95 clocks = <&coreclk 0>;
100 compatible = "marvell,mvebu-devbus";
101 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
102 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
103 #address-cells = <1>;
105 clocks = <&coreclk 0>;
110 compatible = "marvell,mvebu-devbus";
111 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
112 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
113 #address-cells = <1>;
115 clocks = <&coreclk 0>;
120 compatible = "marvell,mvebu-devbus";
121 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
122 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
123 #address-cells = <1>;
125 clocks = <&coreclk 0>;
130 compatible = "simple-bus";
131 #address-cells = <1>;
133 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
135 L2: cache-controller@8000 {
136 compatible = "arm,pl310-cache";
137 reg = <0x8000 0x1000>;
143 compatible = "arm,cortex-a9-scu";
148 compatible = "arm,cortex-a9-twd-timer";
150 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
151 clocks = <&coreclk 2>;
154 gic: interrupt-controller@d000 {
155 compatible = "arm,cortex-a9-gic";
156 #interrupt-cells = <3>;
158 interrupt-controller;
159 reg = <0xd000 0x1000>,
164 #address-cells = <1>;
166 compatible = "marvell,orion-mdio";
168 clocks = <&gateclk 19>;
171 /* Network controller */
173 compatible = "marvell,armada-375-pp2";
174 reg = <0xf0000 0xa000>, /* Packet Processor regs */
175 <0xc0000 0x3060>, /* LMS regs */
176 <0xc4000 0x100>, /* eth0 regs */
177 <0xc5000 0x100>; /* eth1 regs */
178 clocks = <&gateclk 3>, <&gateclk 19>;
179 clock-names = "pp_clk", "gop_clk";
183 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
189 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
196 compatible = "marvell,orion-rtc";
197 reg = <0x10300 0x20>;
198 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
202 compatible = "marvell,orion-spi";
203 reg = <0x10600 0x50>;
204 #address-cells = <1>;
207 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&coreclk 0>;
213 compatible = "marvell,orion-spi";
214 reg = <0x10680 0x50>;
215 #address-cells = <1>;
218 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&coreclk 0>;
224 compatible = "marvell,mv64xxx-i2c";
225 reg = <0x11000 0x20>;
226 #address-cells = <1>;
228 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&coreclk 0>;
235 compatible = "marvell,mv64xxx-i2c";
236 reg = <0x11100 0x20>;
237 #address-cells = <1>;
239 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&coreclk 0>;
246 compatible = "snps,dw-apb-uart";
247 reg = <0x12000 0x100>;
249 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&coreclk 0>;
256 compatible = "snps,dw-apb-uart";
257 reg = <0x12100 0x100>;
259 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&coreclk 0>;
266 compatible = "marvell,mv88f6720-pinctrl";
267 reg = <0x18000 0x24>;
269 i2c0_pins: i2c0-pins {
270 marvell,pins = "mpp14", "mpp15";
271 marvell,function = "i2c0";
274 i2c1_pins: i2c1-pins {
275 marvell,pins = "mpp61", "mpp62";
276 marvell,function = "i2c1";
279 nand_pins: nand-pins {
280 marvell,pins = "mpp0", "mpp1", "mpp2",
281 "mpp3", "mpp4", "mpp5",
282 "mpp6", "mpp7", "mpp8",
283 "mpp9", "mpp10", "mpp11",
285 marvell,function = "nand";
288 sdio_pins: sdio-pins {
289 marvell,pins = "mpp24", "mpp25", "mpp26",
290 "mpp27", "mpp28", "mpp29";
291 marvell,function = "sd";
294 spi0_pins: spi0-pins {
295 marvell,pins = "mpp0", "mpp1", "mpp4",
296 "mpp5", "mpp8", "mpp9";
297 marvell,function = "spi0";
302 compatible = "marvell,orion-gpio";
303 reg = <0x18100 0x40>;
307 interrupt-controller;
308 #interrupt-cells = <2>;
309 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
316 compatible = "marvell,orion-gpio";
317 reg = <0x18140 0x40>;
321 interrupt-controller;
322 #interrupt-cells = <2>;
323 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
330 compatible = "marvell,orion-gpio";
331 reg = <0x18180 0x40>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
337 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
340 system-controller@18200 {
341 compatible = "marvell,armada-375-system-controller";
342 reg = <0x18200 0x100>;
345 gateclk: clock-gating-control@18220 {
346 compatible = "marvell,armada-375-gating-clock";
348 clocks = <&coreclk 0>;
352 usbcluster: usb-cluster@18400 {
353 compatible = "marvell,armada-375-usb-cluster";
358 mbusc: mbus-controller@20000 {
359 compatible = "marvell,mbus-controller";
360 reg = <0x20000 0x100>, <0x20180 0x20>;
363 mpic: interrupt-controller@20000 {
364 compatible = "marvell,mpic";
365 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
366 #interrupt-cells = <1>;
368 interrupt-controller;
370 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
374 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
375 reg = <0x20300 0x30>, <0x21040 0x30>;
376 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
377 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
378 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
379 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
382 clocks = <&coreclk 0>, <&refclk>;
383 clock-names = "nbclk", "fixed";
387 compatible = "marvell,armada-375-wdt";
388 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
389 clocks = <&coreclk 0>, <&refclk>;
390 clock-names = "nbclk", "fixed";
394 compatible = "marvell,armada-370-cpu-reset";
395 reg = <0x20800 0x10>;
398 coherency-fabric@21010 {
399 compatible = "marvell,armada-375-coherency-fabric";
400 reg = <0x21010 0x1c>;
404 compatible = "marvell,orion-ehci";
405 reg = <0x50000 0x500>;
406 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&gateclk 18>;
408 phys = <&usbcluster PHY_TYPE_USB2>;
414 compatible = "marvell,orion-ehci";
415 reg = <0x54000 0x500>;
416 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&gateclk 26>;
422 compatible = "marvell,armada-375-xhci";
423 reg = <0x58000 0x20000>,<0x5b880 0x80>;
424 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&gateclk 16>;
426 phys = <&usbcluster PHY_TYPE_USB3>;
432 compatible = "marvell,orion-xor";
435 clocks = <&gateclk 22>;
439 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
444 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
452 compatible = "marvell,orion-xor";
455 clocks = <&gateclk 23>;
459 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
464 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
472 compatible = "marvell,orion-sata";
473 reg = <0xa0000 0x5000>;
474 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&gateclk 14>, <&gateclk 20>;
476 clock-names = "0", "1";
481 compatible = "marvell,armada370-nand";
482 reg = <0xd0000 0x54>;
483 #address-cells = <1>;
485 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&gateclk 11>;
491 compatible = "marvell,orion-sdio";
492 reg = <0xd4000 0x200>;
493 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&gateclk 17>;
503 compatible = "marvell,armada375-thermal";
504 reg = <0xe8078 0x4>, <0xe807c 0x8>;
508 coreclk: mvebu-sar@e8204 {
509 compatible = "marvell,armada-375-core-clock";
510 reg = <0xe8204 0x04>;
514 coredivclk: corediv-clock@e8250 {
515 compatible = "marvell,armada-375-corediv-clock";
519 clock-output-names = "nand";
524 compatible = "marvell,armada-370-pcie";
528 #address-cells = <3>;
531 msi-parent = <&mpic>;
532 bus-range = <0x00 0xff>;
535 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
536 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
537 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
538 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
539 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
540 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
544 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
545 reg = <0x0800 0 0 0 0>;
546 #address-cells = <3>;
548 #interrupt-cells = <1>;
549 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
550 0x81000000 0 0 0x81000000 0x1 0 1 0>;
551 interrupt-map-mask = <0 0 0 0>;
552 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
553 marvell,pcie-port = <0>;
554 marvell,pcie-lane = <0>;
555 clocks = <&gateclk 5>;
561 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
562 reg = <0x1000 0 0 0 0>;
563 #address-cells = <3>;
565 #interrupt-cells = <1>;
566 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
567 0x81000000 0 0 0x81000000 0x2 0 1 0>;
568 interrupt-map-mask = <0 0 0 0>;
569 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
570 marvell,pcie-port = <0>;
571 marvell,pcie-lane = <1>;
572 clocks = <&gateclk 6>;