arch/arm/boot/dts/armada-370.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 370 family SoC
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  *
  14  * Contains definitions specific to the Armada 370 SoC that are not
  15  * common to all Armada SoCs.
  16  */
  17
  18 #include "armada-370-xp.dtsi"
  19 /include/ "skeleton.dtsi"
  20
  21 / {
  22         model = "Marvell Armada 370 family SoC";
  23         compatible = "marvell,armada370", "marvell,armada-370-xp";
  24
  25         aliases {
  26                 gpio0 = &gpio0;
  27                 gpio1 = &gpio1;
  28                 gpio2 = &gpio2;
  29         };
  30
  31         soc {
  32                 compatible = "marvell,armada370-mbus", "simple-bus";
  33
  34                 bootrom {
  35                         compatible = "marvell,bootrom";
  36                         reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
  37                 };
  38
  39                 pcie-controller {
  40                         compatible = "marvell,armada-370-pcie";
  41                         status = "disabled";
  42                         device_type = "pci";
  43
  44                         #address-cells = <3>;
  45                         #size-cells = <2>;
  46
  47                         msi-parent = <&mpic>;
  48                         bus-range = <0x00 0xff>;
  49
  50                         ranges =
  51                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
  52                                 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
  53                                 0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
  54                                 0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
  55                                 0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */
  56                                 0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;
  57
  58                         pcie@1,0 {
  59                                 device_type = "pci";
  60                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
  61                                 reg = <0x0800 0 0 0 0>;
  62                                 #address-cells = <3>;
  63                                 #size-cells = <2>;
  64                                 #interrupt-cells = <1>;
  65                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
  66                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
  67                                 interrupt-map-mask = <0 0 0 0>;
  68                                 interrupt-map = <0 0 0 0 &mpic 58>;
  69                                 marvell,pcie-port = <0>;
  70                                 marvell,pcie-lane = <0>;
  71                                 clocks = <&gateclk 5>;
  72                                 status = "disabled";
  73                         };
  74
  75                         pcie@2,0 {
  76                                 device_type = "pci";
  77                                 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
  78                                 reg = <0x1000 0 0 0 0>;
  79                                 #address-cells = <3>;
  80                                 #size-cells = <2>;
  81                                 #interrupt-cells = <1>;
  82                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
  83                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
  84                                 interrupt-map-mask = <0 0 0 0>;
  85                                 interrupt-map = <0 0 0 0 &mpic 62>;
  86                                 marvell,pcie-port = <1>;
  87                                 marvell,pcie-lane = <0>;
  88                                 clocks = <&gateclk 9>;
  89                                 status = "disabled";
  90                         };
  91                 };
  92
  93                 internal-regs {
  94                         L2: l2-cache {
  95                                 compatible = "marvell,aurora-outer-cache";
  96                                 reg = <0x08000 0x1000>;
  97                                 cache-id-part = <0x100>;
  98                                 cache-unified;
  99                                 wt-override;
 100                         };
 101
 102                         /*
 103                          * Default SPI pinctrl setting, can be overwritten on
 104                          * board level if a different configuration is used.
 105                          */
 106                         spi0: spi@10600 {
 107                                 pinctrl-0 = <&spi0_pins1>;
 108                                 pinctrl-names = "default";
 109                         };
 110
 111                         spi1: spi@10680 {
 112                                 pinctrl-0 = <&spi1_pins>;
 113                                 pinctrl-names = "default";
 114                         };
 115
 116                         i2c0: i2c@11000 {
 117                                 reg = <0x11000 0x20>;
 118                         };
 119
 120                         i2c1: i2c@11100 {
 121                                 reg = <0x11100 0x20>;
 122                         };
 123
 124                         gpio0: gpio@18100 {
 125                                 compatible = "marvell,orion-gpio";
 126                                 reg = <0x18100 0x40>;
 127                                 ngpios = <32>;
 128                                 gpio-controller;
 129                                 #gpio-cells = <2>;
 130                                 interrupt-controller;
 131                                 #interrupt-cells = <2>;
 132                                 interrupts = <82>, <83>, <84>, <85>;
 133                         };
 134
 135                         gpio1: gpio@18140 {
 136                                 compatible = "marvell,orion-gpio";
 137                                 reg = <0x18140 0x40>;
 138                                 ngpios = <32>;
 139                                 gpio-controller;
 140                                 #gpio-cells = <2>;
 141                                 interrupt-controller;
 142                                 #interrupt-cells = <2>;
 143                                 interrupts = <87>, <88>, <89>, <90>;
 144                         };
 145
 146                         gpio2: gpio@18180 {
 147                                 compatible = "marvell,orion-gpio";
 148                                 reg = <0x18180 0x40>;
 149                                 ngpios = <2>;
 150                                 gpio-controller;
 151                                 #gpio-cells = <2>;
 152                                 interrupt-controller;
 153                                 #interrupt-cells = <2>;
 154                                 interrupts = <91>;
 155                         };
 156
 157                         /*
 158                          * Default UART pinctrl setting without RTS/CTS, can
 159                          * be overwritten on board level if a different
 160                          * configuration is used.
 161                          */
 162                         uart0: serial@12000 {
 163                                 pinctrl-0 = <&uart0_pins>;
 164                                 pinctrl-names = "default";
 165                         };
 166
 167                         uart1: serial@12100 {
 168                                 pinctrl-0 = <&uart1_pins>;
 169                                 pinctrl-names = "default";
 170                         };
 171
 172                         system-controller@18200 {
 173                                 compatible = "marvell,armada-370-xp-system-controller";
 174                                 reg = <0x18200 0x100>;
 175                         };
 176
 177                         gateclk: clock-gating-control@18220 {
 178                                 compatible = "marvell,armada-370-gating-clock";
 179                                 reg = <0x18220 0x4>;
 180                                 clocks = <&coreclk 0>;
 181                                 #clock-cells = <1>;
 182                         };
 183
 184                         coreclk: mvebu-sar@18230 {
 185                                 compatible = "marvell,armada-370-core-clock";
 186                                 reg = <0x18230 0x08>;
 187                                 #clock-cells = <1>;
 188                         };
 189
 190                         thermal@18300 {
 191                                 compatible = "marvell,armada370-thermal";
 192                                 reg = <0x18300 0x4
 193                                         0x18304 0x4>;
 194                                 status = "okay";
 195                         };
 196
 197                         sscg@18330 {
 198                                 reg = <0x18330 0x4>;
 199                         };
 200
 201                         interrupt-controller@20000 {
 202                                 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
 203                         };
 204
 205                         timer@20300 {
 206                                 compatible = "marvell,armada-370-timer";
 207                                 clocks = <&coreclk 2>;
 208                         };
 209
 210                         watchdog@20300 {
 211                                 compatible = "marvell,armada-370-wdt";
 212                                 clocks = <&coreclk 2>;
 213                         };
 214
 215                         cpurst@20800 {
 216                                 compatible = "marvell,armada-370-cpu-reset";
 217                                 reg = <0x20800 0x8>;
 218                         };
 219
 220                         audio_controller: audio-controller@30000 {
 221                                 #sound-dai-cells = <1>;
 222                                 compatible = "marvell,armada370-audio";
 223                                 reg = <0x30000 0x4000>;
 224                                 interrupts = <93>;
 225                                 clocks = <&gateclk 0>;
 226                                 clock-names = "internal";
 227                                 status = "disabled";
 228                         };
 229
 230                         usb@50000 {
 231                                 clocks = <&coreclk 0>;
 232                         };
 233
 234                         usb@51000 {
 235                                 clocks = <&coreclk 0>;
 236                         };
 237
 238                         xor@60800 {
 239                                 compatible = "marvell,orion-xor";
 240                                 reg = <0x60800 0x100
 241                                        0x60A00 0x100>;
 242                                 status = "okay";
 243
 244                                 xor00 {
 245                                         interrupts = <51>;
 246                                         dmacap,memcpy;
 247                                         dmacap,xor;
 248                                 };
 249                                 xor01 {
 250                                         interrupts = <52>;
 251                                         dmacap,memcpy;
 252                                         dmacap,xor;
 253                                         dmacap,memset;
 254                                 };
 255                         };
 256
 257                         xor@60900 {
 258                                 compatible = "marvell,orion-xor";
 259                                 reg = <0x60900 0x100
 260                                        0x60b00 0x100>;
 261                                 status = "okay";
 262
 263                                 xor10 {
 264                                         interrupts = <94>;
 265                                         dmacap,memcpy;
 266                                         dmacap,xor;
 267                                 };
 268                                 xor11 {
 269                                         interrupts = <95>;
 270                                         dmacap,memcpy;
 271                                         dmacap,xor;
 272                                         dmacap,memset;
 273                                 };
 274                         };
 275                 };
 276         };
 277 };
 278
 279 &pinctrl {
 280         compatible = "marvell,mv88f6710-pinctrl";
 281
 282         spi0_pins1: spi0-pins1 {
 283                 marvell,pins = "mpp33", "mpp34",
 284                                "mpp35", "mpp36";
 285                 marvell,function = "spi0";
 286         };
 287
 288         spi0_pins2: spi0_pins2 {
 289                 marvell,pins = "mpp32", "mpp63",
 290                                "mpp64", "mpp65";
 291                 marvell,function = "spi0";
 292         };
 293
 294         spi1_pins: spi1-pins {
 295                 marvell,pins = "mpp49", "mpp50",
 296                                "mpp51", "mpp52";
 297                 marvell,function = "spi1";
 298         };
 299
 300         uart0_pins: uart0-pins {
 301                 marvell,pins = "mpp0", "mpp1";
 302                 marvell,function = "uart0";
 303         };
 304
 305         uart1_pins: uart1-pins {
 306                 marvell,pins = "mpp41", "mpp42";
 307                 marvell,function = "uart1";
 308         };
 309
 310         sdio_pins1: sdio-pins1 {
 311                 marvell,pins = "mpp9",  "mpp11", "mpp12",
 312                                 "mpp13", "mpp14", "mpp15";
 313                 marvell,function = "sd0";
 314         };
 315
 316         sdio_pins2: sdio-pins2 {
 317                 marvell,pins = "mpp47", "mpp48", "mpp49",
 318                                 "mpp50", "mpp51", "mpp52";
 319                 marvell,function = "sd0";
 320         };
 321
 322         sdio_pins3: sdio-pins3 {
 323                 marvell,pins = "mpp48", "mpp49", "mpp50",
 324                                 "mpp51", "mpp52", "mpp53";
 325                 marvell,function = "sd0";
 326         };
 327
 328         i2c0_pins: i2c0-pins {
 329                 marvell,pins = "mpp2", "mpp3";
 330                 marvell,function = "i2c0";
 331         };
 332
 333         i2s_pins1: i2s-pins1 {
 334                 marvell,pins = "mpp5", "mpp6", "mpp7",
 335                                "mpp8", "mpp9", "mpp10",
 336                                "mpp12", "mpp13";
 337                 marvell,function = "audio";
 338         };
 339
 340         i2s_pins2: i2s-pins2 {
 341                 marvell,pins = "mpp49", "mpp47", "mpp50",
 342                                "mpp59", "mpp57", "mpp61",
 343                                "mpp62", "mpp60", "mpp58";
 344                 marvell,function = "audio";
 345         };
 346
 347         mdio_pins: mdio-pins {
 348                 marvell,pins = "mpp17", "mpp18";
 349                 marvell,function = "ge";
 350         };
 351
 352         ge0_rgmii_pins: ge0-rgmii-pins {
 353                 marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
 354                                "mpp9", "mpp10", "mpp11", "mpp12",
 355                                "mpp13", "mpp14", "mpp15", "mpp16";
 356                 marvell,function = "ge0";
 357         };
 358
 359         ge1_rgmii_pins: ge1-rgmii-pins {
 360                 marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
 361                                "mpp23", "mpp24", "mpp25", "mpp26",
 362                                "mpp27", "mpp28", "mpp29", "mpp30";
 363                 marvell,function = "ge1";
 364         };
 365 };