arch/arm/boot/dts/arm-realview-pb1176.dts

   1 /*
   2  * Copyright 2014 Linaro Ltd
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20  * THE SOFTWARE.
  21  */
  22
  23 /dts-v1/;
  24 #include <dt-bindings/interrupt-controller/irq.h>
  25 #include "skeleton.dtsi"
  26
  27 / {
  28         model = "ARM RealView PB1176";
  29         compatible = "arm,realview-pb1176";
  30
  31         chosen { };
  32
  33         aliases {
  34                 serial0 = &pb1176_serial0;
  35                 serial1 = &pb1176_serial1;
  36                 serial2 = &pb1176_serial2;
  37                 serial3 = &pb1176_serial3;
  38                 serial4 = &fpga_serial;
  39         };
  40
  41         memory {
  42                 /* 128 MiB memory @ 0x0 */
  43                 reg = <0x00000000 0x08000000>;
  44         };
  45
  46         xtal24mhz: xtal24mhz@24M {
  47                 #clock-cells = <0>;
  48                 compatible = "fixed-clock";
  49                 clock-frequency = <24000000>;
  50         };
  51
  52         timclk: timclk@1M {
  53                 #clock-cells = <0>;
  54                 compatible = "fixed-factor-clock";
  55                 clock-div = <24>;
  56                 clock-mult = <1>;
  57                 clocks = <&xtal24mhz>;
  58         };
  59
  60         kmiclk: kmiclk@24M {
  61                 #clock-cells = <0>;
  62                 compatible = "fixed-factor-clock";
  63                 clock-div = <1>;
  64                 clock-mult = <1>;
  65                 clocks = <&xtal24mhz>;
  66         };
  67
  68         sspclk: sspclk@24M {
  69                 #clock-cells = <0>;
  70                 compatible = "fixed-factor-clock";
  71                 clock-div = <1>;
  72                 clock-mult = <1>;
  73                 clocks = <&xtal24mhz>;
  74         };
  75
  76         uartclk: uartclk@24M {
  77                 #clock-cells = <0>;
  78                 compatible = "fixed-factor-clock";
  79                 clock-div = <1>;
  80                 clock-mult = <1>;
  81                 clocks = <&xtal24mhz>;
  82         };
  83
  84         /* FIXME: this actually hangs off the PLL clocks */
  85         pclk: pclk@0 {
  86                 #clock-cells = <0>;
  87                 compatible = "fixed-clock";
  88                 clock-frequency = <0>;
  89         };
  90
  91         soc {
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 compatible = "arm,realview-pb1176-soc", "simple-bus";
  95                 regmap = <&syscon>;
  96                 ranges;
  97
  98                 syscon: syscon@10000000 {
  99                         compatible = "arm,realview-pb1176-syscon", "syscon";
 100                         reg = <0x10000000 0x1000>;
 101
 102                         led@08.0 {
 103                                 compatible = "register-bit-led";
 104                                 offset = <0x08>;
 105                                 mask = <0x01>;
 106                                 label = "versatile:0";
 107                                 linux,default-trigger = "heartbeat";
 108                                 default-state = "on";
 109                         };
 110                         led@08.1 {
 111                                 compatible = "register-bit-led";
 112                                 offset = <0x08>;
 113                                 mask = <0x02>;
 114                                 label = "versatile:1";
 115                                 linux,default-trigger = "mmc0";
 116                                 default-state = "off";
 117                         };
 118                         led@08.2 {
 119                                 compatible = "register-bit-led";
 120                                 offset = <0x08>;
 121                                 mask = <0x04>;
 122                                 label = "versatile:2";
 123                                 linux,default-trigger = "cpu0";
 124                                 default-state = "off";
 125                         };
 126                         led@08.3 {
 127                                 compatible = "register-bit-led";
 128                                 offset = <0x08>;
 129                                 mask = <0x08>;
 130                                 label = "versatile:3";
 131                                 default-state = "off";
 132                         };
 133                         led@08.4 {
 134                                 compatible = "register-bit-led";
 135                                 offset = <0x08>;
 136                                 mask = <0x10>;
 137                                 label = "versatile:4";
 138                                 default-state = "off";
 139                         };
 140                         led@08.5 {
 141                                 compatible = "register-bit-led";
 142                                 offset = <0x08>;
 143                                 mask = <0x20>;
 144                                 label = "versatile:5";
 145                                 default-state = "off";
 146                         };
 147                         led@08.6 {
 148                                 compatible = "register-bit-led";
 149                                 offset = <0x08>;
 150                                 mask = <0x40>;
 151                                 label = "versatile:6";
 152                                 default-state = "off";
 153                         };
 154                         led@08.7 {
 155                                 compatible = "register-bit-led";
 156                                 offset = <0x08>;
 157                                 mask = <0x80>;
 158                                 label = "versatile:7";
 159                                 default-state = "off";
 160                         };
 161                 };
 162
 163                 /* Primary DevChip GIC synthesized with the CPU */
 164                 intc_dc1176: interrupt-controller@10120000 {
 165                         compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
 166                         #interrupt-cells = <3>;
 167                         #address-cells = <1>;
 168                         interrupt-controller;
 169                         reg = <0x10121000 0x1000>,
 170                               <0x10120000 0x100>;
 171                 };
 172
 173                 L2: l2-cache {
 174                         compatible = "arm,l220-cache";
 175                         reg = <0x10110000 0x1000>;
 176                         interrupt-parent = <&intc_dc1176>;
 177                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
 178                         cache-unified;
 179                         cache-level = <2>;
 180                         /*
 181                          * Override default cache size, sets and
 182                          * associativity as these may be erroneously set
 183                          * up by boot loader(s).
 184                          */
 185                         arm,override-auxreg;
 186                         cache-size = <131072>; // 128kB
 187                         cache-sets = <512>;
 188                         cache-line-size = <32>;
 189                 };
 190
 191                 pmu {
 192                         compatible = "arm,arm1176-pmu";
 193                         interrupt-parent = <&intc_dc1176>;
 194                         interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 195                 };
 196
 197                 timer01: timer@10104000 {
 198                         compatible = "arm,sp804", "arm,primecell";
 199                         reg = <0x10104000 0x1000>;
 200                         interrupt-parent = <&intc_dc1176>;
 201                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
 202                         clocks = <&timclk>, <&timclk>, <&pclk>;
 203                         clock-names = "timer1", "timer2", "apb_pclk";
 204                 };
 205
 206                 timer23: timer@10105000 {
 207                         compatible = "arm,sp804", "arm,primecell";
 208                         reg = <0x10105000 0x1000>;
 209                         interrupt-parent = <&intc_dc1176>;
 210                         interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 211                         arm,sp804-has-irq = <1>;
 212                         clocks = <&timclk>, <&timclk>, <&pclk>;
 213                         clock-names = "timer1", "timer2", "apb_pclk";
 214                 };
 215
 216                 pb1176_rtc: rtc@10108000 {
 217                         compatible = "arm,pl031", "arm,primecell";
 218                         reg = <0x10108000 0x1000>;
 219                         interrupt-parent = <&intc_dc1176>;
 220                         interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 221                         clocks = <&pclk>;
 222                         clock-names = "apb_pclk";
 223                 };
 224
 225                 pb1176_gpio0: gpio@1010a000 {
 226                         compatible = "arm,pl061", "arm,primecell";
 227                         reg = <0x1010a000 0x1000>;
 228                         gpio-controller;
 229                         interrupt-parent = <&intc_dc1176>;
 230                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
 231                         #gpio-cells = <2>;
 232                         interrupt-controller;
 233                         #interrupt-cells = <2>;
 234                         clocks = <&pclk>;
 235                         clock-names = "apb_pclk";
 236                 };
 237
 238                 pb1176_ssp: ssp@1010b000 {
 239                         compatible = "arm,pl022", "arm,primecell";
 240                         reg = <0x1010b000 0x1000>;
 241                         interrupt-parent = <&intc_dc1176>;
 242                         interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
 243                         clocks = <&sspclk>, <&pclk>;
 244                         clock-names = "SSPCLK", "apb_pclk";
 245                 };
 246
 247                 pb1176_serial0: serial@1010c000 {
 248                         compatible = "arm,pl011", "arm,primecell";
 249                         reg = <0x1010c000 0x1000>;
 250                         interrupt-parent = <&intc_dc1176>;
 251                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 252                         clocks = <&uartclk>, <&pclk>;
 253                         clock-names = "uartclk", "apb_pclk";
 254                 };
 255
 256                 pb1176_serial1: serial@1010d000 {
 257                         compatible = "arm,pl011", "arm,primecell";
 258                         reg = <0x1010d000 0x1000>;
 259                         interrupt-parent = <&intc_dc1176>;
 260                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 261                         clocks = <&uartclk>, <&pclk>;
 262                         clock-names = "uartclk", "apb_pclk";
 263                 };
 264
 265                 pb1176_serial2: serial@1010e000 {
 266                         compatible = "arm,pl011", "arm,primecell";
 267                         reg = <0x1010e000 0x1000>;
 268                         interrupt-parent = <&intc_dc1176>;
 269                         interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
 270                         clocks = <&uartclk>, <&pclk>;
 271                         clock-names = "uartclk", "apb_pclk";
 272                 };
 273
 274                 pb1176_serial3: serial@1010f000 {
 275                         compatible = "arm,pl011", "arm,primecell";
 276                         reg = <0x1010f000 0x1000>;
 277                         interrupt-parent = <&intc_dc1176>;
 278                         interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 279                         clocks = <&uartclk>, <&pclk>;
 280                         clock-names = "uartclk", "apb_pclk";
 281                 };
 282         };
 283
 284         /* These peripherals are inside the FPGA rather than the DevChip */
 285         fpga {
 286                 #address-cells = <1>;
 287                 #size-cells = <1>;
 288                 compatible = "simple-bus";
 289                 ranges;
 290
 291                 fpga_kmi0: kmi@10006000 {
 292                         compatible = "arm,pl050", "arm,primecell";
 293                         reg = <0x10006000 0x1000>;
 294                         interrupt-parent = <&intc_fpga1176>;
 295                         interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
 296                         clocks = <&kmiclk>, <&pclk>;
 297                         clock-names = "KMIREFCLK", "apb_pclk";
 298                 };
 299
 300                 fpga_kmi1: kmi@10007000 {
 301                         compatible = "arm,pl050", "arm,primecell";
 302                         reg = <0x10007000 0x1000>;
 303                         interrupt-parent = <&intc_fpga1176>;
 304                         interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
 305                         clocks = <&kmiclk>, <&pclk>;
 306                         clock-names = "KMIREFCLK", "apb_pclk";
 307                 };
 308
 309                 fpga_charlcd: charlcd@10008000 {
 310                         compatible = "arm,versatile-lcd";
 311                         reg = <0x10008000 0x1000>;
 312                         interrupt-parent = <&intc_fpga1176>;
 313                         interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 314                         clocks = <&pclk>;
 315                         clock-names = "apb_pclk";
 316                 };
 317
 318                 fpga_serial: serial@10009000 {
 319                         compatible = "arm,pl011", "arm,primecell";
 320                         reg = <0x10009000 0x1000>;
 321                         interrupt-parent = <&intc_fpga1176>;
 322                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 323                         clocks = <&uartclk>, <&pclk>;
 324                         clock-names = "uartclk", "apb_pclk";
 325                 };
 326
 327                 /* This GIC on the board is cascaded off the DevChip GIC */
 328                 intc_fpga1176: interrupt-controller@10040000 {
 329                         compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
 330                         #interrupt-cells = <3>;
 331                         #address-cells = <1>;
 332                         interrupt-controller;
 333                         reg = <0x10041000 0x1000>,
 334                               <0x10040000 0x100>;
 335                         interrupt-parent = <&intc_dc1176>;
 336                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 337                 };
 338
 339                 fpga_gpio0: gpio@10014000 {
 340                         compatible = "arm,pl061", "arm,primecell";
 341                         reg = <0x10014000 0x1000>;
 342                         gpio-controller;
 343                         interrupt-parent = <&intc_fpga1176>;
 344                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 345                         #gpio-cells = <2>;
 346                         interrupt-controller;
 347                         #interrupt-cells = <2>;
 348                         clocks = <&pclk>;
 349                         clock-names = "apb_pclk";
 350                 };
 351
 352                 fpga_gpio1: gpio@10015000 {
 353                         compatible = "arm,pl061", "arm,primecell";
 354                         reg = <0x10015000 0x1000>;
 355                         gpio-controller;
 356                         interrupt-parent = <&intc_fpga1176>;
 357                         interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 358                         #gpio-cells = <2>;
 359                         interrupt-controller;
 360                         #interrupt-cells = <2>;
 361                         clocks = <&pclk>;
 362                         clock-names = "apb_pclk";
 363                 };
 364
 365                 fpga_rtc: rtc@10017000 {
 366                         compatible = "arm,pl031", "arm,primecell";
 367                         reg = <0x10017000 0x1000>;
 368                         interrupt-parent = <&intc_fpga1176>;
 369                         interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 370                         clocks = <&pclk>;
 371                         clock-names = "apb_pclk";
 372                 };
 373
 374
 375         };
 376 };