2 * Device Tree Source for AM43xx clock data
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 sys_clkin_ck: sys_clkin_ck {
13 compatible = "ti,mux-clock";
14 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
19 crystal_freq_sel_ck: crystal_freq_sel_ck {
21 compatible = "ti,mux-clock";
22 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
27 sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
29 compatible = "ti,mux-clock";
30 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
35 adc_tsc_fck: adc_tsc_fck {
37 compatible = "fixed-factor-clock";
38 clocks = <&sys_clkin_ck>;
43 dcan0_fck: dcan0_fck {
45 compatible = "fixed-factor-clock";
46 clocks = <&sys_clkin_ck>;
51 dcan1_fck: dcan1_fck {
53 compatible = "fixed-factor-clock";
54 clocks = <&sys_clkin_ck>;
59 mcasp0_fck: mcasp0_fck {
61 compatible = "fixed-factor-clock";
62 clocks = <&sys_clkin_ck>;
67 mcasp1_fck: mcasp1_fck {
69 compatible = "fixed-factor-clock";
70 clocks = <&sys_clkin_ck>;
75 smartreflex0_fck: smartreflex0_fck {
77 compatible = "fixed-factor-clock";
78 clocks = <&sys_clkin_ck>;
83 smartreflex1_fck: smartreflex1_fck {
85 compatible = "fixed-factor-clock";
86 clocks = <&sys_clkin_ck>;
93 compatible = "fixed-factor-clock";
94 clocks = <&sys_clkin_ck>;
101 compatible = "fixed-factor-clock";
102 clocks = <&sys_clkin_ck>;
107 ehrpwm0_tbclk: ehrpwm0_tbclk {
109 compatible = "ti,gate-clock";
110 clocks = <&l4ls_gclk>;
115 ehrpwm1_tbclk: ehrpwm1_tbclk {
117 compatible = "ti,gate-clock";
118 clocks = <&l4ls_gclk>;
123 ehrpwm2_tbclk: ehrpwm2_tbclk {
125 compatible = "ti,gate-clock";
126 clocks = <&l4ls_gclk>;
131 ehrpwm3_tbclk: ehrpwm3_tbclk {
133 compatible = "ti,gate-clock";
134 clocks = <&l4ls_gclk>;
139 ehrpwm4_tbclk: ehrpwm4_tbclk {
141 compatible = "ti,gate-clock";
142 clocks = <&l4ls_gclk>;
147 ehrpwm5_tbclk: ehrpwm5_tbclk {
149 compatible = "ti,gate-clock";
150 clocks = <&l4ls_gclk>;
156 clk_32768_ck: clk_32768_ck {
158 compatible = "fixed-clock";
159 clock-frequency = <32768>;
162 clk_rc32k_ck: clk_rc32k_ck {
164 compatible = "fixed-clock";
165 clock-frequency = <32768>;
168 virt_19200000_ck: virt_19200000_ck {
170 compatible = "fixed-clock";
171 clock-frequency = <19200000>;
174 virt_24000000_ck: virt_24000000_ck {
176 compatible = "fixed-clock";
177 clock-frequency = <24000000>;
180 virt_25000000_ck: virt_25000000_ck {
182 compatible = "fixed-clock";
183 clock-frequency = <25000000>;
186 virt_26000000_ck: virt_26000000_ck {
188 compatible = "fixed-clock";
189 clock-frequency = <26000000>;
192 tclkin_ck: tclkin_ck {
194 compatible = "fixed-clock";
195 clock-frequency = <26000000>;
198 dpll_core_ck: dpll_core_ck {
200 compatible = "ti,am3-dpll-core-clock";
201 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
202 reg = <0x2d20>, <0x2d24>, <0x2d2c>;
205 dpll_core_x2_ck: dpll_core_x2_ck {
207 compatible = "ti,am3-dpll-x2-clock";
208 clocks = <&dpll_core_ck>;
211 dpll_core_m4_ck: dpll_core_m4_ck {
213 compatible = "ti,divider-clock";
214 clocks = <&dpll_core_x2_ck>;
216 ti,autoidle-shift = <8>;
218 ti,index-starts-at-one;
219 ti,invert-autoidle-bit;
222 dpll_core_m5_ck: dpll_core_m5_ck {
224 compatible = "ti,divider-clock";
225 clocks = <&dpll_core_x2_ck>;
227 ti,autoidle-shift = <8>;
229 ti,index-starts-at-one;
230 ti,invert-autoidle-bit;
233 dpll_core_m6_ck: dpll_core_m6_ck {
235 compatible = "ti,divider-clock";
236 clocks = <&dpll_core_x2_ck>;
238 ti,autoidle-shift = <8>;
240 ti,index-starts-at-one;
241 ti,invert-autoidle-bit;
244 dpll_mpu_ck: dpll_mpu_ck {
246 compatible = "ti,am3-dpll-clock";
247 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
248 reg = <0x2d60>, <0x2d64>, <0x2d6c>;
251 dpll_mpu_m2_ck: dpll_mpu_m2_ck {
253 compatible = "ti,divider-clock";
254 clocks = <&dpll_mpu_ck>;
256 ti,autoidle-shift = <8>;
258 ti,index-starts-at-one;
259 ti,invert-autoidle-bit;
262 dpll_ddr_ck: dpll_ddr_ck {
264 compatible = "ti,am3-dpll-clock";
265 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
266 reg = <0x2da0>, <0x2da4>, <0x2dac>;
269 dpll_ddr_m2_ck: dpll_ddr_m2_ck {
271 compatible = "ti,divider-clock";
272 clocks = <&dpll_ddr_ck>;
274 ti,autoidle-shift = <8>;
276 ti,index-starts-at-one;
277 ti,invert-autoidle-bit;
280 dpll_disp_ck: dpll_disp_ck {
282 compatible = "ti,am3-dpll-clock";
283 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
284 reg = <0x2e20>, <0x2e24>, <0x2e2c>;
287 dpll_disp_m2_ck: dpll_disp_m2_ck {
289 compatible = "ti,divider-clock";
290 clocks = <&dpll_disp_ck>;
292 ti,autoidle-shift = <8>;
294 ti,index-starts-at-one;
295 ti,invert-autoidle-bit;
299 dpll_per_ck: dpll_per_ck {
301 compatible = "ti,am3-dpll-j-type-clock";
302 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
303 reg = <0x2de0>, <0x2de4>, <0x2dec>;
306 dpll_per_m2_ck: dpll_per_m2_ck {
308 compatible = "ti,divider-clock";
309 clocks = <&dpll_per_ck>;
311 ti,autoidle-shift = <8>;
313 ti,index-starts-at-one;
314 ti,invert-autoidle-bit;
317 dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
319 compatible = "fixed-factor-clock";
320 clocks = <&dpll_per_m2_ck>;
325 dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
327 compatible = "fixed-factor-clock";
328 clocks = <&dpll_per_m2_ck>;
333 clk_24mhz: clk_24mhz {
335 compatible = "fixed-factor-clock";
336 clocks = <&dpll_per_m2_ck>;
341 clkdiv32k_ck: clkdiv32k_ck {
343 compatible = "fixed-factor-clock";
344 clocks = <&clk_24mhz>;
349 clkdiv32k_ick: clkdiv32k_ick {
351 compatible = "ti,gate-clock";
352 clocks = <&clkdiv32k_ck>;
357 sysclk_div: sysclk_div {
359 compatible = "fixed-factor-clock";
360 clocks = <&dpll_core_m4_ck>;
365 pruss_ocp_gclk: pruss_ocp_gclk {
367 compatible = "ti,mux-clock";
368 clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
372 clk_32k_tpm_ck: clk_32k_tpm_ck {
374 compatible = "fixed-clock";
375 clock-frequency = <32768>;
378 timer1_fck: timer1_fck {
380 compatible = "ti,mux-clock";
381 clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
385 timer2_fck: timer2_fck {
387 compatible = "ti,mux-clock";
388 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
392 timer3_fck: timer3_fck {
394 compatible = "ti,mux-clock";
395 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
399 timer4_fck: timer4_fck {
401 compatible = "ti,mux-clock";
402 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
406 timer5_fck: timer5_fck {
408 compatible = "ti,mux-clock";
409 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
413 timer6_fck: timer6_fck {
415 compatible = "ti,mux-clock";
416 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
420 timer7_fck: timer7_fck {
422 compatible = "ti,mux-clock";
423 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
429 compatible = "ti,mux-clock";
430 clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
436 compatible = "fixed-factor-clock";
437 clocks = <&dpll_core_m4_ck>;
442 dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
444 compatible = "fixed-factor-clock";
445 clocks = <&sysclk_div>;
450 l4hs_gclk: l4hs_gclk {
452 compatible = "fixed-factor-clock";
453 clocks = <&dpll_core_m4_ck>;
460 compatible = "fixed-factor-clock";
461 clocks = <&dpll_core_m4_div2_ck>;
466 l4ls_gclk: l4ls_gclk {
468 compatible = "fixed-factor-clock";
469 clocks = <&dpll_core_m4_div2_ck>;
474 cpsw_125mhz_gclk: cpsw_125mhz_gclk {
476 compatible = "fixed-factor-clock";
477 clocks = <&dpll_core_m5_ck>;
482 cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
484 compatible = "ti,mux-clock";
485 clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
489 dpll_clksel_mac_clk: dpll_clksel_mac_clk {
491 compatible = "ti,divider-clock";
492 clocks = <&dpll_core_m5_ck>;
495 ti,dividers = <2>, <5>;
498 clk_32k_mosc_ck: clk_32k_mosc_ck {
500 compatible = "fixed-clock";
501 clock-frequency = <32768>;
504 gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
506 compatible = "ti,mux-clock";
507 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
511 gpio0_dbclk: gpio0_dbclk {
513 compatible = "ti,gate-clock";
514 clocks = <&gpio0_dbclk_mux_ck>;
519 gpio1_dbclk: gpio1_dbclk {
521 compatible = "ti,gate-clock";
522 clocks = <&clkdiv32k_ick>;
527 gpio2_dbclk: gpio2_dbclk {
529 compatible = "ti,gate-clock";
530 clocks = <&clkdiv32k_ick>;
535 gpio3_dbclk: gpio3_dbclk {
537 compatible = "ti,gate-clock";
538 clocks = <&clkdiv32k_ick>;
543 gpio4_dbclk: gpio4_dbclk {
545 compatible = "ti,gate-clock";
546 clocks = <&clkdiv32k_ick>;
551 gpio5_dbclk: gpio5_dbclk {
553 compatible = "ti,gate-clock";
554 clocks = <&clkdiv32k_ick>;
561 compatible = "fixed-factor-clock";
562 clocks = <&dpll_per_m2_ck>;
567 gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
569 compatible = "ti,mux-clock";
570 clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
575 gfx_fck_div_ck: gfx_fck_div_ck {
577 compatible = "ti,divider-clock";
578 clocks = <&gfx_fclk_clksel_ck>;
585 compatible = "ti,mux-clock";
586 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
591 dpll_extdev_ck: dpll_extdev_ck {
593 compatible = "ti,am3-dpll-clock";
594 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
595 reg = <0x2e60>, <0x2e64>, <0x2e6c>;
598 dpll_extdev_m2_ck: dpll_extdev_m2_ck {
600 compatible = "ti,divider-clock";
601 clocks = <&dpll_extdev_ck>;
603 ti,autoidle-shift = <8>;
605 ti,index-starts-at-one;
606 ti,invert-autoidle-bit;
609 mux_synctimer32k_ck: mux_synctimer32k_ck {
611 compatible = "ti,mux-clock";
612 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
616 synctimer_32kclk: synctimer_32kclk {
618 compatible = "ti,gate-clock";
619 clocks = <&mux_synctimer32k_ck>;
624 timer8_fck: timer8_fck {
626 compatible = "ti,mux-clock";
627 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
631 timer9_fck: timer9_fck {
633 compatible = "ti,mux-clock";
634 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
638 timer10_fck: timer10_fck {
640 compatible = "ti,mux-clock";
641 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
645 timer11_fck: timer11_fck {
647 compatible = "ti,mux-clock";
648 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
652 cpsw_50m_clkdiv: cpsw_50m_clkdiv {
654 compatible = "fixed-factor-clock";
655 clocks = <&dpll_core_m5_ck>;
660 cpsw_5m_clkdiv: cpsw_5m_clkdiv {
662 compatible = "fixed-factor-clock";
663 clocks = <&cpsw_50m_clkdiv>;
668 dpll_ddr_x2_ck: dpll_ddr_x2_ck {
670 compatible = "ti,am3-dpll-x2-clock";
671 clocks = <&dpll_ddr_ck>;
674 dpll_ddr_m4_ck: dpll_ddr_m4_ck {
676 compatible = "ti,divider-clock";
677 clocks = <&dpll_ddr_x2_ck>;
679 ti,autoidle-shift = <8>;
681 ti,index-starts-at-one;
682 ti,invert-autoidle-bit;
685 dpll_per_clkdcoldo: dpll_per_clkdcoldo {
687 compatible = "ti,fixed-factor-clock";
688 clocks = <&dpll_per_ck>;
691 ti,autoidle-shift = <8>;
693 ti,invert-autoidle-bit;
696 dll_aging_clk_div: dll_aging_clk_div {
698 compatible = "ti,divider-clock";
699 clocks = <&sys_clkin_ck>;
701 ti,dividers = <8>, <16>, <32>;
704 div_core_25m_ck: div_core_25m_ck {
706 compatible = "fixed-factor-clock";
707 clocks = <&sysclk_div>;
712 func_12m_clk: func_12m_clk {
714 compatible = "fixed-factor-clock";
715 clocks = <&dpll_per_m2_ck>;
720 vtp_clk_div: vtp_clk_div {
722 compatible = "fixed-factor-clock";
723 clocks = <&sys_clkin_ck>;
728 usbphy_32khz_clkmux: usbphy_32khz_clkmux {
730 compatible = "ti,mux-clock";
731 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
735 usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k {
737 compatible = "ti,gate-clock";
738 clocks = <&usbphy_32khz_clkmux>;
743 usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
745 compatible = "ti,gate-clock";
746 clocks = <&usbphy_32khz_clkmux>;
751 usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m {
753 compatible = "ti,gate-clock";
754 clocks = <&dpll_per_clkdcoldo>;
759 usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
761 compatible = "ti,gate-clock";
762 clocks = <&dpll_per_clkdcoldo>;