arch/arm/boot/dts/am43xx-clocks.dtsi

   1 /*
   2  * Device Tree Source for AM43xx clock data
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 &scm_clocks {
  11         sys_clkin_ck: sys_clkin_ck {
  12                 #clock-cells = <0>;
  13                 compatible = "ti,mux-clock";
  14                 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
  15                 ti,bit-shift = <31>;
  16                 reg = <0x0040>;
  17         };
  18
  19         crystal_freq_sel_ck: crystal_freq_sel_ck {
  20                 #clock-cells = <0>;
  21                 compatible = "ti,mux-clock";
  22                 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
  23                 ti,bit-shift = <29>;
  24                 reg = <0x0040>;
  25         };
  26
  27         sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
  28                 #clock-cells = <0>;
  29                 compatible = "ti,mux-clock";
  30                 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
  31                 ti,bit-shift = <22>;
  32                 reg = <0x0040>;
  33         };
  34
  35         adc_tsc_fck: adc_tsc_fck {
  36                 #clock-cells = <0>;
  37                 compatible = "fixed-factor-clock";
  38                 clocks = <&sys_clkin_ck>;
  39                 clock-mult = <1>;
  40                 clock-div = <1>;
  41         };
  42
  43         dcan0_fck: dcan0_fck {
  44                 #clock-cells = <0>;
  45                 compatible = "fixed-factor-clock";
  46                 clocks = <&sys_clkin_ck>;
  47                 clock-mult = <1>;
  48                 clock-div = <1>;
  49         };
  50
  51         dcan1_fck: dcan1_fck {
  52                 #clock-cells = <0>;
  53                 compatible = "fixed-factor-clock";
  54                 clocks = <&sys_clkin_ck>;
  55                 clock-mult = <1>;
  56                 clock-div = <1>;
  57         };
  58
  59         mcasp0_fck: mcasp0_fck {
  60                 #clock-cells = <0>;
  61                 compatible = "fixed-factor-clock";
  62                 clocks = <&sys_clkin_ck>;
  63                 clock-mult = <1>;
  64                 clock-div = <1>;
  65         };
  66
  67         mcasp1_fck: mcasp1_fck {
  68                 #clock-cells = <0>;
  69                 compatible = "fixed-factor-clock";
  70                 clocks = <&sys_clkin_ck>;
  71                 clock-mult = <1>;
  72                 clock-div = <1>;
  73         };
  74
  75         smartreflex0_fck: smartreflex0_fck {
  76                 #clock-cells = <0>;
  77                 compatible = "fixed-factor-clock";
  78                 clocks = <&sys_clkin_ck>;
  79                 clock-mult = <1>;
  80                 clock-div = <1>;
  81         };
  82
  83         smartreflex1_fck: smartreflex1_fck {
  84                 #clock-cells = <0>;
  85                 compatible = "fixed-factor-clock";
  86                 clocks = <&sys_clkin_ck>;
  87                 clock-mult = <1>;
  88                 clock-div = <1>;
  89         };
  90
  91         sha0_fck: sha0_fck {
  92                 #clock-cells = <0>;
  93                 compatible = "fixed-factor-clock";
  94                 clocks = <&sys_clkin_ck>;
  95                 clock-mult = <1>;
  96                 clock-div = <1>;
  97         };
  98
  99         aes0_fck: aes0_fck {
 100                 #clock-cells = <0>;
 101                 compatible = "fixed-factor-clock";
 102                 clocks = <&sys_clkin_ck>;
 103                 clock-mult = <1>;
 104                 clock-div = <1>;
 105         };
 106
 107         ehrpwm0_tbclk: ehrpwm0_tbclk {
 108                 #clock-cells = <0>;
 109                 compatible = "ti,gate-clock";
 110                 clocks = <&l4ls_gclk>;
 111                 ti,bit-shift = <0>;
 112                 reg = <0x0664>;
 113         };
 114
 115         ehrpwm1_tbclk: ehrpwm1_tbclk {
 116                 #clock-cells = <0>;
 117                 compatible = "ti,gate-clock";
 118                 clocks = <&l4ls_gclk>;
 119                 ti,bit-shift = <1>;
 120                 reg = <0x0664>;
 121         };
 122
 123         ehrpwm2_tbclk: ehrpwm2_tbclk {
 124                 #clock-cells = <0>;
 125                 compatible = "ti,gate-clock";
 126                 clocks = <&l4ls_gclk>;
 127                 ti,bit-shift = <2>;
 128                 reg = <0x0664>;
 129         };
 130
 131         ehrpwm3_tbclk: ehrpwm3_tbclk {
 132                 #clock-cells = <0>;
 133                 compatible = "ti,gate-clock";
 134                 clocks = <&l4ls_gclk>;
 135                 ti,bit-shift = <4>;
 136                 reg = <0x0664>;
 137         };
 138
 139         ehrpwm4_tbclk: ehrpwm4_tbclk {
 140                 #clock-cells = <0>;
 141                 compatible = "ti,gate-clock";
 142                 clocks = <&l4ls_gclk>;
 143                 ti,bit-shift = <5>;
 144                 reg = <0x0664>;
 145         };
 146
 147         ehrpwm5_tbclk: ehrpwm5_tbclk {
 148                 #clock-cells = <0>;
 149                 compatible = "ti,gate-clock";
 150                 clocks = <&l4ls_gclk>;
 151                 ti,bit-shift = <6>;
 152                 reg = <0x0664>;
 153         };
 154 };
 155 &prcm_clocks {
 156         clk_32768_ck: clk_32768_ck {
 157                 #clock-cells = <0>;
 158                 compatible = "fixed-clock";
 159                 clock-frequency = <32768>;
 160         };
 161
 162         clk_rc32k_ck: clk_rc32k_ck {
 163                 #clock-cells = <0>;
 164                 compatible = "fixed-clock";
 165                 clock-frequency = <32768>;
 166         };
 167
 168         virt_19200000_ck: virt_19200000_ck {
 169                 #clock-cells = <0>;
 170                 compatible = "fixed-clock";
 171                 clock-frequency = <19200000>;
 172         };
 173
 174         virt_24000000_ck: virt_24000000_ck {
 175                 #clock-cells = <0>;
 176                 compatible = "fixed-clock";
 177                 clock-frequency = <24000000>;
 178         };
 179
 180         virt_25000000_ck: virt_25000000_ck {
 181                 #clock-cells = <0>;
 182                 compatible = "fixed-clock";
 183                 clock-frequency = <25000000>;
 184         };
 185
 186         virt_26000000_ck: virt_26000000_ck {
 187                 #clock-cells = <0>;
 188                 compatible = "fixed-clock";
 189                 clock-frequency = <26000000>;
 190         };
 191
 192         tclkin_ck: tclkin_ck {
 193                 #clock-cells = <0>;
 194                 compatible = "fixed-clock";
 195                 clock-frequency = <26000000>;
 196         };
 197
 198         dpll_core_ck: dpll_core_ck {
 199                 #clock-cells = <0>;
 200                 compatible = "ti,am3-dpll-core-clock";
 201                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 202                 reg = <0x2d20>, <0x2d24>, <0x2d2c>;
 203         };
 204
 205         dpll_core_x2_ck: dpll_core_x2_ck {
 206                 #clock-cells = <0>;
 207                 compatible = "ti,am3-dpll-x2-clock";
 208                 clocks = <&dpll_core_ck>;
 209         };
 210
 211         dpll_core_m4_ck: dpll_core_m4_ck {
 212                 #clock-cells = <0>;
 213                 compatible = "ti,divider-clock";
 214                 clocks = <&dpll_core_x2_ck>;
 215                 ti,max-div = <31>;
 216                 ti,autoidle-shift = <8>;
 217                 reg = <0x2d38>;
 218                 ti,index-starts-at-one;
 219                 ti,invert-autoidle-bit;
 220         };
 221
 222         dpll_core_m5_ck: dpll_core_m5_ck {
 223                 #clock-cells = <0>;
 224                 compatible = "ti,divider-clock";
 225                 clocks = <&dpll_core_x2_ck>;
 226                 ti,max-div = <31>;
 227                 ti,autoidle-shift = <8>;
 228                 reg = <0x2d3c>;
 229                 ti,index-starts-at-one;
 230                 ti,invert-autoidle-bit;
 231         };
 232
 233         dpll_core_m6_ck: dpll_core_m6_ck {
 234                 #clock-cells = <0>;
 235                 compatible = "ti,divider-clock";
 236                 clocks = <&dpll_core_x2_ck>;
 237                 ti,max-div = <31>;
 238                 ti,autoidle-shift = <8>;
 239                 reg = <0x2d40>;
 240                 ti,index-starts-at-one;
 241                 ti,invert-autoidle-bit;
 242         };
 243
 244         dpll_mpu_ck: dpll_mpu_ck {
 245                 #clock-cells = <0>;
 246                 compatible = "ti,am3-dpll-clock";
 247                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 248                 reg = <0x2d60>, <0x2d64>, <0x2d6c>;
 249         };
 250
 251         dpll_mpu_m2_ck: dpll_mpu_m2_ck {
 252                 #clock-cells = <0>;
 253                 compatible = "ti,divider-clock";
 254                 clocks = <&dpll_mpu_ck>;
 255                 ti,max-div = <31>;
 256                 ti,autoidle-shift = <8>;
 257                 reg = <0x2d70>;
 258                 ti,index-starts-at-one;
 259                 ti,invert-autoidle-bit;
 260         };
 261
 262         dpll_ddr_ck: dpll_ddr_ck {
 263                 #clock-cells = <0>;
 264                 compatible = "ti,am3-dpll-clock";
 265                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 266                 reg = <0x2da0>, <0x2da4>, <0x2dac>;
 267         };
 268
 269         dpll_ddr_m2_ck: dpll_ddr_m2_ck {
 270                 #clock-cells = <0>;
 271                 compatible = "ti,divider-clock";
 272                 clocks = <&dpll_ddr_ck>;
 273                 ti,max-div = <31>;
 274                 ti,autoidle-shift = <8>;
 275                 reg = <0x2db0>;
 276                 ti,index-starts-at-one;
 277                 ti,invert-autoidle-bit;
 278         };
 279
 280         dpll_disp_ck: dpll_disp_ck {
 281                 #clock-cells = <0>;
 282                 compatible = "ti,am3-dpll-clock";
 283                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 284                 reg = <0x2e20>, <0x2e24>, <0x2e2c>;
 285         };
 286
 287         dpll_disp_m2_ck: dpll_disp_m2_ck {
 288                 #clock-cells = <0>;
 289                 compatible = "ti,divider-clock";
 290                 clocks = <&dpll_disp_ck>;
 291                 ti,max-div = <31>;
 292                 ti,autoidle-shift = <8>;
 293                 reg = <0x2e30>;
 294                 ti,index-starts-at-one;
 295                 ti,invert-autoidle-bit;
 296                 ti,set-rate-parent;
 297         };
 298
 299         dpll_per_ck: dpll_per_ck {
 300                 #clock-cells = <0>;
 301                 compatible = "ti,am3-dpll-j-type-clock";
 302                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 303                 reg = <0x2de0>, <0x2de4>, <0x2dec>;
 304         };
 305
 306         dpll_per_m2_ck: dpll_per_m2_ck {
 307                 #clock-cells = <0>;
 308                 compatible = "ti,divider-clock";
 309                 clocks = <&dpll_per_ck>;
 310                 ti,max-div = <127>;
 311                 ti,autoidle-shift = <8>;
 312                 reg = <0x2df0>;
 313                 ti,index-starts-at-one;
 314                 ti,invert-autoidle-bit;
 315         };
 316
 317         dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
 318                 #clock-cells = <0>;
 319                 compatible = "fixed-factor-clock";
 320                 clocks = <&dpll_per_m2_ck>;
 321                 clock-mult = <1>;
 322                 clock-div = <4>;
 323         };
 324
 325         dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
 326                 #clock-cells = <0>;
 327                 compatible = "fixed-factor-clock";
 328                 clocks = <&dpll_per_m2_ck>;
 329                 clock-mult = <1>;
 330                 clock-div = <4>;
 331         };
 332
 333         clk_24mhz: clk_24mhz {
 334                 #clock-cells = <0>;
 335                 compatible = "fixed-factor-clock";
 336                 clocks = <&dpll_per_m2_ck>;
 337                 clock-mult = <1>;
 338                 clock-div = <8>;
 339         };
 340
 341         clkdiv32k_ck: clkdiv32k_ck {
 342                 #clock-cells = <0>;
 343                 compatible = "fixed-factor-clock";
 344                 clocks = <&clk_24mhz>;
 345                 clock-mult = <1>;
 346                 clock-div = <732>;
 347         };
 348
 349         clkdiv32k_ick: clkdiv32k_ick {
 350                 #clock-cells = <0>;
 351                 compatible = "ti,gate-clock";
 352                 clocks = <&clkdiv32k_ck>;
 353                 ti,bit-shift = <8>;
 354                 reg = <0x2a38>;
 355         };
 356
 357         sysclk_div: sysclk_div {
 358                 #clock-cells = <0>;
 359                 compatible = "fixed-factor-clock";
 360                 clocks = <&dpll_core_m4_ck>;
 361                 clock-mult = <1>;
 362                 clock-div = <1>;
 363         };
 364
 365         pruss_ocp_gclk: pruss_ocp_gclk {
 366                 #clock-cells = <0>;
 367                 compatible = "ti,mux-clock";
 368                 clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
 369                 reg = <0x4248>;
 370         };
 371
 372         clk_32k_tpm_ck: clk_32k_tpm_ck {
 373                 #clock-cells = <0>;
 374                 compatible = "fixed-clock";
 375                 clock-frequency = <32768>;
 376         };
 377
 378         timer1_fck: timer1_fck {
 379                 #clock-cells = <0>;
 380                 compatible = "ti,mux-clock";
 381                 clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
 382                 reg = <0x4200>;
 383         };
 384
 385         timer2_fck: timer2_fck {
 386                 #clock-cells = <0>;
 387                 compatible = "ti,mux-clock";
 388                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 389                 reg = <0x4204>;
 390         };
 391
 392         timer3_fck: timer3_fck {
 393                 #clock-cells = <0>;
 394                 compatible = "ti,mux-clock";
 395                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 396                 reg = <0x4208>;
 397         };
 398
 399         timer4_fck: timer4_fck {
 400                 #clock-cells = <0>;
 401                 compatible = "ti,mux-clock";
 402                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 403                 reg = <0x420c>;
 404         };
 405
 406         timer5_fck: timer5_fck {
 407                 #clock-cells = <0>;
 408                 compatible = "ti,mux-clock";
 409                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 410                 reg = <0x4210>;
 411         };
 412
 413         timer6_fck: timer6_fck {
 414                 #clock-cells = <0>;
 415                 compatible = "ti,mux-clock";
 416                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 417                 reg = <0x4214>;
 418         };
 419
 420         timer7_fck: timer7_fck {
 421                 #clock-cells = <0>;
 422                 compatible = "ti,mux-clock";
 423                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 424                 reg = <0x4218>;
 425         };
 426
 427         wdt1_fck: wdt1_fck {
 428                 #clock-cells = <0>;
 429                 compatible = "ti,mux-clock";
 430                 clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
 431                 reg = <0x422c>;
 432         };
 433
 434         l3_gclk: l3_gclk {
 435                 #clock-cells = <0>;
 436                 compatible = "fixed-factor-clock";
 437                 clocks = <&dpll_core_m4_ck>;
 438                 clock-mult = <1>;
 439                 clock-div = <1>;
 440         };
 441
 442         dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
 443                 #clock-cells = <0>;
 444                 compatible = "fixed-factor-clock";
 445                 clocks = <&sysclk_div>;
 446                 clock-mult = <1>;
 447                 clock-div = <2>;
 448         };
 449
 450         l4hs_gclk: l4hs_gclk {
 451                 #clock-cells = <0>;
 452                 compatible = "fixed-factor-clock";
 453                 clocks = <&dpll_core_m4_ck>;
 454                 clock-mult = <1>;
 455                 clock-div = <1>;
 456         };
 457
 458         l3s_gclk: l3s_gclk {
 459                 #clock-cells = <0>;
 460                 compatible = "fixed-factor-clock";
 461                 clocks = <&dpll_core_m4_div2_ck>;
 462                 clock-mult = <1>;
 463                 clock-div = <1>;
 464         };
 465
 466         l4ls_gclk: l4ls_gclk {
 467                 #clock-cells = <0>;
 468                 compatible = "fixed-factor-clock";
 469                 clocks = <&dpll_core_m4_div2_ck>;
 470                 clock-mult = <1>;
 471                 clock-div = <1>;
 472         };
 473
 474         cpsw_125mhz_gclk: cpsw_125mhz_gclk {
 475                 #clock-cells = <0>;
 476                 compatible = "fixed-factor-clock";
 477                 clocks = <&dpll_core_m5_ck>;
 478                 clock-mult = <1>;
 479                 clock-div = <2>;
 480         };
 481
 482         cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
 483                 #clock-cells = <0>;
 484                 compatible = "ti,mux-clock";
 485                 clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
 486                 reg = <0x4238>;
 487         };
 488
 489         dpll_clksel_mac_clk: dpll_clksel_mac_clk {
 490                 #clock-cells = <0>;
 491                 compatible = "ti,divider-clock";
 492                 clocks = <&dpll_core_m5_ck>;
 493                 reg = <0x4234>;
 494                 ti,bit-shift = <2>;
 495                 ti,dividers = <2>, <5>;
 496         };
 497
 498         clk_32k_mosc_ck: clk_32k_mosc_ck {
 499                 #clock-cells = <0>;
 500                 compatible = "fixed-clock";
 501                 clock-frequency = <32768>;
 502         };
 503
 504         gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
 505                 #clock-cells = <0>;
 506                 compatible = "ti,mux-clock";
 507                 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
 508                 reg = <0x4240>;
 509         };
 510
 511         gpio0_dbclk: gpio0_dbclk {
 512                 #clock-cells = <0>;
 513                 compatible = "ti,gate-clock";
 514                 clocks = <&gpio0_dbclk_mux_ck>;
 515                 ti,bit-shift = <8>;
 516                 reg = <0x2b68>;
 517         };
 518
 519         gpio1_dbclk: gpio1_dbclk {
 520                 #clock-cells = <0>;
 521                 compatible = "ti,gate-clock";
 522                 clocks = <&clkdiv32k_ick>;
 523                 ti,bit-shift = <8>;
 524                 reg = <0x8c78>;
 525         };
 526
 527         gpio2_dbclk: gpio2_dbclk {
 528                 #clock-cells = <0>;
 529                 compatible = "ti,gate-clock";
 530                 clocks = <&clkdiv32k_ick>;
 531                 ti,bit-shift = <8>;
 532                 reg = <0x8c80>;
 533         };
 534
 535         gpio3_dbclk: gpio3_dbclk {
 536                 #clock-cells = <0>;
 537                 compatible = "ti,gate-clock";
 538                 clocks = <&clkdiv32k_ick>;
 539                 ti,bit-shift = <8>;
 540                 reg = <0x8c88>;
 541         };
 542
 543         gpio4_dbclk: gpio4_dbclk {
 544                 #clock-cells = <0>;
 545                 compatible = "ti,gate-clock";
 546                 clocks = <&clkdiv32k_ick>;
 547                 ti,bit-shift = <8>;
 548                 reg = <0x8c90>;
 549         };
 550
 551         gpio5_dbclk: gpio5_dbclk {
 552                 #clock-cells = <0>;
 553                 compatible = "ti,gate-clock";
 554                 clocks = <&clkdiv32k_ick>;
 555                 ti,bit-shift = <8>;
 556                 reg = <0x8c98>;
 557         };
 558
 559         mmc_clk: mmc_clk {
 560                 #clock-cells = <0>;
 561                 compatible = "fixed-factor-clock";
 562                 clocks = <&dpll_per_m2_ck>;
 563                 clock-mult = <1>;
 564                 clock-div = <2>;
 565         };
 566
 567         gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
 568                 #clock-cells = <0>;
 569                 compatible = "ti,mux-clock";
 570                 clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
 571                 ti,bit-shift = <1>;
 572                 reg = <0x423c>;
 573         };
 574
 575         gfx_fck_div_ck: gfx_fck_div_ck {
 576                 #clock-cells = <0>;
 577                 compatible = "ti,divider-clock";
 578                 clocks = <&gfx_fclk_clksel_ck>;
 579                 reg = <0x423c>;
 580                 ti,max-div = <2>;
 581         };
 582
 583         disp_clk: disp_clk {
 584                 #clock-cells = <0>;
 585                 compatible = "ti,mux-clock";
 586                 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
 587                 reg = <0x4244>;
 588                 ti,set-rate-parent;
 589         };
 590
 591         dpll_extdev_ck: dpll_extdev_ck {
 592                 #clock-cells = <0>;
 593                 compatible = "ti,am3-dpll-clock";
 594                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 595                 reg = <0x2e60>, <0x2e64>, <0x2e6c>;
 596         };
 597
 598         dpll_extdev_m2_ck: dpll_extdev_m2_ck {
 599                 #clock-cells = <0>;
 600                 compatible = "ti,divider-clock";
 601                 clocks = <&dpll_extdev_ck>;
 602                 ti,max-div = <127>;
 603                 ti,autoidle-shift = <8>;
 604                 reg = <0x2e70>;
 605                 ti,index-starts-at-one;
 606                 ti,invert-autoidle-bit;
 607         };
 608
 609         mux_synctimer32k_ck: mux_synctimer32k_ck {
 610                 #clock-cells = <0>;
 611                 compatible = "ti,mux-clock";
 612                 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
 613                 reg = <0x4230>;
 614         };
 615
 616         synctimer_32kclk: synctimer_32kclk {
 617                 #clock-cells = <0>;
 618                 compatible = "ti,gate-clock";
 619                 clocks = <&mux_synctimer32k_ck>;
 620                 ti,bit-shift = <8>;
 621                 reg = <0x2a30>;
 622         };
 623
 624         timer8_fck: timer8_fck {
 625                 #clock-cells = <0>;
 626                 compatible = "ti,mux-clock";
 627                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 628                 reg = <0x421c>;
 629         };
 630
 631         timer9_fck: timer9_fck {
 632                 #clock-cells = <0>;
 633                 compatible = "ti,mux-clock";
 634                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 635                 reg = <0x4220>;
 636         };
 637
 638         timer10_fck: timer10_fck {
 639                 #clock-cells = <0>;
 640                 compatible = "ti,mux-clock";
 641                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 642                 reg = <0x4224>;
 643         };
 644
 645         timer11_fck: timer11_fck {
 646                 #clock-cells = <0>;
 647                 compatible = "ti,mux-clock";
 648                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 649                 reg = <0x4228>;
 650         };
 651
 652         cpsw_50m_clkdiv: cpsw_50m_clkdiv {
 653                 #clock-cells = <0>;
 654                 compatible = "fixed-factor-clock";
 655                 clocks = <&dpll_core_m5_ck>;
 656                 clock-mult = <1>;
 657                 clock-div = <1>;
 658         };
 659
 660         cpsw_5m_clkdiv: cpsw_5m_clkdiv {
 661                 #clock-cells = <0>;
 662                 compatible = "fixed-factor-clock";
 663                 clocks = <&cpsw_50m_clkdiv>;
 664                 clock-mult = <1>;
 665                 clock-div = <10>;
 666         };
 667
 668         dpll_ddr_x2_ck: dpll_ddr_x2_ck {
 669                 #clock-cells = <0>;
 670                 compatible = "ti,am3-dpll-x2-clock";
 671                 clocks = <&dpll_ddr_ck>;
 672         };
 673
 674         dpll_ddr_m4_ck: dpll_ddr_m4_ck {
 675                 #clock-cells = <0>;
 676                 compatible = "ti,divider-clock";
 677                 clocks = <&dpll_ddr_x2_ck>;
 678                 ti,max-div = <31>;
 679                 ti,autoidle-shift = <8>;
 680                 reg = <0x2db8>;
 681                 ti,index-starts-at-one;
 682                 ti,invert-autoidle-bit;
 683         };
 684
 685         dpll_per_clkdcoldo: dpll_per_clkdcoldo {
 686                 #clock-cells = <0>;
 687                 compatible = "ti,fixed-factor-clock";
 688                 clocks = <&dpll_per_ck>;
 689                 ti,clock-mult = <1>;
 690                 ti,clock-div = <1>;
 691                 ti,autoidle-shift = <8>;
 692                 reg = <0x2e14>;
 693                 ti,invert-autoidle-bit;
 694         };
 695
 696         dll_aging_clk_div: dll_aging_clk_div {
 697                 #clock-cells = <0>;
 698                 compatible = "ti,divider-clock";
 699                 clocks = <&sys_clkin_ck>;
 700                 reg = <0x4250>;
 701                 ti,dividers = <8>, <16>, <32>;
 702         };
 703
 704         div_core_25m_ck: div_core_25m_ck {
 705                 #clock-cells = <0>;
 706                 compatible = "fixed-factor-clock";
 707                 clocks = <&sysclk_div>;
 708                 clock-mult = <1>;
 709                 clock-div = <8>;
 710         };
 711
 712         func_12m_clk: func_12m_clk {
 713                 #clock-cells = <0>;
 714                 compatible = "fixed-factor-clock";
 715                 clocks = <&dpll_per_m2_ck>;
 716                 clock-mult = <1>;
 717                 clock-div = <16>;
 718         };
 719
 720         vtp_clk_div: vtp_clk_div {
 721                 #clock-cells = <0>;
 722                 compatible = "fixed-factor-clock";
 723                 clocks = <&sys_clkin_ck>;
 724                 clock-mult = <1>;
 725                 clock-div = <2>;
 726         };
 727
 728         usbphy_32khz_clkmux: usbphy_32khz_clkmux {
 729                 #clock-cells = <0>;
 730                 compatible = "ti,mux-clock";
 731                 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
 732                 reg = <0x4260>;
 733         };
 734
 735         usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k {
 736                 #clock-cells = <0>;
 737                 compatible = "ti,gate-clock";
 738                 clocks = <&usbphy_32khz_clkmux>;
 739                 ti,bit-shift = <8>;
 740                 reg = <0x2a40>;
 741         };
 742
 743         usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
 744                 #clock-cells = <0>;
 745                 compatible = "ti,gate-clock";
 746                 clocks = <&usbphy_32khz_clkmux>;
 747                 ti,bit-shift = <8>;
 748                 reg = <0x2a48>;
 749         };
 750
 751         usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m {
 752                 #clock-cells = <0>;
 753                 compatible = "ti,gate-clock";
 754                 clocks = <&dpll_per_clkdcoldo>;
 755                 ti,bit-shift = <8>;
 756                 reg = <0x8a60>;
 757         };
 758
 759         usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
 760                 #clock-cells = <0>;
 761                 compatible = "ti,gate-clock";
 762                 clocks = <&dpll_per_clkdcoldo>;
 763                 ti,bit-shift = <8>;
 764                 reg = <0x8a68>;
 765         };
 766 };